NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
Recommended Substitutions:
8-Bit Serial-Input DMOS Power Driver
A6B595
For existing customer transition, and for new customers or new appli-
cations, contact Allegro Sales.
Date of status change: May 3, 2010
Deadline for receipt of LAST TIME BUY orders: October 29, 2010
This part is in production but has been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Last T ime Buy
Description
The A6B595 combines an 8-bit CMOS shift register and
accompanying data latches, control circuitry, and DMOS
power driver outputs. Power driver applications include
relays, solenoids, and other medium-current or high-voltage
peripheral power loads.
The serial-data input, CMOS shift register and latches allow
direct interfacing with microprocessor-based systems. Serial-
data input rates are over 5 MHz. Use with TTL may require
appropriate pull-up resistors to ensure an input logic high.
A CMOS serial-data output enables cascade connections in
applications requiring additional drive lines. Similar devices
with reduced rDS(on) are available as the A6595.
The A6B595 DMOS open-drain outputs are capable of sinking
up to 500 mA. All of the output drivers are disabled (the DMOS
sink drivers turned off) by the OUTPUT ENABLE input high.
Copper lead frames, reduced supply current requirements, and
low on-state resistance allow both devices to sink 150 mA from
all outputs continuously, to ambient temperatures over 85°C.
The A6B595 is furnished in a 20-pin dual in-line plastic package
and a 20-pin wide-body, small-outline plastic package (SOICW)
with gull-wing leads. The Pb (lead) free versions (suffix -T)
have 100% matte tin leadframe plating.
26185.122G
Features and Benefits
▪ 50 V minimum output clamp voltage
▪ 150 mA output current (all outputs simultaneously)
▪ 5 typical rDS(on)
▪ Low power consumption
▪ Replacement for TPIC6B595N and TPIC6B595DW
8-Bit Serial-Input DMOS Power Driver
Packages:
Functional Block Diagram
Not to scale
A6B595
18-pin DIP
(A package)
20-pin SOICW
(LW package)
Grounds (terminals 10, 11, and 19) must be connected together externally.
8-Bit Serial-Input DMOS Power Driver
A6B595
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Logic Supply Voltage VDD 7V
Output Voltage VO50 V
Input Voltage Range VI–0.3 to 7.0 V
Output Drain Current IOContinuous; each output, all outputs on 150 mA
IOM Peak; pulse duration 100 μs, duty cycle 2% 500 mA
Single-Pulse Avalanche Energy EAS 30 mJ
Operating Ambient Temperature TARange K –40 to 85 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –65 to 150 ºC
Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high
static electrical charges.
Selection Guide
Part Number Package Packing
A6B595KA-T 18-pin DIP 18 pieces per tube
A6B595KLWTR-T 20-pin SOICW 1000 pieces per reel
Thermal Characteristics
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA
Package A, 1-layer PCB with copper limited to solder pads 65 ºC/W
Package LW, 1-layer PCB with copper limited to solder pads 90 ºC/W
*Additional thermal information available on the Allegro website
50 75 100 125 150
2.5
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN oC
2.0
1.5
1.0
25
Dwg. GS-004A
SUFFIX 'A', R = 65oC/W
QJA
SUFFIX 'LW', R = 90oC/W
QJA
8-Bit Serial-Input DMOS Power Driver
A6B595
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Note that the A package (DIP) and the LW package
(SOIC) are electrically identical and share a common
terminal number assignment.
PIN-OUT DIAGRAM
GROUND
1
2
3
8
9
13
14
15
16
17
19
4
5
6
7
12
18
20
SERIAL
DATA OUT
SERIAL
DATA IN
LOGIC
SUPPLY V
DD
STROBE
GROUND
CLOCKCLK
ST
OUT
7
OUT
6
OUT
5
Dwg. PP-029-12
OUT
0
OUT
1
OUT
2
OUT
3
OUT
4
10 11
NO
CONNECTION NO
CONNECTION
NCNC
OUTPUT
ENABLE OE
REGISTER
CLEAR
GROUND
CLR
TERMINAL DESCRIPTIONS
Terminal No. Terminal Name Function
1 NC No internal connection.
2 LOGIC SUPPLY (VDD) The logic supply voltage (typically 5 V).
3 SERIAL DATA IN Serial-data input to the shift-register.
4-7 OUT0-3 Current-sinking, open-drain DMOS output terminals.
8 CLEAR When (active) low, the registers are cleared (set low).
9 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
10 GROUND Reference terminal for output voltage measurements (OUT0-3).
11 GROUND Reference terminal for output voltage measurements (OUT0-7).
12 STROBE Data strobe input terminal; shift register data is latched on rising edge.
13 CLOCK Clock input terminal for data shift on rising edge.
14-17 OUT4-7 Current-sinking, open-drain DMOS output terminals.
18 SERIAL DATA OUT CMOS serial-data output to the following shift register.
19 GROUND Reference terminal for input voltage measurements.
20 NC No internal connection.
NOTE — Grounds (terminals 10, 11, and 19) must be connected together externally.
8-Bit Serial-Input DMOS Power Driver
A6B595
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TRUTH TABLE
Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Output
Input Input I0 I
1 I
2 ... I6 I
7 Output Strobe I0 I
1 I
2 ... I6 I
7 Enable I0 I
1 I
2 … I6 I
7
H H R0 R
1 … R5 R
6 R
6
L L R0 R
1 … R5 R
6 R
6
X R0 R
1 R
2 … R6 R
7 R
7
X X X … X X X — R0 R1 R
2 … R6 R
7
P
0 P
1 P
2 … P6 P
7 P
7 P
0 P
1 P
2 … P6 P
7 L P0 P
1 P
2 … P6 P
7
X X X … X X H H H H … H H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
SERIAL DATA OUT
LOGIC INPUTS DMOS POWER DRIVER OUTPUT
RECOMMENDED OPERATING CONDITIONS
over operating temperature range
Logic Supply Voltage Range, VDD ................ 4.5 V to 5.5 V
High-Level Input Voltage, VIH ............................ ≥ 0.85VDD
Low-level input voltage, VIL ................................. ≤ 0.15VDD
8-Bit Serial-Input DMOS Power Driver
A6B595
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Breakdown V(BR)DSX I
O = 1 mA 50 — — V
Voltage
Off-State Output IDSX V
O = 40 V, VDD = 5.5 V — 0.1 5.0 μA
Current V
O = 40 V, VDD = 5.5 V, TA = 125°C — 0.15 8.0 μA
Static Drain-Source rDS(on) I
O = 100 mA, VDD = 4.5 V — 4.2 5.7 Ω
On-State Resistance I
O = 100 mA, VDD = 4.5 V, TA = 125°C — 6.8 9.5 Ω
I
O = 350 mA, VDD = 4.5 V (see note) — 5.5 8.0 Ω
Nominal Output ION V
DS(on) = 0.5 V, TA = 85°C — 90 — mA
Current
Logic Input Current IIH VI = VDD = 5.5 V — — 1.0 μA
I
IL VI = 0, VDD = 5.5 V — — -1.0 μA
SERIAL-DATA VOH I
OH = -20 μA, VDD = 4.5 V 4.4 4.49 — V
Output Voltage I
OH = -4 mA, VDD = 4.5 V 4.0 4.2 — V
V
OL I
OL = 20 μA, VDD = 4.5 V — 0.005 0.1 V
I
OL = 4 mA, VDD = 4.5 V — 0.3 0.5 V
Prop. Delay Time tPLH I
O = 100 mA, CL = 30 pF — 150 — ns
t
PHL I
O = 100 mA, CL = 30 pF — 90 — ns
Output Rise Time tr I
O = 100 mA, CL = 30 pF — 200 — ns
Output Fall Time tf I
O = 100 mA, CL = 30 pF — 200 — ns
Supply Current IDD(OFF) V
DD = 5.5 V, Outputs OFF — 20 100 μA
I
DD(ON) V
DD = 5.5 V, Outputs ON — 150 300 μA
I
DD(fclk) f
clk = 5 MHz, CL = 30 pF, Outputs OFF — 0.4 5.0 mA
Typical Data is at VDD = 5 V and is for design information only.
NOTE — Pulse test, duration 100 μs, duty cycle 2%.
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif 10 ns (unless otherwise
specifi ed).
8-Bit Serial-Input DMOS Power Driver
A6B595
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) .......................................... 20 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 20 ns
C. Clock Pulse Width, tw(CLK) ............................................. 40 ns
D. Time Between Clock Activation
and Strobe, tsu(ST) ....................................................... 50 ns
E. Strobe Pulse Width, tw(ST) ............................................... 50 ns
F. Output Enable Pulse Width, tw(OE) ................................ 4.5 μs
NOTE – Timing is representative of a 12.5 MHz clock.
Higher speeds are attainable.
Serial data present at the input is transferred to the shift reg-
ister on the rising edge of the CLOCK input pulse. On succeed-
ing CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT.
Information present at any register is transferred to the
respective latch on the rising edge of the STROBE input pulse
(serial-to-parallel conversion).
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
8-Bit Serial-Input DMOS Power Driver
A6B595
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TEST CIRCUITS
Single-Pulse Avalanche Energy Test Circuit and
Waveforms
EAS = IAS x V(BR)DSX x tAV/2
LOGIC SYMBOL
8-Bit Serial-Input DMOS Power Driver
A6B595
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package A, 18-Pin DIP
Package LW, 20-Pin SOICW
5.33 MAX
0.46 ±0.12
22.86 ±0.51
6.35 +0.76
–0.25
3.30 +0.51
–0.38
10.92 +0.38
–0.25
1.52 +0.25
–0.38
7.62
2.54
0.25 +0.10
–0.05
C
SEATING
PLANE
21
18
A
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
All dimensions nominal, not for tooling use
(reference JEDEC MS-001 AC)
Dimensions in inches
21
20
21
20
A
2.65 MAX
C
SEATING
PLANE
C0.10
20X
ATerminal #1 mark area
GAUGE PLANE
SEATING PLANE B
2.25
0.65
9.50
1.27
PCB Layout Reference View
For Reference Only
Dimensions in millimeters
(Reference JEDEC MS-013 AC)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
BReference pad layout (reference IPC SOIC127P1030X265-20M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
1.27
0.25
0.20 ±0.10
0.41 ±0.10
12.80±0.20
10.30±0.33
7.50±0.10
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
8-Bit Serial-Input DMOS Power Driver
A6B595
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©1999-2009, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
