1
FEATURES APPLICATIONS
DESCRIPTION
1 Fm
SD
MuteControl
PVCCL
TPA3124D2
SIMPLIFIED APPLICATIONCIRCUIT
PVCCR
VCLAMP
GAIN1
BYPASS
1 Fm
1 Fm
0.22 Fm
AGND
LeftChannel
RightChannel
10Vto26V 10Vto26V
4-StepGainControl
ShutdownControl
LIN
RIN
BSR
BSL
PGNDR
PGNDL
0.22 Fm
33 Hm
33 Hm470 Fm
0.22 Fm
1 Fm
470 Fm
GAIN0
AVCC
MUTE
ROUT
LOUT
S0267-02
0.22 Fm
TPA3124D2
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........................................................................................................................................................................................................ SLOS578 – MAY 2008
15-W STEREO CLASS-D AUDIO POWER AMPLIFIER
•Flat Panel Televisions234
•10-W/Ch Into an 8- ΩLoad From a 24-V Supply
•DLP
®
TVs•15-W/Ch into a 4- ΩLoad from a 22-V Supply
•CRT TVs•30-W/Ch into a 8- ΩLoad from a 22-V Supply
•Powered Speakers•Operates From 10 V to 26 V•Can Run From +24 V LCD Backlight Supply•Efficient Class-D Operation Eliminates Need
The TPA3124D2 is a 15-W (per channel), efficient,for Heat Sinks
class-D audio power amplifier for driving stereo•Four Selectable, Fixed-Gain Settings
speakers in a single-ended configuration; or, a mono•Internal Oscillator (No External Components
speaker in a bridge-tied-load configuration. TheTPA3124D2 can drive stereo speakers as low as 4 Ω.Required)
The efficiency of the TPA3124D2 eliminates the need•Single-Ended Analog Inputs
for an external heat sink when playing music.•Thermal and Short-Circuit Protection With
The gain of the amplifier is controlled by two gainAuto Recovery
select pins. The gain selections are 20, 26, 32, and•Space-Saving Surface Mount 24-Pin TSSOP
36 dB.Package
The patented start-up and shutdown sequences•Advanced Power-Off Pop Reduction
minimize pop noise in the speakers without additionalcircuitry.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DLP is a registered trademark of Texas Instruments.3System Two, Audio Precision are trademarks of Audio Precision, Inc.4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
1
2
3
4
5
6
7
8
9
10
11
12
PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR
24
23
22
21
20
19
18
17
16
15
14
13
PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
PWP (TSSOP) PACKAGE
(TOP VIEW)
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O/P DESCRIPTION24-PINNAME
(PWP)
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance toSD 2 I
AVCCRIN 6 I Audio input for right channelLIN 5 I Audio input for left channelGAIN0 18 I Gain select least-significant bit. TTL logic levels with compliance to AVCCGAIN1 17 I Gain select most-significant bit. TTL logic levels with compliance to AVCCMute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =MUTE 4 I
outputs enabled). TTL logic levels with compliance to AVCCBSL 21 I/O Bootstrap I/O for left channelPVCCL 1, 3 P Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCCLOUT 22 O Class-D -H-bridge positive output for left channelPGNDL 23, 24 P Power ground for left-channel H-bridgeVCLAMP 11 P Internally generated voltage supply for bootstrap capacitorsBSR 16 I/O Bootstrap I/O for right channelROUT 15 O Class-D -H-bridge negative output for right channelPGNDR 13, 14 P Power ground for right-channel H-bridge.PVCCR 10, 12 P Power supply for right-channel H-bridge, not connected to PVCCL or AVCCAGND 9 P Analog ground for digital/analog cells in coreAGND 8 P Analog ground for analog cells in coreReference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time viaBYPASS 7 O
external capacitor sizing.AVCC 19, 20 P High-voltage analog power supply. Not internally connected to PVCCR or PVCCLConnect to ground. Thermal pad should be soldered down on all applications to secure theThermal pad Die pad P
device properly to the printed wiring board.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
TPA3124D2
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........................................................................................................................................................................................................ SLOS578 – MAY 2008
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
V
CC
Supply voltage AVCC, PVCC – 0.3 to 30 VV
I
Logic input voltage SD, MUTE, GAIN0, GAIN1 – 0.3 to V
CC
+ 0.3 VV
IN
Analog input voltage RIN, LIN – 0.3 to 7 VContinuous total power dissipation See Dissipation Rating TableT
A
Operating free-air temperature range – 40 to 85 °CT
J
Operating junction temperature range – 40 to 150 °CT
stg
Storage temperature range – 65 to 150 °CSE Output Configuration 3.2R
L
Load resistance (minimum value) ΩBTL Output Configuration 6.4Human body model (all pins) ± 2 kVESD Electrostatic Discharge
Charged-device model (all
± 500 Vpins)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE
(1) (2)
T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °C
24-pin TSSOP 4.16 W 33.3 mW/ °C 2.67 W 2.16 W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad mustbe soldered to a thermal land on the printed-circuit board. See the PowerPAD Thermally Enhanced Package application note(SLMA002 ).
MIN MAX UNIT
V
CC
Supply voltage PVCC, AVCC 10 26 VV
IH
High-level input voltage SD, MUTE, GAIN0, GAIN1 2 VV
IL
Low-level input voltage SD, MUTE, GAIN0, GAIN1 0.8 VSD, V
I
= V
CC
, V
CC
= 30 V 125I
IH
High-level input current MUTE, V
I
= V
CC
, V
CC
= 30 V 125 µAGAIN0, GAIN1, V
I
= V
CC
, V
CC
= 24 V 125SD, V
I
= 0, V
CC
= 30 V 1I
IL
Low-level input current MUTE, V
I
= 0 V, V
CC
= 30 V 1 µAGAIN0, GAIN1, V
I
= 0 V, V
CC
= 24 V 1T
A
Operating free-air temperature – 40 85 °C
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DC CHARACTERISTICS
AC CHARACTERISTICS
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................
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T
A
= 25 °C, V
CC
= 24 V, R
L
=8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage| V
OS
| (measured differentially in BTL V
I
= 0 V, A
V
= 36 dB 7.5 50 mVmode as shown in Figure 36 )V
(BYPASS)
Bypass output voltage No load AVCC/8 VI
CC(q)
Quiescent supply current SD = 2 V, MUTE = 0 V, no load 16 30 mAI
CC(q)
Quiescent supply current in
MUTE = 0.8 V, no load 16 mAmute modeI
CC(q)
Quiescent supply current in
SD = 0.8 V, no load 0.39 1 mAshutdown moder
DS(on)
Drain-source on-state 450210 m Ωresistance
GAIN0 = 0.8 V 18 20 22GAIN1 = 0.8 V
GAIN0 = 2 V 24 26 28G Gain dBGAIN0 = 0.8 V 30 32 34GAIN = 2 V
GAIN0 = 2 V 34 36 38Mute attenuation V
I
= 1 Vrms – 80 dB
T
A
= 25 °C, V
CC
= 24 V, R
L
= 8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
CC
= 24, V
ripple
= 200 mV
PP
100 Hz – 48ksvr Supply ripple rejection dBGain = 20 dB
1 kHz – 52Output power at 1% THD+N V
CC
= 24 V, f = 1 kHz 8P
O
WOutput power at 10% THD+N V
CC
= 24 V, f = 1 kHz 10Total harmonic distortion + f = 1 kHz, P
O
= 5 W 0.04%THD+N
noise
125 µV20 Hz to 22 kHz, A-weighted filter,V
n
Output integrated noise floor
Gain = 20 dB
– 78 dBVCrosstalk P
O
= 1 W, f = 1 kHz; gain = 20 dB – 70 dBMax output at THD+N < 1%, f = 1 kHz,SNR Signal-to-noise ratio – 92 dBgain = 20 dBThermal trip point 150 °CThermal hysteresis 30 °Cf
OSC
Oscillator frequency 250 300 350 kHz
Δt mute Mute delay Time from mute input switches high until 30 µsecoutputs muted
Δt unmute Unmute delay Time from mute input switches low until 120 msecoutputs unmuted
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FUNCTIONAL BLOCK DIAGRAM
LS
HS
OSC/RAMP
BYPASS
AVDDAVCC
LIN
RIN
MUTE
BYPASS
GAIN1
GAIN0
SD
BSL
PVCCL
LOUT
PGNDL
VCLAMP
BSR
PVCCR
ROUT
PGNDR
VCLAMP
AVDD
AVDD
AVDD/2
AVDD AVDD
AVDD/2
REGULATOR
AGND
+
+
–
–
CONTROL
BIAS
THERMAL
MUTE
CONTROL
AV
CONTROL
SC
DETECT
SC
DETECT
LS
HS
VCLAMP
TPA3124D2
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TYPICAL CHARACTERISTICS
f − Frequency − Hz
20
VCC = 12 V
RL = 4 Ω (SE)
Gain = 20 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G001
1
PO = 0.5 W
PO = 2.5 W
0.01
PO = 1 W
f − Frequency − Hz
20
VCC = 18 V
RL = 6 Ω (SE)
Gain = 20 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G002
1
PO = 0.5 W
PO = 2.5 W
0.01
PO = 1 W
f − Frequency − Hz
20
VCC = 18 V
RL = 8 Ω (SE)
Gain = 20 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G003
1
PO = 2.5 W
0.01 PO = 1 W
f − Frequency − Hz
20
VCC = 24 V
RL = 8 Ω (SE)
Gain = 20 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G004
1
PO = 1 W
PO = 5 W
0.01
PO = 2.5 W
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................
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All tests are made at frequency = 1 kHz unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY FREQUENCY
Figure 1. Figure 2.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY FREQUENCY
Figure 3. Figure 4.
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PO − Output Power − W
0.01
RL = 4 Ω (SE)
Gain = 20 dB
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G005
1
VCC = 12 V
PO − Output Power − W
0.01
RL = 6 Ω (SE)
Gain = 20 dB
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G006
1
VCC = 12 V
VCC = 18 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
f − Frequency − Hz
Crosstalk − dB
G008
20 100 1k 10k 20k
Left to Right
Right to Left
VCC = 12 V
VO = 1 V rms
RL = 4 Ω (SE)
PO = 0.25 W
Gain = 20 dB
PO − Output Power − W
0.01
RL = 8 Ω (SE)
Gain = 20 dB
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G007
1
VCC = 12 V
VCC = 18 V
VCC = 24 V
TPA3124D2
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........................................................................................................................................................................................................ SLOS578 – MAY 2008
TYPICAL CHARACTERISTICS (continued)All tests are made at frequency = 1 kHz unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsOUTPUT POWER OUTPUT POWER
Figure 5. Figure 6.
TOTAL HARMONIC DISTORTION + NOISE CROSSTALKvs vsOUTPUT POWER FREQUENCY
Figure 7. Figure 8.
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−100
−90
−80
−70
−60
−50
−40
−30
−20
f − Frequency − Hz
Crosstalk − dB
G009
20 100 1k 10k 20k
Left to Right
Right to Left
VCC = 18 V
VO = 1 V rms
RL = 8 Ω (SE)
PO = 0.125 W
Gain = 20 dB
−100
−90
−80
−70
−60
−50
−40
−30
−20
f − Frequency − Hz
Crosstalk − dB
G010
20 100 1k 10k 20k
Left to Right
Right to Left
VCC = 24 V
VO = 1 V rms
RL = 8 Ω (SE)
PO = 0.125 W
Gain = 20 dB
f − Frequency − Hz
Phase − °
20 100 1k 100k10k
G011
600
500
400
300
200
100
0
−100
−200
0
5
10
15
20
25
30
35
40
Gain − dB
Phase
Gain
VCC = 24 V
RL = 4 Ω (SE)
Gain = 20 dB
Lfilt = 22 µH
Cfilt = 0.68 µF
Cdc = 1000 µF
f − Frequency − Hz
Phase − °
20 100 1k 100k10k
G012
600
500
400
300
200
100
0
−100
−200
0
5
10
15
20
25
30
35
40
Gain − dB
Phase
Gain
VCC = 24 V
RL = 8 Ω (SE)
Gain = 20 dB
Lfilt = 33 µH
Cfilt = 0.22 µF
Cdc = 470 µF
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)All tests are made at frequency = 1 kHz unless otherwise noted.
CROSSTALK CROSSTALKvs vsFREQUENCY FREQUENCY
Figure 9. Figure 10.
GAIN/PHASE GAIN/PHASEvs vsFREQUENCY FREQUENCY
Figure 11. Figure 12.
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VCC − Supply V oltage − V
0
1
2
3
4
5
6
7
8
9
10
10 11 12 13 14 15
PO − Output Power − W
G013
THD+N = 1%
THD+N = 10%
RL = 4 Ω (SE)
Gain = 20 dB
VCC − Supply V oltage − V
0
2
4
6
8
10
12
14
10 12 14 16 18 20 22 24 26
PO − Output Power − W
G014
THD+N = 1%
THD+N = 10%
RL = 8 Ω (SE)
Gain = 20 dB
PO − Output Power − W
0
10
20
30
40
50
60
70
80
90
100
01234567
Efficiency − %
G015
RL = 4 Ω (SE)
Gain = 20 dB
VCC = 12 V
PO − Output Power − W
0
10
20
30
40
50
60
70
80
90
100
0 2 4 6 8 10 12
Efficiency − %
G016
VCC = 18 V
RL = 8 Ω (SE)
Gain = 20 dB
VCC = 24 V
TPA3124D2
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........................................................................................................................................................................................................ SLOS578 – MAY 2008
TYPICAL CHARACTERISTICS (continued)All tests are made at frequency = 1 kHz unless otherwise noted.
OUTPUT POWER OUTPUT POWERvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 14.A. Dashed line represents thermally limitedregion.
Figure 13.
EFFICIENCY EFFICIENCYvs vsOUTPUT POWER OUTPUT POWER
Figure 15. Figure 16.
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PO − Output Power − W
0.0
0.3
0.6
0.9
1.2
1.5
0 3 6 9 12 15
ICC − Supply Current − A
G017
RL = 4 Ω (SE)
Gain = 20 dB
VCC = 12 V
PO − Output Power − W
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0 5 10 15 20 25
ICC − Supply Current − A
G018
VCC = 24 V
VCC = 18 V
RL = 8 Ω (SE)
Gain = 20 dB
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Power Supply Rejection Ratio − dB
G019
20 100 1k 10k 20k
VCC = 24 V
VO(ripple) = 0.2 VPP
RL = 4 Ω (SE)
Gain = 20 dB
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Power Supply Rejection Ratio − dB
G025
20 100 1k 10k 20k
VCC = 24 V
VO(ripple) = 0.2 VPP
RL = 8 Ω (SE)
Gain = 20 dB
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)All tests are made at frequency = 1 kHz unless otherwise noted.
SUPPLY CURRENT SUPPLY CURRENTvs vsOUTPUT POWER OUTPUT POWER
Figure 17.
A. Dashed line represents thermally limitedregion.
Figure 18.
POWER SUPPLY REJECTION RATIO POWER SUPPLY REJECTION RATIOvs vsFREQUENCY FREQUENCY
Figure 19. Figure 20.
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f − Frequency − Hz
20
VCC = 24 V
RL = 8 Ω (BTL)
Gain = 20 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G020
1
PO = 5 W
PO = 20 W
0.01
PO = 1 W
PO − Output Power − W
0.01
RL = 8 Ω (BTL)
Gain = 20 dB
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G021
1VCC = 12 V
VCC = 24 V
VCC = 18 V
VCC − Supply V oltage − V
0
5
10
15
20
25
30
35
40
45
50
10 12 14 16 18 20 22 24 26
PO − Output Power − W
G023
THD+N = 1%
THD+N = 10%
RL = 8 Ω (BTL)
Gain = 20 dB
PO − Output Power − W
0
10
20
30
40
50
60
70
80
90
100
0 2 4 6 8 10 12
Efficiency − %
G024
RL = 8 Ω (BTL)
Gain = 20 dB
VCC = 24 V
TPA3124D2
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........................................................................................................................................................................................................ SLOS578 – MAY 2008
TYPICAL CHARACTERISTICS (continued)All tests are made at frequency = 1 kHz unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY OUTPUT POWER
Figure 21. Figure 22.
OUTPUT POWER EFFICIENCYvs vsSUPPLY VOLTAGE OUTPUT POWER
Figure 24.A. Dashed line represents thermally limitedregion.
Figure 23.
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APPLICATION INFORMATION
CLASS-D OPERATION
Traditional Class-D Modulation Scheme
+VCC
0V
OutputCurrent
OutputCurrent
+VCC
0V
+VCC
0V
+VCC
0V
–VCC
DifferentialVoltage
AcrossSpeaker
Supply Pumping
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................
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This section focuses on the class-D operation of the TPA3124D2.
The TPA3124D2 operates in AD mode. There are two main configurations that may be used. For stereooperation, the TPA3124D2 should be configured in a single-ended (SE) half-bridge amplifier. For monoapplications, TPA3124D2 may be used as a bridge-tied-load (BTL) amplifier. The traditional class-D modulationscheme, which is used in the TPA3124D2 BTL configuration, has a differential output where each output is 180degrees out of phase and changes from ground to the supply voltage, V
CC
. Therefore, the differential prefilteredoutput varies between positive and negative V
CC
, where filtered 50% duty cycle yields0 V across the load. The class-D modulation scheme with voltage and current waveforms is shown in Figure 25and Figure 26 .
Figure 25. Class-D Modulation for TPA3124D2 SE Configuration
Figure 26. Class-D Modulation for TPA3124D2 BTL Configuration
One issue encountered in single-ended (SE) class-D amplifier designs is supply pumping. Power-supply pumpingis a rise in the local supply voltage due to energy being driven back to the supply by operation of the class-Damplifier. This phenomenon is most evident at low audio frequencies and when both channels are operating atthe same frequency and phase. At low levels, power-supply pumping results in distortion in the audio output dueto fluctuations in supply voltage. At higher levels, pumping can cause the overvoltage protection to operate,which temporarily shuts down the audio output.
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Gain Setting via GAIN0 and GAIN1 Inputs
INPUT RESISTANCE
f= 1
2 Z Cpi i
(1)
TPA3124D2
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........................................................................................................................................................................................................ SLOS578 – MAY 2008
Several things can be done to relieve power-supply pumping. The lowest impact is to operate the two inputs outof phase 180 °and reverse the speaker connections. Because most audio is highly correlated, this causes thesupply pumping to be out of phase and not as severe. If this is not enough, the amount of bulk capacitance onthe supply must be increased. Also, improvement is realized by hooking other supplies to this node, thereby,sinking some of the excess current. Power-supply pumping should be tested by operating the amplifier at lowfrequencies and high output levels.
The gain of the TPA3124D2 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 2 are realized by changing the taps on the input resistors and feedback resistors insidethe amplifier. This causes the input impedance (Z
I
) to be dependent on the gain setting. The actual gain settingsare controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedancefrom part-to-part at the same gain may shift by ± 20% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an inputimpedance of 8 k Ω, which is the absolute minimum input impedance of the TPA3124D2. At the higher gainsettings, the input impedance could increase as high as 72 k Ω.
Table 2. Gain Setting
INPUT IMPEDANCEAMPLIFIER GAIN (dB),GAIN1 GAIN0 (k Ω),TYPICAL
TYPICAL
0 0 20 600 1 26 301 0 32 151 1 36 9
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 10 k Ω± 20%, tothe largest value, 60 k Ω± 20%. As a result, if a single capacitor is used in the input high-pass filter, the – 3-dBcutoff frequency may change when changing gain steps.
The – 3-dB frequency can be calculated using Equation 1 . Use the Z
I
values given in Table 2 .
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INPUT CAPACITOR, C
I
f =
c
1
2 Z Cpi i
–3dB
fc
(2)
C =
i
1
2 Z fpi c
(3)
Single-Ended Output Capacitor, C
O
Output Filter and Frequency Response
TPA3124D2
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In the typical application, input capacitor C
I
is required to allow the amplifier to bias the input signal to the properdc level for optimum operation. In this case C
I
and the input impedance of the amplifier (Z
I
) form a high-pass filterwith the corner frequency determined in Equation 2 .
The value of C
I
is important, as it directly affects the bass (low-frequency) performance of the circuit. Considerthe example where Z
I
is 20 k Ωand the specification calls for a flat bass response down to 20 Hz. Equation 2 isreconfigured as Equation 3 .
In this example, C
I
is 0.4 µF; so, one would likely choose a value of 0.47 µF as this value is commonly used. Ifthe gain is known and is constant, use Z
I
from Table 2 to calculate C
I
. A further consideration for this capacitor isthe leakage path from the input source through the input network, C
I
, and the feedback network to the load. Thisleakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especiallyin high-gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. Whenpolarized capacitors are used, the positive side of the capacitor should face the amplifier input in mostapplications as the dc level there is held at 2 V, which is likely higher than the source dc level. Note that it isimportant to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offsetvoltages, and it is important to ensure that boards are cleaned properly.
In single-ended (SE) applications, the dc blocking capacitor forms a high-pass filter with the speaker impedance.The frequency response rolls off with decreasing frequency at a rate of 20 dB/decade. The cutoff frequency isdetermined byf
c
=πC
O
Z
L
Table 3 shows some common component values and the associated cutoff frequencies:
Table 3. Common Filter Responses
C
SE
- DC Blocking Capacitor ( µF)Speaker Impedance ( Ω)
f
c
= 60 Hz ( – 3 dB) f
c
= 40 Hz ( – 3 dB) f
c
= 20 Hz ( – 3 dB)
4 680 1000 22006 470 680 15008 330 470 1000
For the best frequency response, a flat-passband output filter (second-order Butterworth) may be used. Theoutput filter components consist of the series inductor and capacitor to ground at the LOUT and ROUT pins.There are several possible configurations, depending on the speaker impedance and whether the outputconfiguration is single-ended (SE) or bridge-tied load (BTL). Table 4 lists the recommended values for the filtercomponents. It is important to use a high-quality capacitor in this application. A rating of at least X7R is required.
14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPA3124D2
LOUT /ROUT
Lfilter
Cfilter
LOUT
Lfilter
Cfilter
Lfilter
Cfilter
ROUT
Power-Supply Decoupling, C
S
TPA3124D2
www.ti.com
........................................................................................................................................................................................................ SLOS578 – MAY 2008
Table 4. Recommended Filter Output Components
Output Configuration Speaker Impedance ( Ω) Filter Inductor ( µH) Filter Capacitor (nF)
4 22 680Single Ended (SE)
8 33 220Bridge Tied Load (BTL) 8 22 680
Figure 27. BTL Filter Configuration Figure 28. SE Filter Configuration
The TPA3124D2 is a high-performance CMOS audio amplifier that requires adequate power-supply decouplingto ensure that the output total harmonic distortion (THD) is as low as possible. Power-supply decoupling alsoprevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling isachieved by using two capacitors of different types that target different types of noise on the power-supply leads.For higher-frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)ceramic capacitor, typically 0.1 µF to 1 µF, placed as close as possible to the device V
CC
lead works best. Forfiltering lower frequency noise signals, a larger aluminum electrolytic capacitor of 470 µF or greater placed nearthe audio power amplifier is recommended. The 470- µF capacitor also serves as local storage capacitor forsupplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the powerto the output transistors, so a 470- µF or larger capacitor should be placed on each PVCC terminal. A 10- µFcapacitor on the AVCC terminal is adequate. These capacitors must be properly derated for voltage andripple-current rating to ensure reliability.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPA3124D2
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Power Supply Rejection Ratio − dB
G026
20 100 1k 10k 20k
VCC = 24 V
VO(ripple) = 0.2 VPP
RL = 8 Ω (SE)
Gain = 20 dB
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Power Supply Rejection Ratio − dB
G027
20 100 1k 10k 20k
VCC = 24 V
VO(ripple) = 0.2 VPP
RL = 8 Ω (SE)
Gain = 20 dB
VCC
MUTE
SHUTDOWN
C6
1.0 Fm
R7
C12 0.22 Fm
0.22 F
mC19
+
1 2
TPA3124D2
PVCCL1
1
SDZ
2
PVCCL2
3
MUTE
4
LIN
5
RIN
6
BYP
7
GND1
8
GND2
9
PVCCR1
10
VCLAMP
11
PVCCR2
12 PVSSR2 13
PVSSR1 14
OUTR 15
BSR 16
GAIN1 17
GAIN0 18
AVCC2 19
AVCC1 20
BSL 21
OUTL 22
PVSSL2 23
PVSSL1 24
THERMAL
25
R6
C13
220 Fm
220 W
R8
C7 0.1 Fm
C8
470 Fm
+
1
2
C14
0.1 Fm
0.22 FmC20
4.75kW4.75kW
+
1 2
C15 0.22 Fm
C2
470 Fm
+
1
2
0.1 Fm
C1
C5
1.0 Fm
C3
1.0 Fm
C4
1.0 Fm
L1
33 Fm
L2
33 Fm
C17
470 Fm
C10
470 Fm
BSN and BSP Capacitors
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................
www.ti.com
Figure 29. PSRR Without AVCC Filter Figure 30. PSRR With AVCC Filter
Figure 31. Application Schematic with 220- Ω/220- µF AVCC Filter
The half H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for thehigh side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must beconnected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must beconnected from LOUT to BSL, and one 220-nF capacitor must be connected from ROUT to BSR.
The bootstrap capacitors connected between the BSx pins and their corresponding outputs function as a floatingpower supply for the high-side N-channel power MOSFET gate-drive circuitry. During each high-side switchingcycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETsturned on.
16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPA3124D2
VCLAMP Capacitor
VBYP Capacitor Selection
SHUTDOWN OPERATION
MUTE Operation
USING LOW-ESR CAPACITORS
SHORT-CIRCUIT PROTECTION
TPA3124D2
www.ti.com
........................................................................................................................................................................................................ SLOS578 – MAY 2008
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, oneinternal regulator clamps the gate voltage. One 1- µF capacitor must be connected from VCLAMP (pin 11) toground and must be rated for at least 16 V. The voltages at the VCLAMP terminal may vary with V
CC
and maynot be used for powering any other circuitry.
The scaled supply reference (VBYP) nominally provides an AVCC/8 internal bias for the preamplifier stages. Theexternal capacitor for this reference, C
BYP
, is a critical component and serves several important functions. Duringstart-up or recovery from shutdown mode, C
BYP
determines the rate at which the amplifier starts. The start uptime is proportional to 0.5 s per microfarad. Thus, the recommended 1- µF capacitor results in a start-up time ofapproximately 500 ms. The second function is to reduce noise produced by the power supply caused by couplingwith the output drive signal. This noise could result in degraded power-supply rejection and THD+N.
The circuit is designed for a C
BYP
value of 1 µF for best pop performance. The input capacitors should have thesame value. A ceramic or tantalum low-ESR capacitor is recommended.
The TPA3124D2 employs a shutdown mode of operation designed to reduce supply current (I
CC
) to the absoluteminimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be heldhigh (see specification table for trip point) during normal operation when the amplifier is in use. PullingSHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leaveSHUTDOWN unconnected, because amplifier operation would be unpredictable.
For the best power-up pop performance, place the amplifier in the shutdown or mute mode prior to applying thepower-supply voltage.
The MUTE pin is an input for controlling the output state of the TPA3124D2. A logic high on this terminal causesthe outputs to run at a constant 50% duty cycle. A logic low on this pin enables the outputs. This terminal may beused as a quick disable/enable of outputs when changing channels on a television or transitioning betweendifferent audio sources.
The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should beused to reduce the quiescent current to the absolute minimum level.
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitorcan be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistorminimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,the more the real capacitor behaves like an ideal capacitor.
The TPA3124D2 has short-circuit protection circuitry on the outputs that prevents damage to the device duringoutput-to-output shorts and output-to-GND shorts after the filter and output capacitor (at the speaker terminal.)Directly at the device terminals, the protection circuitry prevents damage to device during output-to-output,output-to-ground, and output-to-supply. When a short circuit is detected on the outputs, the part immediatelydisables the output drive. This is an unlatched fault. Normal operation is restored when the fault is removed.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPA3124D2
THERMAL PROTECTION
PRINTED-CIRCUIT BOARD (PCB) LAYOUT
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................
www.ti.com
Thermal protection on the TPA3124D2 prevents damage to the device when the internal die temperatureexceeds 150 °C. There is a ± 15 °C tolerance on this trip point from device to device. Once the die temperatureexceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is nota latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30 °C. The devicebegins normal operation at this point with no external system interaction.
Because the TPA3124D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuitboard (PCB) should be optimized according to the following guidelines for the best possible performance.•Decoupling capacitors — The high-frequency 0.1- µF decoupling capacitors should be placed as close to thePVCC (pins 1, 3, 10, and 12) and AVCC (pins 19 and 20) terminals as possible. The VBYP (pin 7) capacitorand VCLAMP (pin 11) capacitor should also be placed as close to the device as possible. Large (220- µF orgreater) bulk power-supply decoupling capacitors should be placed near the TPA3124D2 on the PVCCL andPVCCR terminals.•Grounding — The AVCC (pins 19 and 20) decoupling capacitor and VBYP (pin 7) capacitor should each begrounded to analog ground (AGND, pins 8 and 9). The PVCCx decoupling capacitors and VCLAMPcapacitors should each be grounded to power ground (PGND, pins 13, 14, 23, and 24). Analog ground andpower ground should be connected at the thermal pad, which should be used as a central ground connectionor star ground for the TPA3124D2.•Output filter — The reconstruction filter (L1, L2, C9, and C16) should be placed as close to the output terminalsas possible for the best EMI performance. The capacitors should be grounded to power ground.•Thermal pad — The thermal pad must be soldered to the PCB for proper thermal performance and optimalreliability. The dimensions of the thermal pad and thermal land are described in the mechanical section at theback of the data sheet. See TI Technical Briefs SLMA002 and SLOA120 for more information about using thethermal pad. For recommended PCB footprints, see figures at the end of this data sheet.
For an example layout, see the TPA3124D2 Evaluation Module (TPA3124D2EVM) User Manual, (SLOU189 ).Both the EVM user manual and the thermal pad application note are available on the TI Web site athttp://www.ti.com .
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Product Folder Link(s): TPA3124D2
VCC
VCC
LeftIn
Shutdown
Control
Mute
Control
RightIn
10 F
m
470 Fm
0.22µF
TPTPA3124D2
PVCCL
1
SD
2
PVCCL
3
MUTE
4
LIN
5
RIN
6
BYPASS
7
AGND
8
AGND
9
PVCCR
10
VCLAMP
11
PVCCR
12 PGNDR 13
PGNDR 14
ROUT 15
BSR 16
GAIN1 17
GAIN0 18
AVCC 19
AVCC 20
BSL 21
LOUT 22
PGNDL 23
PGNDL 24
THERMAL
25
1.0 Fm
+LOUT
0.22 Fm
–ROUT
–LOUT
+ROUT
0.1 F
m
1.0 Fm
470
470
470
F
F
F
m
m
m
1.0 Fm
1.0 Fm
1.0 Fm
1.0 Fm
0.22 Fm
0.22µF
33µH
33µH
S0268-02
+In
–In
+OUT
–OUT
VCC
VCC
Shutdown
Control
Mute
Control
10 Fm
22 Hm
470 Fm
0.68 Fm
TPA3124D2
PVCCL
1
SD
2
PVCCL
3
MUTE
4
LIN
5
RIN
6
BYPASS
7
AGND
8
AGND
9
PVCCR
10
VCLAMP
11
PVCCR
12 PGNDR 13
PGNDR 14
ROUT 15
BSR 16
GAIN1 17
GAIN0 18
AVCC 19
AVCC 20
BSL 21
LOUT 22
PGNDL 23
PGNDL 24
THERMAL
25
1.0 Fm
0.22 Fm
0.1 Fm
1.0 Fm
470 Fm
1.0 Fm
1.0 Fm
1.0 Fm
1.0 Fm
0.22 Fm
22 Hm
0.68 Fm
S0294-02
TPA3124D2
www.ti.com
........................................................................................................................................................................................................ SLOS578 – MAY 2008
Figure 32. Schematic for Single-Ended (SE) Configuration (8- ΩSpeaker)
Figure 33. Schematic for Bridge-Tied-Load (BTL) Configuration (8- ΩSpeaker)
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPA3124D2
BASIC MEASUREMENT SYSTEM
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................
www.ti.com
This section focuses on methods that use the basic equipment listed below:•Audio analyzer or spectrum analyzer•Digital multi meter (DMM)•Oscilloscope
•Twisted-pair wires•Signal generator•Power resistor(s)•Linear regulated power supply•Filter components
•EVM or other complete audio circuit
Figure 34 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sinewave is normally used as the input signal because it consists of the fundamental frequency only (no otherharmonics are present). An analyzer is then connected to the audio power amplifier (APA) output to measure thevoltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc powersupply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two™audio measurement system (AP-II) by Audio Precision™ includes the signal generator and analyzer in onepackage.
The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-couplingcapacitors C
IN
, so no additional coupling is required. The generator output impedance should be low to avoidattenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, theanalyzer input impedance should be high. The output resistance, R
OUT
, of the APA is normally in the hundreds ofmilliohms and can be ignored for all but the power-related calculations.
Figure 34 (a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signaloutput. This amplifier circuit can be directly connected to the AP-II or other analyzer input.
This is not true of the class-D amplifier system shown in Figure 34 (b), which requires low-pass filters in mostcases in order to measure the audio output waveforms. This is because it takes an analog input signal andconverts it into a pulse-width modulated (PWM) output signal that is not accurately processed by someanalyzers.
20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPA3124D2
Analyzer
20Hz-20kHz
(a)BasicClass-AB
APA
Signal
Generator
PowerSupply
Analyzer
20Hz-20kHz
RL
(b)TraditionalClass-D
Class-D APA
Signal
Generator
PowerSupply
RL
Lfilt
Cfilt
TPA3124D2
www.ti.com
........................................................................................................................................................................................................ SLOS578 – MAY 2008
Figure 34. Audio Measurement Systems
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPA3124D2
SE Input and SE Output (TPA3124D2 Stereo Configuration)
VGEN
CIN
CL
RIN
RGEN
Twisted-PairWire
Generator
EvaluationModule
AudioPower
Amplifier
Twisted-PairWire
RL
RANA CANA
Analyzer
RANA CANA
Lfilt
Cfilt
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................
www.ti.com
The SE input and output configuration is used with class-AB amplifiers. A block diagram of a fully SEmeasurement circuit is shown in Figure 35 . SE inputs normally have one input pin per channel. In some cases,two pins are present; one is the signal and the other is ground. SE outputs have one pin driving a load throughan output ac-coupling capacitor and the other end of the load is tied to ground. SE inputs and outputs areconsidered to be unbalanced, meaning one end is tied to ground and the other to an amplifier input/output.
The generator should have unbalanced outputs, and the signal should be referenced to the generator ground forbest results. Unbalanced or balanced outputs can be used when floating, but they may create a ground loop thataffects the measurement accuracy. The analyzer should have balanced inputs to cancel out any common-modenoise in the measurement.
Figure 35. SE Input — SE Output Measurement Circuit
The following general rules should be followed when connecting to APAs with SE inputs and outputs:•Use an unbalanced source to supply the input signal.•Use an analyzer with balanced inputs.•Use twisted-pair wire for all connections.•Use shielding when the system environment is noisy.•Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the largecurrents (see Table 5 ).
22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPA3124D2
DIFFERENTIAL INPUT AND BTL OUTPUT (TPA3124D2 Mono Configuration)
CIN
AudioPower
Amplifier
Generator
CIN
RGEN
RGEN RIN
RIN
VGEN
Analyzer
RANA
RANA CANA
RL
CANA
Twisted-PairWire
EvaluationModule
Twisted-PairWire
Lfilt
Lfilt
Cfilt
Cfilt
TPA3124D2
www.ti.com
........................................................................................................................................................................................................ SLOS578 – MAY 2008
Many of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied-load (BTL) outputs.Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonlyused in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180 °out of phase. The load is connected between these pins. This has the added benefits of quadrupling the outputpower to the load and eliminating a dc-blocking capacitor.
A block diagram of the measurement circuit is shown in Figure 36 . The differential input is a balanced input,meaning the positive (+) and negative ( – ) pins have the same impedance to ground. Similarly, the SE outputequates to a balanced output.
Figure 36. Differential Input, BTL Output Measurement Circuit
The generator should have balanced outputs, and the signal should be balanced for best results. An unbalancedoutput can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer mustalso have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise inthe circuit and providing the most accurate measurement.
The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:•Use a balanced source to supply the input signal.•Use an analyzer with balanced inputs.•Use twisted-pair wire for all connections.•Use shielding when the system environment is noisy.•Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the largecurrents (see Table 5 ).
Table 5 shows the recommended wire size for the power supply and load cables of the APA system. The realconcern is the dc or ac power loss that occurs as the current flows through the cable. These recommendationsare based on 12-inch (30.5-cm)-long wire with a 20-kHz sine-wave signal at 25 °C.
Table 5. Recommended Minimum Wire Size for Power Cables
DC POWER LOSS AC POWER LOSSP
OUT
(W) R
L
(Ω) AWG Size
(mW) (mW)
10 4 18 22 16 40 18 422 4 18 22 3.2 8 3.7 8.51 8 22 28 2 8 2.1 8.1< 0.75 8 22 28 1.5 6.1 1.6 6.2
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TPA3124D2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA3124D2PWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA3124D2PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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