VRE305CD - Cirrus Logic - Datasheet.Directory

VRE305

VRE305DS 1

VRE305

DESCRIPTION

The VRE305 is a low cost, high precision +5 V refer-

ence. Packaged in an industry standard 8-pin DIP or

SMT, the device is ideal for upgrading systems that

use lower performance references.

The device provides ultrastable +5 V output with ±0.5

mV (.01%) initial accuracy and a temperature coef-

cient of 0.6 ppm/°C. This improvement in accuracy is

made possible by a unique, patented multipoint laser

compensation technique. Signicant improvements

have been made in other performance parameters

as well, including initial accuracy, warm-up drift, line

regulation, and long-term stability, making the VRE305

series the most accurate reference available in a stan-

dard 8-pin DIP or SMT.

For enhanced performance, the VRE305 has an exter-

nal trim option for users who want less than 0.01% ini-

tial error. For ultra low noise applications, an external

capacitor can be attached between the noise reduc-

tion pin and the ground pin. A reference ground pin is

provided to eliminate socket contact resistance errors.

FEATURES

♦ +5 V Output, ± 0.5 mV (.01%)

♦ Temperature Drift: 0.6 ppm/ºC

♦ Low Noise: 3 μVP-P (0.1-10Hz)

♦ Industry Standard Pinout: 8-pin DIP or

Surface Mount Package

♦ Excellent Line Regulation: 6 ppm/V Typical

♦ Output Trim Capability

APPLICATIONS

The VRE305 is recommended for use as a refer-

ence for 14, 16, or 18 bit D/A converters which re-

quire an external precision reference. The device

is also ideal for calibrating scale factor on high

resolution A/D converters. The VRE305 offers su-

perior performance over monolithic references.

Precision Voltage Reference

VRE305

Figure 1. BLOCK DIAGRAM

Model

Initial Error

(mV)

Temp. Coeff.

(ppm/ºC)

Temp. Range

(ºC)

Package

Options

VRE305AS

VRE305AD

VRE305CS

VRE305CD

VRE305LS

0.5

1.0

0.6

2.0

0ºC to +70ºC

-40ºC to +85ºC

SIP8 (GD)

DIP8 (KD)

SIP8 (GD)

DIP8 (KD)

SIP8 (GD)

SELECTION GUIDE

8-pin Surface Mount

Package Style GD

8-pin DIP

Package Style KD

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VRE305DS REVH

VRE305

2 VRE305DS

1. CHARACTERISTICS AND SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

VPS = +15V, T = +25ºC, RL = 10KΩ Unless Otherwise Noted.

Model A C/L

Parameter Min Typ Max Min Typ Max Units

ABSOLUTE MAXIMUM RATINGS

Power Supply +13.5 +15 +22 * * * V

Operating Temperature 0 +70 * * ºC

Storage Temperature -65 +150 * * ºC

Short Circuit Protection Continuous *

OUTPUT VOLTAGE

VRE305 +5.0 * V

Temp. Sensor Voltage (Note 1) 630 * mV

OUTPUT VOLTAGE ERRORS

Initial Error (Note 2) 0.5 1.00 mV

Warmup Drift 1 3 ppm

TMIN - TMAX (Note3) 0.6 2.0 ppm/ºC

Long-Term Stability 6 * ppm/1000hrs.

Noise (0.1 - 10Hz) (Note 4) 3 * µVpp

OUTPUT CURRENT

Range ±10 mA

REGULATION

Line 6 10 * * ppm/V

Load 3 * ppm/mA

OUTPUT ADJUSTMENT

Range 10 * mV

POWER SUPPLY CURRENT (Note 5)

VRE305 +PS 5 7 * * mA

NOTES:

* Same as A Model.

1. The temp. reference TC is 2.1 mV/ ºC

2. The specied values are without external trim.

3. The temperature coefcient is determined by the box method using the following formula:

4. The specied values are without the external noise reduction capacitor.

5. The specied values are unloaded.

VNOMINAL x (TMAX – TMIN)

VMAX – VMIN

T.C. = x 106

VRE305

VRE305DS 3

2. TYPICAL PERFORMANCE CURVES

Temperature oC

VRE305A

VOUT vs. TEMPERATURE VOUT vs. TEMPERATURE

Temperature oC

VRE305C

QUIESCENT CURRENT VS. TEMP

Temperature oC

JUNCTION TEMP. RISE VS. OUTPUT CURRENT

Output Current (mA)

PSRR VS. FREQUENCY

Frequency (Hz)

Temperature oC

VRE305L

VOUT vs. TEMPERATURE

3. THEORY OF OPERATION

The following discussion refers to the block diagram in Figure 1. A FET current source is used to bias a 6.3 V zener

diode. The zener voltage is divided by the resistor network R1 and R2. This voltage is then applied to the noninvert-

ing input of the operational amplier which amplies the voltage to produce a 5 V output. The gain is determined by

the resistor networks R3 and R4: G=1 + R4/R3. The 6.3 V zener diode is used because it is the most stable diode

over time and temperature.

The current source provides a closely regulated zener current, which determines the slope of the references’ volt-

age vs. temperature function. By trimming the zener current a lower drift over temperature can be achieved. But

since the voltage vs. temperature function is nonlinear this compensation technique is not well suited for wide tem-

perature ranges.

A nonlinear compensation network of thermistors and resistors is used in the VRE series voltage references. This

proprietary network eliminates most of the nonlinearity in the voltage vs. temperature function. By adjusting the

slope, a very stable voltage is produced over wide temperature ranges.

This network is less than 2% of the overall network resistance so it has a negligible effect on long term stability.

VRE305

4 VRE305DS

The proper connection of the VRE305 series voltage references with the optional trim resistor for initial error and

the optional capacitor for noise reduction is shown below. The VRE305 reference has the ground terminal brought

out on two pins (pin 4 and pin 7) which are connected together internally. This allows the user to achieve greater

accuracy when using a socket. Voltage references have a voltage drop across their power supply ground pin due to

quiescent current owing through the contact resistance. If the contact resistance was constant with time and tem-

perature, this voltage drop could be trimmed out. When the reference is plugged into a socket, this source of error

can be as high as 20 ppm. By connecting pin 4 to the power supply ground and pin 7 to a high impedance ground

point in the measurement circuit, the error due to the contact resistance can be eliminated. If the unit is soldered

into place, the contact resistance is sufciently small that it does not effect performance. Pay careful attention to the

circuit layout to avoid noise pickup and voltage drops in the lines.

EXTERNAL CONNECTIONS

+ VOUT

+ VIN

VRE305

10KΩ

1µF

OPTIONAL

NOISE REDUCTION

CAPACITOR

OPTIONAL

FINE TRIM

ADJUSTMENT

VTEMP OUT

REF. GND

VRE305

TOP

VIEW

N/C

+VIN

TEMP

GND

NOISE

REDUCTION

REF. GND

VOUT

TRIM

PIN CONFIGURATION

NEED TECHNICAL HELP? CONTACT APEX SUPPORT!

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For inquiries via email, please contact apex.support@apexanalog.com.

International customers can also request support by contacting their local Apex Microtechnology Sales Representative.

To nd the one nearest to you, go to www.apexanalog.com

IMPORTANT NOTICE

Apex Microtechnology, Inc. has made every effort to insure the accuracy of the content contained in this document. However, the information is subject to change

without notice and is provided "AS IS" without warranty of any kind (expressed or implied). Apex Microtechnology reserves the right to make changes without further

notice to any specications or products mentioned herein to improve reliability. This document is the property of Apex Microtechnology and by furnishing this informa-

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of their respective holders.

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VRE305DS REVH