14
12
8
OUT
CS
3
4
2
5
6
3V3
AGND
IN
CLF
ILIM
UCD7100PWP
Bias
Winding
VIN
VOUT
VDD
2
Isolation
Amplifier
PWMB
INT
Digital Controller
PWMA
VDD
AN2
AN3
AN1
AGND
Communication
UCD7100
www.ti.com
SLUS651C –MARCH 2005–REVISED MAY 2010
Digital Control Compatible Single Low-Side ±4-A MOSFET Driver with Current Sense
Check for Samples: UCD7100
1FEATURES DESCRIPTION
2• Adjustable Current Limit Protection The UCD7100 is a member of the UCD7K family of
digital control compatible drivers for applications
• 3.3-V, 10-mA Internal Regulator utilizing digital control techniques or applications
• DSP/µC Compatible Inputs requiring fast local peak current limit protection.
• Single ±4-A TrueDrive™ High Current Driver The UCD7100 is a low-side ±4-A high-current
• 10-ns Typical Rise and Fall Times with 2.2-nF MOSFET gate driver. It allows the digital power
Loads controllers such as UCD9110 or UCD9501 to
• 25-ns Input-to-Output Propagation Delay interface to the power stage in single ended
topologies. It provides a cycle-by-cycle current limit
• 25-ns Current Sense to Output Delay function with programmable threshold and a digital
• Programmable Current Limit Threshold output current limit flag which can be monitored by
• Digital Output Current Limit Flag the host controller. With a fast 25-ns cycle-by-cycle
current limit protection, the driver can turn off the
• 4.5-V to 15-V Supply Voltage Range power stage in the unlikely event that the digital
• Rated from -40°C to 105°C system can not respond to a failure situation in time.
• Lead(Pb)-Free Packaging For fast switching speeds, the UCD7100 output stage
uses the TrueDrive™ output architecture, which
APPLICATIONS delivers rated current of ±4 A into the gate of a
• Digitally Controlled Power Supplies MOSFET during the Miller plateau region of the
• DC/DC Converters switching transition. It also includes a 3.3-V, 10-mA
• Motor Controllers linear regulator to provide power to the digital
controller.
• Line Drivers
TYPICAL APPLICATION DIAGRAMS
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2TrueDrive, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
PWP−14 PACKAGE
(TOP VIEW)
NC − No internal connection
VDD
IN
3V3
AGND
CLF
ILIM
NC
PVDD
PVDD
OUT
OUT
PGND
PGND
CS
UCD7100
SLUS651C –MARCH 2005–REVISED MAY 2010
www.ti.com
DESCRIPTION (CONT.)
The UCD7000 driver family is compatible with standard 3.3-V I/O ports of DSPs, Microcontrollers, or ASICs.
UCD7100 is offered in a PowerPAD™ HTSSOP-14.
CONNECTION DIAGRAMS
ORDERING INFORMATION Packaged Devices(1) (2)
Temperature Range 110-V HV Startup Circuit PowerPAD™ HTSSOP-14 (PWP)
-40°C to 105°C No UCD7100PWP
(1) HTSSOP-14 (PWP) package is available taped and reeled. Add R suffix to device type (e.g. UCD7100PWPR) to order quantities of
2,000 devices per reel for the PWP package.
(2) These products are packaged in Pb-Free and Green lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C
peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.
ABSOLUTE MAXIMUM RATINGS(1) (2)
SYMBOL PARAMETER UCD7100 UNIT
VDD Supply Voltage 16
Quiescent 20
IDD Supply Current mA
Switching, TA= 25°C, TJ= 125°C, VDD = 12 V 200
Output Gate Drive
VOUT OUT -1 V to VDD V
Voltage
IOUT(sink) 4.0
Output Gate Drive OUT A
Current
IOUT(source) -4.0
ISET, CS -0.3 to 3.6
Analog Input ILIM -0.3 to 3.6 V
Digital I/O’s IN, CLF -0.3 to 3.6
Power Dissipation TA= 25°C, TJ= 125°C, (PWP-14) 2.67 W
TJJunction Operating Temperature -55 to 150 °C
Tstr Storage Temperature -65 to 150
HBM Human body model 2000
ESD Rating V
CDM Change device model 500
TSOL Lead Temperature (Soldering, 10 sec) +300 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
2Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): UCD7100
UCD7100
www.ti.com
SLUS651C –MARCH 2005–REVISED MAY 2010
RECOMMENDED OPERATING CONDITIONS
PARAMETER MIN TYP MAX UNIT
Supply Voltage, VDD 4.25 12 14.5 V
Supply bypass capacitance 1 µF
Reference bypass capacitance 0.22
Operating junction temperature -40 105 °C
ELECTRICAL CHARACTERISTICS
VDD = 12 V, 4.7-µF capacitor from VDD to GND, TA= TJ= -40°C to 105°C, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY SECTION
Supply current, OFF VDD = 4.2 V 200 400 µA
Supply current Outputs not switching IN = LOW 1.5 2.5 mA
LOW VOLTAGE UNDER-VOLTAGE LOCKOUT
VDD UVLO ON 4.25 4.5 4.75 V
VDD UVLO OFF 4.05 4.25 4.45
VDD UVLO hysteresis 150 250 350 mV
REFERENCE / EXTERNAL BIAS SUPPLY
3V3 initial set point TA= 25°C 3.267 3.3 3.333 V
3V3 over temperature 3.234 3.3 3.366
3V3 load regulation ILOAD = 1 mA to 10 mA, VDD = 5 V 1 6.6 mV
3V3 line regulation VDD = 4.75 V to 12 V, ILOAD = 10 mA 1 6.6
Short circuit current VDD = 4.75 to 12 V 11 20 35 mA
3V3 OK threshold, ON 3.3 V rising 2.9 3.0 3.1 V
3V3 OK threshold, OFF 3.3 V falling 2.7 2.8 2.9
INPUT SIGNAL
HIGH, positive-going input threshold 1.65 2.08
voltage (VIT+)
LOW negative-going input threshold 1.16 1.5 V
voltage (VIT-)
Input voltage hysteresis, (VIT+ - 0.6 0.8
VIT-)
Frequency 2 MHz
CURRENT LIMIT (ILIM)
ILIM internal current limit threshold ILIM = OPEN 0.466 0.50 0.536 V
ILIM maximum current limit threshold ILIM = 3.3 V 0.975 1.025 1.075 V
ILIM current limit threshold ILIM = 0.75 V 0.700 0.725 0.750
ILIM minimum current limit threshold ILIM = 0.25 V 0.21 0.23 0.25 mV
CLF output high level CS > ILIM , ILOAD = -7 mA 2.64 V
CLF output low level CS ≤ILIM, ILOAD = 7 mA 0.66
Propagation delay from IN to CLF IN rising to CLF falling after a current limit event 10 20 ns
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): UCD7100
VIT−
10%
90%
INPUT
OUTPUT
VIT+
tD1
tFtF
tD2
UCD7100
SLUS651C –MARCH 2005–REVISED MAY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VDD = 12 V, 4.7-µF capacitor from VDD to GND, TA= TJ= -40°C to 105°C, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT SENSE COMPARATOR
Bias voltage Includes CS comp offset 5 25 50 mV
Input bias current –1 uA
Propagation delay from CS to OUTx ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV 25 40 ns
Propagation delay from CS to CLF ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV 25 50
CURRENT SENSE DISCHARGE TRANSISTOR
Discharge resistance IN = low, resistance from CS to AGND 10 35 75 Ω
OUTPUT DRIVERS
Source current (1) VDD = 12 V, IN = high, OUT = 5 V 4
Sink current (1) VDD = 12 V, IN = low, OUT = 5 V 4 A
Source current(1) VDD = 4.75 V, IN = high, OUT = 0 2
Sink current (1) VDD = 4.75 V, IN = low, OUT = 4.75 V 3
Rise time, tR(1) CLOAD = 2.2 nF, VDD = 12 V 10 20 ns
Fall time, tF(1) CLOAD = 2.2 nF, VDD = 12 V 10 15
Output with VDD < UVLO VDD = 1.0 V, ISINK = 10 mA 0.8 1.2 V
Propagation delay from IN to OUTx, CLOAD = 2.2 nF, VDD = 12 V, CLK rising 20 35 ns
tD1
(1) Ensured by design. Not 100% tested in production.
NOTE
The 10% and 90% thresholds depict the dynamics of the bipolar output devices that
dominate the power MOSFET transition through the Miller regions of operation.
4Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): UCD7100
2
7
4
3
5
6
3V3 Regulator
&
Reference UVLO 12
14
11
1
10
9
8
PVDD
N/C
3V3
IN
AGND
CLF
ILIM
OUT
OUT
PGND
PGND
CS
+
13 PVDD
VDD
+
25 mV
SD
Q
Q R
UCD7100
www.ti.com
SLUS651C –MARCH 2005–REVISED MAY 2010
FUNCTIONAL BLOCK DIAGRAM
Figure 1. UCD7100
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): UCD7100
UCD7100
SLUS651C –MARCH 2005–REVISED MAY 2010
www.ti.com
TERMINAL FUNCTIONS
UCD7100 PIN I/O FUNCTION
HTSSOP DFN-14 NAME
-14 PIN # PIN #
Supply input pin to power the driver. The UCD7K devices accept an input range of 4.25 V to
1 1 VDD I 15 V. Bypass the pin with at least 4.7 µF of capacitance.
The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up
2 2 IN I to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry
from any external noise.
Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA
3 3 3V3 O of current. Place 0.22-µF of ceramic capacitance from the pin to ground.
4 4 AGND - Analog ground return.
Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output
5 5 CLF O of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is
latched high until the UCD7K device receives the next rising edge on the IN pin.
Current limit threshold set pin. The current limit threshold can be set to any value between
6 6 ILIM I 0.25 V and 1.0 V.
7 7 NC - No Connection.
Current sense pin. Fast current limit comparator connected to the CS pin is used to protect
8 8 CS I the power stage by implementing cycle-by-cycle current limiting.
Power ground return. Connect the two PGNDs together. These ground pins should be
9 9 PGND - connected very closely to the source of the power MOSFET.
Power ground return. Connect the two PGNDs together. These ground pins should be
10 10 PGND - connected very closely to the source of the power MOSFET.
11 11 OUT O The high-current TrueDrive™ driver output. Connect the two OUT pins together.
12 12 OUT O The high-current TrueDrive™ driver output. Connect the two OUT pins together.
Supply pin provides power for the output drivers. It is not connected internally to the VDD
13 13 PVDD I supply rail. Connect the two PVDD pins together.
Supply pin provides power for the output drivers. It is not connected internally to the VDD
14 14 PVDD I supply rail. Connect the two PVDD pins together.
6Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): UCD7100
UCD7100
www.ti.com
SLUS651C –MARCH 2005–REVISED MAY 2010
APPLICATION INFORMATION
The UCD7100 is part of a family of digital compatible drivers targeting applications utilizing digital control
techniques or applications that require local fast peak current limit protection.
Supply
The UCD7K devices accept an input range of 4.5 V to 15 V. The device has an internal precision linear regulator
that produces the 3V3 output from this VDD input. A separate pin, PVDD, not connected internally to the VDD
supply rail provides power for the output drivers. In all applications the same bus voltage supplies the two pins. It
is recommended that a low value of resistance be placed between the two pins so that the local capacitance on
each pin forms low pass filters to attenuate any switching noise that may be on the bus.
Although quiescent VDD current is low, total supply current will be higher, depending on the gate drive output
current required by the switching frequency. Total VDD current is the sum of quiescent VDD current and the
average OUT current. Knowing the operating frequency and the MOSFET gate charge (QG), average OUT
current can be calculated from:
IOUT = QGx f, where f is frequency.
For high-speed circuit performance, a VDD bypass capacitor is recommended to prevent noise problems. A
4.7-µF ceramic capacitor should be located close to the VDD to ground connection. A larger capacitor with
relatively low ESR should be connected to the PVDD pin, to help deliver the high current peaks to the load. The
capacitors should present a low impedance characteristic for the expected current levels in the driver application.
The use of surface mount components for all bypass capacitors is highly recommended.
Reference / External Bias Supply
All devices in the UCD7K family are capable of supplying a regulated 3.3-V rail to power various types of external
loads such as a microcontroller or an ASIC. The onboard linear voltage regulator is capable of sourcing up to 10
mA of current. For normal operation, place a minimum of 0.22 µF of ceramic capacitance from the reference pin
to ground.
Input
The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. There is
an internal Schmitt Trigger comparator which isolates the internal circuitry from any external noise.
If limiting the rise or fall times to the power device is desired, then an external resistance can be added between
the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor may
also help remove power dissipation from the package.
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): UCD7100
UCD7100
SLUS651C –MARCH 2005–REVISED MAY 2010
www.ti.com
Current Sensing and Protection
A very fast current limit comparator connected to the CS pin is used to protect the power stage by implementing
cycle-by-cycle current limiting.
The current limit threshold is equal to the lesser of the positive inputs at the current limit comparator. The current
limit threshold can be set to any value between 0.25 V and 1.0 V by applying the desired threshold voltage to the
current limit (ILIM) pin. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver
is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the UCD7K device
receives the next rising edge on the IN pin.
When the CS voltage is below ILIM, the driver output will follow the PWM input. The CLF digital output flag can
be monitored by the host controller to determine when a current limit event occurs and to then apply the
appropriate algorithm to obtain the desired current limit profile.
One of the main benefits of this local protection feature is that the UCD7K devices can protect the power stage if
the software code in the digital controller becomes corrupted and hangs up. If the controller’s PWM output stays
high, the local current sense circuit will turn off the driver output when an over-current condition occurs. The
system would likely go into a retry mode because; most DSP and microcontrollers have on-board watchdog,
brown-out, and other supervisory peripherals to restart the device in the event that it is not operating properly.
But these peripherals typically do not react fast enough to save the power stage. The UCD7K’s local current limit
comparator provides the required fast protection for the power stage.
The CS threshold is 25 mV below the ILIM voltage. This way, if the user attempts to command zero current (ILIM
< 25 mV) while the CS pin is at ground, for example at start-up, the CLF flag latches high until the IN pin
receives a pulse. At start-up it is necessary to ensure that the ILIM pin always greater than the CS pin for the
handshaking to work as described below. If for any reason the CS pin comes to within 25 mV of the ILIM pin
during start-up, then the CLF flag is latched high and the digital controller must poll the UCD7K device, by
sending it a narrow IN pulse. If the fault condition is not present the IN pulse resets the CLF signal to low
indicating that the UCD7K device is ready to process power pulses.
8Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): UCD7100
UCD7100
www.ti.com
SLUS651C –MARCH 2005–REVISED MAY 2010
Handshaking
The UCD7K family of devices have a built-in handshaking feature to facilitate efficient start-up of the digitally
controlled power supply. At start-up the CLF flag is held high until all the internal and external supply voltages of
the UCD7K device are within their operating range. Once the supply voltages are within acceptable limits, the
CLF goes low and the device will process input drive signals. The micro-controller should monitor the CLF flag at
start-up and wait for the CLF flag to go LOW before sending power pulses to the UCD7K device.
Driver Output
The high-current output stage of the UCD7K device family is capable of supplying ±4-A peak current pulses and
swings to both VDD and GND. The driver outputs follows the state of the IN pin provided that the VDD and 3V3
voltages are above their respective under-voltage lockout threshold.
The drive output utilizes Texas Instruments’ TrueDrive™ architecture, which delivers rated current into the gate
of a MOSFET when it is most needed during the Miller plateau region of the switching transition providing
efficiency gains.
TrueDrive™ consists of pullup/ pulldown circuits using bipolar and MOSFET transistors in parallel. The peak
output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is
the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of
the bipolar transistor. This hybrid output stage also allows efficient current sourcing at low supply voltages.
Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the
external MOSFET. This means that in many cases, external-schottky-clamp diodes are not required.
Source/Sink Capabilities During Miller Plateau
Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable
operation. The UCD7K drivers have been optimized to provide maximum drive to a power MOSFET during the
Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between
the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate
capacitance with current supplied or removed by the driver device. See Reference [1]
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): UCD7100
E+1
2 CV2
P+1
2 CV2 f
P+10 nF 122 300 kHz +0.432 W
I+P
V+0.432 W
12 V +0.036 A
P+C V2 f+QG V f
UCD7100
SLUS651C –MARCH 2005–REVISED MAY 2010
www.ti.com
Drive Current and Power Requirements
The UCD7K family of drivers can deliver high current into a MOSFET gate for a period of several hundred
nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the
driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the
power device. A MOSFET is used in this discussion because it is the most common type of switching device
used in high frequency power conversion equipment.
Reference [1] discusses the current required to drive a power MOSFET and other capacitive-input switching
devices.
When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power
that is required from the bias supply. The energy that must be transferred from the bias supply to charge the
capacitor is given by:
(1)
where C is the load capacitor and V is the bias voltage feeding the driver.
There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a
power loss given by the following:
(2)
where f is the switching frequency.
This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver
and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is
charged, and the other half is dissipated when the capacitor is discharged. An actual example using the
conditions of the previous gate drive waveform should help clarify this.
With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as:
(3)
With a 12-V supply, this would equate to a current of:
(4)
The actual current measured from the supply was 0.037 A, and is very close to the predicted value. But, the IDD
current that is due to the device internal consumption should be considered. With no load the device current
drawn is 0.0027 A. Under this condition the output rise and fall times are faster than with a load. This could lead
to an almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver.
However, these small current differences are buried in the high frequency switching spikes, and are beyond the
measurement capabilities of a basic lab setup. The measured current with 10-nF load is close to the value
expected.
The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus
the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers
provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under
specified conditions. Using the gate charge QG, one can determine the power that must be dissipated when
charging a capacitor. This is done by using the equivalence QG= CEFF x V to provide the following equation for
power:
(5)
This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a
specific bias voltage.
10 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): UCD7100
14
UCD91xx
with
CLA
Peripheral
1
12
8
PVDD
OUT
CS
10
PGND
3
4
2
5
6
3V3
AGND
IN
CLF
ILIM
7
2
UCD7100PWP
Bias
Winding
VIN
VOUT
VDS
CS
FB
CS
VDS
COMMUNICATION
(Programming & Status Reporting)
Bias Supply
11OUT
9
PGND
13
PVDD
VDD
NC
2
Isolation
Amplifier
2
1
UCD7100
www.ti.com
SLUS651C –MARCH 2005–REVISED MAY 2010
Thermal Information
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the device package. In order for a power driver to be useful over a particular temperature range
the package must allow for the efficient removal of the heat produced while keeping the junction temperature
within rated limits. The UCD7K family of drivers is available in PowerPAD™ TSSOP package to cover a range of
application requirements. Both have the exposed pads to relieve thermal dissipation from the semiconductor
junction.
As illustrated in Reference [2], the PowerPAD™ packages offer a leadframe die pad that is exposed at the base
of the package. This pad is soldered to the copper on the PC board (PCB) directly underneath the device
package, reducing the ΘJC down to 4.7°C/W. The PC board must be designed with thermal lands and thermal
vias to complete the heat removal subsystem, as summarized in Reference [3].
Note that the PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and
thermally connected to the substrate which is the ground of the device.
Circuit Layout Recommendations
In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much
overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high
di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout. It is
advantageous to connect the driver IC as close as possible to the leads. The driver device layout has the analog
ground on the opposite side of the output, so the ground should be connected to the bypass capacitors and the
load with copper trace as wide as possible. These connections should also be made with a small enclosed loop
area to minimize the inductance.
Figure 2. Isolated Forward Converter
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): UCD7100
14
UCD9501
Digital
1
12
8
PVDD
OUT
CS
10
PGND
3
4
2
5
6
3V3
AGND
IN
CLF
ILIM
7
UCD7100PWP
VOUT
VDS
CS
FB
CS
VDS
COMMUNICATION
(Programming & Status Reporting)
Bias
Supply
11
OUT
9
PGND
13
PVDDVDD
NC
Signal
Conditioning
Amplifier
~
~+−
VAC
PFC_ISENSE
Signal
Conditioning
Amplifier
Controller
UCD7100
SLUS651C –MARCH 2005–REVISED MAY 2010
www.ti.com
Figure 3. PFC Boost Front-End Power Supply
12 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): UCD7100
−50 50 125−25 0 25 75 100
3.24
3.26
3.28
3.30
3.32
3.34
3.36
t − Temperature − °C
3V3 − Reference Voltage − V
−50 50
5.0
4.5
2.5
2.0
1.5
0.5
0.0 −25 0 25 75 100
4.0
1.0
3.5
3.0
UVLO on
UVLO on
UVLO on
t − Temperature − °C
125
VUVLO − UVLO Thresholds − V
−50 50 125−25 0 25 75 100
20.0
20.5
21.0
21.5
22.0
22.5
23.0
t − Temperature − °C
ISHORT_CKT − Short Circuit Current − mA
VDD = 4.75 V
VDD = 12 V
−50 50 125−25 0 25 75 100
0.0
0.5
1.0
1.5
2.0
2.5
TJ − Temperature − °C
VINPUT − Input Voltage − V
Input Rising
Input Falling
UCD7100
www.ti.com
SLUS651C –MARCH 2005–REVISED MAY 2010
TYPICAL CHARACTERISTICS
UVLO THRESHOLDS 3V3 REFERENCE VOLTAGE
vs vs
TEMPERATURE TEMPERATURE
Figure 4. Figure 5.
3V3 SHORT CIRCUIT CURRENT INPUT THRESHOLDS
vs vs
TEMPERATURE TEMPERATURE
Figure 6. Figure 7.
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): UCD7100
5
15
25
35
45
55
65
5 7.5 10 12.5 15
VDD − Supply V oltage − V
tR − Rise Time − ns
CLOAD = 10 nF
CLOAD = 4.7 nF
CLOAD = 2.2 nF
CLOAD = 1 nF
−50 50 125−25 0 25 75 100
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
TJ − Temperature − °C
tR, tF − Rise and Fall Times − ns
tR = Rise Time
tF = Fall Time
0
5
10
15
20
5 7.5 10 12.5 15
VDD − Supply V oltage − V
tPD − Propagation Delay, Rising − ns
CLOAD = 10 nF
CLOAD = 4.7 nF
CLOAD = 2.2 nF
CLOAD = 1 nF
5
10
15
20
25
30
35
40
45
5 7.5 10 12.5 15
VDD − Supply V oltage − V
tF − Fall Time − ns
CLOAD = 10 nF
CLOAD = 4.7 nF
CLOAD = 2.2 nF
CLOAD = 1 nF
UCD7100
SLUS651C –MARCH 2005–REVISED MAY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
OUTPUT RISE TIME AND FALL TIME RISE TIME
vs vs
TEMPERATURE (VDD = 12 V
) SUPPLY VOLTAGE
Figure 8. Figure 9.
FALL TIME PROPAGATION DELAY RISING
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 10. Figure 11.
14 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): UCD7100
5
10
15
20
25
5 7.5 10 12.5 15
VDD − Supply V oltage − V
tPD − Propagation Delay, Falling − ns
CLOAD = 10 nF
CLOAD = 4.7 nF
CLOAD = 2.2 nF CLOAD = 1 nF
−50 50 125−25 0 25 75 100
0.46
0.47
0.48
0.49
0.50
0.51
0.52
0.53
0.54
TJ − Temperature − °C
VCS − Current Limit Threshold − V
−50 50−25 0 25 75 100
0
5
10
15
20
25
30
35
40
45
50
TJ − Temperature − °C
tPD − CS to CLF Propagation Delay − ns
125
−50 50 125−25 0 25 75 100
0
5
10
15
20
25
30
35
40
TJ − Temperature − °C
tPD − CS to OUTx Propagation Delay − ns
UCD7100
www.ti.com
SLUS651C –MARCH 2005–REVISED MAY 2010
TYPICAL CHARACTERISTICS (continued)
PROPAGATION DELAY FALLING DEFAULT CURRENT LIMIT THRESHOLD
vs vs
SUPPLY VOLTAGE TEMPERATURE
Figure 12. Figure 13.
CS TO OUTx PROPAGATION DELAY CS TO CLF PROPAGATION DELAY
vs vs
TEMPERATURE TEMPERATURE
Figure 14. Figure 15.
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): UCD7100
t − Time − 40 µs/div
VDD (2 V/div)
3V3 (2 V/div)
OUTx (2 V/div)
−50 50 125−25 0 25 75 100
0
5
10
15
20
25
30
35
TJ − Temperature − °C
tPD − Propagation Delay − ns
t − Time − 40 µs/div
VDD (2 V/div)
3V3 (2 V/div)
OUTx (2 V/div)
t − Time − 40 µs/div
VDD (2 V/div)
3V3 (2 V/div)
OUTx (2 V/div)
UCD7100
SLUS651C –MARCH 2005–REVISED MAY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
IN TO OUT PROPAGATION DELAY
vs
TEMPERATURE START-UP BEHAVIOR AT VDD = 12 V (INPUT TIED TO 3V3)
Figure 16. Figure 17.
SHUT DOWN BEHAVIOR AT VDD = 12 V (INPUT TIED TO START-UP BEHAVIOR AT VDD = 12 V (INPUT SHORTED
3V3) TO GND)
Figure 18. Figure 19.
16 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): UCD7100
t − Time − 40 ns/div
Output Voltage − 2 V/div
t − Time − 40 µs/div
VDD (2 V/div)
3V3 (2 V/div)
OUTx (2 V/div)
UCD7100
www.ti.com
SLUS651C –MARCH 2005–REVISED MAY 2010
TYPICAL CHARACTERISTICS (continued)
SHUT DOWN BEHAVIOR AT VDD = 12 V (INPUT SHORTED OUTPUT RISE AND FALL TIME (VDD = 12 V, CLOAD = 10
TO GND) NF)
Figure 20. Figure 21.
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): UCD7100
UCD7100
SLUS651C –MARCH 2005–REVISED MAY 2010
www.ti.com
REFERENCES
1. Power Supply Seminar SEM−1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate
Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133.
2. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
3. Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004
RELATED PRODUCTS
PRODUCT DESCRIPTION FEATURES
UCD7200 Dual Low Side ±4-A Drivers with Independent CS 3V3, CS(1) (2)
UCD7201 Dual Low Side ±4-A Drivers with Common CS 3V3, CS(1) (2)
UCD7230 ±4A Synchronous Buck Driver with CS 3V3, CS(1) (2)
UCD9110 Digital Power Controller for High Performance Single-loop Applications
(1) 3V3 = 3.3V linear regulator.
(2) CS = current sense and current limit function.
REVISION HISTORY
DATE REVISION CHANGE DESCRIPTION
3/4/05 SLUS651 Initial release
4/29/09 SLUS651B Removed QFN package option and all references.
Removed part numbers, UCD7500, UCD7600, UCD7601 and UCD9501 from Related Products
5/21/10 SLUS651C Section.
18 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): UCD7100
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
UCD7100PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCD7100PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCD7100PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCD7100PWPRG4 ACTIVE HTSSOP PWP 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-May-2010
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
