© Freescale Semiconductor, Inc., 2011. All rights reserved.
Freescale Semiconductor
Data Sheet: Technical Data
This document provides an overview of the MPC8315E
PowerQUICC™ II Pro processor features, including a block
diagram showing the major functional components. The
MPC8315E contains a core built on Power Architecture™
technology. It is a cost-effective, low-power, highly
integrated host processor that addresses the requirements of
several storage, consumer, and industrial applications,
including main CPUs and I/O processors in network attached
storage (NAS), voice over IP (VoIP) router/gateway,
intelligent wireless LAN (WLAN), set top boxes, industrial
controllers, and wireless access points. The MPC8315E
extends the PowerQUICC II Pro family, adding higher CPU
performance, new functionality, and faster interfaces while
addressing the requirements related to time-to-market, price,
power consumption, and package size. Note that while the
MPC8315E supports a security engine, the MPC8315 does
not.
Document Number: MPC8315EEC
Rev. 2, 11/2011
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. MPC8315E Features . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8
4. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 18
8. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9. Ethernet: Three-Speed Ethern et, MII Management . 24
10. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1 1. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
15. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 51
16. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
17. Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . 68
18. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
19. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
20. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
21. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
22. TDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
23. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 76
24. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
25. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
26. System Design Information . . . . . . . . . . . . . . . . . . 100
27. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 103
28. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
MPC8315E
PowerQUICC II Pro Processor
Hardware Specifications
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
2Freescale Semiconductor
Overview
1 Overview
The MPC8315E incorporates the e300c3 (MPC603e-based) core, which includes 16 Kbytes of L1
instruction and data caches, on-chip memory management units (MMUs), and floating-point support. In
addition to the e300 core, the SoC platform includes features such as dual enhanced three-speed 10, 100,
1000 Mbps Ethernet controllers (eTSECs) with SGMII support, a 32- or 16-bit DDR1/DDR2 SDRAM
memory controller, dual SATA 3 Gbps controllers (MPC8315E-specific), a security engine to accelerate
control and data plane security protocols, and a high degree of software compatibility with
previous-generation PowerQUICC processor-based designs for backward compatibility and easier
software migration. The MPC8315E also offers peripheral interfaces such as a 32-bit PCI interface with
up to 66 MHz operation, 16-bit enhanced local bus interface with up to 66 MHz operation, TDM interface,
and USB 2.0 with an on-chip USB 2.0 PHY.
The MPC8315E offers additional high-speed interconnect support with dual integrated SATA 3 Gbps
interfaces and dual single-lane PCI Express interfaces. When not used for PCI Express, the SerDes
interface may be configured to support SGMII. The MPC8315E security engine (SEC 3.3) allows
CPU-intensive cryptographic operations to be offloaded from the main CPU core. This figure shows a
block diagram of the MPC8315E.
Figure 1. MPC8315E Block Diagram
2 MPC8315E Features
The following features are supported in the MPC8315E.
2.1 e300 Core
The e300 core has the following features:
• Operates at up to 400 MHz
eTSEC
R TBI, SGMII
DUART
Interrupt
I2C
Timers
GPIO
Enhanced DDR1/DDR2
Controller
Controller
PCI
I/O
Sequencer
(IOS)
Security
Note: The MPC8315 do not include a security engine.
Local Bus,
USB 2.0 HS
Host/Device/OTG
ULPI On-Chip
HS PHY
SPI
Engine 3.3
PCI
Express
x1
SATA
PHY
DMA
SATA
PHY
TDM
RGMII, (R)MII
eTSEC
RTBI, SGMII
RGMII, (R)MII
16-KB
D-Cache
16-KB
I-Cache
e300c3 Core with
Power Management
FPU
PCI
Express
x1
MPC8315E
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
Freescale Semiconductor 3
MPC8315E Features
• 16-Kbyte instruction cache, 16-Kbyte data cache
• One floating point unit and two integer units
• Software-compatible with the Freescale processor families implementing the PowerPC
Architecture
• Performance monitor
2.2 Serial Interfaces
The following interfaces are supported in the MPC8315E.
• Two enhanced TSECs (eTSECs)
• Two Ethernet interfaces using one RGMII/MII/RMII/RTBI or SGMII (no GMII)
• Dual UART, one I2C, and one SPI interface
2.3 Security Engine
The security engine is optimized to handle all the algorithms associated with IPSec, 802.11i, and iSCSI.
The security engine contains one crypto-channel, a controller, and a set of crypto execution units (EUs).
The execution units are:
• Public key execution unit (PKEU)
— RSA and Diffie-Hellman (to 4096 bits)
— Programmable field size up to 2048 bits
— Elliptic curve cryptography (1023 bits)
— F2m and F(p) modes
— Programmable field size up to 511 bits
• Data encryption standard execution unit (DEU)
— DES, 3DES
— Two key (K1, K2) or three key (K1, K2, K3)
— ECB, CBC, CFB-64 and OFB-64 modes for both DES and 3DES
• Advanced encryption standard unit (AESU)
— Implements the Rinjdael symmetric key cipher
— Key lengths of 128, 192, and 256 bits
— ECB, CBC, CCM, CTR, GCM, CMAC, OFB, CFB, XCBC-MAC and LRW modes
— XOR acceleration
• Message digest execution unit (MDEU)
— SHA with 160-bit, 256-bit, 384-bit and 512-bit message digest
— SHA-384/512
— MD5 with 128-bit message digest
— HMAC with either algorithm
• Random number generator (RNG)
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
4Freescale Semiconductor
MPC8315E Features
— Combines a T rue Random Number Generator (TRNG) and a NIST-approved Pseudo-Random
Number Generator (PRNG) (as described in Annex C of FIPS140-2 and ANSI X9.62).
• Cyclical Redundancy Check Hardware Accelerator (CRCA)
— Implements CRC32C as required for iSCSI header and payload checksums, CRC32 as required
for IEEE 802 packets, as well as for programmable 32 bit CRC polynomials
2.4 DDR Memory Controller
The DDR1/DDR2 memory controller includes the following features:
• Single 16- or 32-bit interface supporting both DDR1 and DDR2 SDRAM
• Support for up to 266 MHz data rate
• Support for two physical banks (chip selects), each bank independently addressable
• 64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with x8/x16 data ports (no direct
x4 support)
• Support for one 16-bit device or two 8-bit devices on a 16-bit bus or two 16-bit devices on a 32-bit
bus
• Support for up to 16 simultaneous open pages
• Supports auto refresh
• On-the-fly power management using CKE
• 1.8-/2.5-V SSTL2 compatible I/O
2.5 PCI Contr oller
The PCI controller includes the following features:
• Designed to comply with PCI Local Bus Specification Revision 2.3
• Single 32-bit data PCI interface operates at up to 66 MHz
• PCI 3.3-V compatible (not 5-V compatible)
• Support for host and agent modes
• On-chip arbitration, supporting three external masters on PCI
• Selectable hardware-enforced coherency
2.6 TDM Interface
The TDM interface includes the following features:
• Independent receive and transmit with dedicated data, clock and frame sync line
• Separate or shared RCK and TCK whose source can be either internal or external
• Glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses
• Up to 128 time slots, where each slot can be programmed to be active or inactive
• 8- or 16-bit word widths
• The TDM Transmitter Sync Signal (TFS), Transmitter Clock Signal (TCK) and Receiver Clock
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
Freescale Semiconductor 5
MPC8315E Features
• Signal (RCK) can be configured as either input or output
• Frame sync and data signals can be programmed to be sampled either on the rising edge or on the
falling edge of the clock
• Frame sync can be programmed as active low or active high
• Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame
• MSB or LSB first support
2.7 USB Dual-Role Controller
The USB controller includes the following features:
• Designed to comply with USB Specification, Rev. 2.0
• Supports operation as a stand-alone USB device
— Supports one upstream facing port
— Supports three programmable USB endpoints
• Supports operation as a stand-alone USB host controller
— Supports USB root hub with one downstream-facing port
— Enhanced host controller interface (EHCI) compatible
• Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation.
Low-speed operation is supported only in host mode.
• Supports UTMI+ low pin interface (ULPI) or on-chip USB-2.0 full-speed/high-speed PHY
• Supports USB on-the-go mode, which includes both device and host functionality, when using an
external ULPI PHY
2.8 Dual PCI Express Interfaces
The PCI Express interfaces have the following features:
• PCI Express 1.0a compatible
• x1 link width
• Selectable operation as root complex or endpoint
• Both 32- and 64-bit addressing
• 128-byte maximum payload size
• Support for MSI and INTx interrupt messages
• Virtual channel 0 only
• Selectable Traffic Class
• Full 64-bit decode with 32-bit wide windows
• Dedicated descriptor based DMA engine per interface with separate read and write channels
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
6Freescale Semiconductor
MPC8315E Features
2.9 Dual Serial ATA (SATA) Controllers
The SATA controllers have the following features:
• Designed to comply with Serial ATA Rev 2.5 Specification
• ATAPI 6+
• Spread spectrum clocking on receive
• Asynchronous notification
• Hot plug including asynchronous signal recovery
• Link power management
• Native command queuing
• Staggered spin-up and port multiplier support
• SATA 1.5 and 3.0 Gbps operation
• Interrupt driven
• Power management support
• Error handling and diagnostic features
— Far end/near end loopback
— Failed CRC error reporting
— Increased ALIGN insertion rates
— Scrambling and CONT override
2.10 Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)
The eTSECs include the following features:
• Two SGMII/RGMII/MII/RMII/RTBI interfaces
• Two controllers designed to comply with IEEE Std 802.3™, IEEE 802.3u™, IEEE 802.3x™,
IEEE 802.3z™, IEEE 802.3au™, IEEE 802.3ab™, and IEEE Std 1588™
• Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating
mode
• MII management interface for external PHY control and status.
2.11 Integrated Programmable Interrupt Controller (IPIC)
The integrated programmable interrupt controller (IPIC) provides a flexible solution for general-purpose
interrupt control. The IPIC programming model is compatible with the MPC8260 interrupt controller and
supports external and internal discrete interrupt sources. Interrupts can also be redirected to an external
interrupt controller.
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
Freescale Semiconductor 7
MPC8315E Features
2.12 Power Management Controller (PMC)
The MPC8315E supports a range of power management states that significantly lower power consumption
under the control of the power management controller. The PMC includes the following features:
• Provides power management when the device is used in both PCI host and agent modes
• PCI Power Management 1.2 D0, D1, D2, D3hot, and D3cold states
• PME generation in PCI agent mode, PME detection in PCI host mode
• Wake-up from Ethernet (magic packet), USB, GPIO, and PCI (PME input as host) while in the D1,
D2 and D3hot states
• A new low-power standby power management state called D3warm
— The PMC, one Ethernet port, and the GTM block remain powered via a split power supply
controlled through an external power switch
— Wake-up events include Ethernet (magic packet), GTM, GPIO, or IRQ inputs and cause the
device to transition back to normal operation
— PCI agent mode is not be supported in D3warm state
• PCI Express-based PME events are not supported
2.13 Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) allows the MPC8315E to exchange data between other PowerQUICC
family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit.
2.14 DMA Controller, I2C, DUART, Enhanced Local Bus Controller
(eLBC), and Timer s
The integrated four-channel DMA controller includes the following features:
• Allows chaining (both extended and direct) through local memory-mapped chain descriptors
(accessible by local masters)
• Misaligned transfer capability for source/destination address
• Supports external DREQ, DACK and DONE signals
There is one I2C controller. This synchronous, multi-master buses can be connected to additional devices
for expansion and system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550
programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.
The eLBC port allows connections with a wide variety of external DSPs and ASICs. Three separate state
machines share the same external pins and can be programmed separately to access different types of
devices. The general-purpose chip select machine (GPCM) controls accesses to asynchronous devices
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
8Freescale Semiconductor
Electrical Characteristics
using a simple handshake protocol. The three user programmable machines (UPMs) can be programmed
to interface to synchronous devices or custom ASIC interfaces. Each chip select can be configured so that
the associated chip interface can be controlled by the GPCM or UPM controller. Both may exist in the
same system. The local bus can operate at up to 66 MHz.
The system timers include the following features: periodic interrupt timer, real time clock, software
watchdog timer, and two general-purpose timer blocks.
3 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8315E, which is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but they are included for complete reference. These are not purely I/O buffer
design specifications.
3.1 Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
3.1.1 Absolute Maximum Ratings
This table provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings 1
Characteristic Symbol Max Value Unit Note
Core supply voltage VDD –0.3 to 1.26 V —
PLL supply voltage AVDD –0.3 to 1.26 V —
DDR1 DRAM I/O supply voltage GVDD –0.3 to 2.7 V —
DDR2 DRAM I/O supply voltage GVDD –0.3 to 1.9 V —
PCI, local bus , DUART, system control and power
management, I2C, Ethernet management, 1588 timer and
JTA G I/O voltage
NVDD –0.3 to 3.6 V 7
USB, and eTSEC I/O voltage LVDD –0.3 to 2.75 or
–0.3 to 3.6 V6, 8
PHY voltage USB PHY USB_PLL_PWR1 –0.3 to 1.26 V —
USB_PLL_PWR3,
USB_VDDA_BIAS,
VDDA
–0.3 to 3.6 V —
SERDES PHY XCOREVDD,
XPADVDD,
SDAVDD
–0.3 to 1.26 V —
SATA PHY SATA_VDD,
VDD1IO,
VDD1ANA
–0.3 to 1.26 V —
VDD33PLL,
VDD33ANA –0.3 to 3.6 V —
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
Freescale Semiconductor 9
Electrical Characteristics
3.1.2 Power Supply Voltage Specification
This table provides the recommended operating conditions for theMPC8315E. Note that the values in this
table are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
Input voltage DDR DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 4
DDR DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 4
eTSEC signals LVIN –0.3 to (LVDD + 0.3) V 3, 4
Local bus , DU AR T, SYS_CLK_IN, system
control and power management, I2C, and
JTAG signals
NVIN –0.3 to (NVDD + 0.3) V 3, 4
PCI NVIN –0.3 to (NVDD + 0.3) V 5
SATA_CLKIN NVIN –0.3 to (NVDD + 0.3) V 3, 4
Storage temperature range TSTG –55 to150 C—
Note:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect de vice reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceede d for a maxim u m of 20 ms du ring
power-on reset and power-down sequences.
3. Caution: (N,L)VIN must not exceed (N,L)VDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms
during power-on reset and power-down sequences.
4. (M,N,L)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
5. NVIN on the PCI interface ma y o vershoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 2.
6. The max value of supply voltage should be selected based on the RGMII mode.
7. NVDD means NVDD1_OFF, NVDD1_ON, NVDD2_OFF, NVDD2_ON, NVDD3 _OFF, NVDD4_OFF
8. LVDD means LVDD1_OFF and LVDD2_ON
Table 2. Recommended Operating Conditions
Characteristic Symbol Recommended
Value1Unit Status in D3
Warm mode Note
SerDes inter nal digital power XCOREVDD 1.0 ± 50 mv V Switched Off —
SerDes internal digital power XCOREVSS 0.0 V — —
SerDes I/O digital power XPADVDD 1.0 ± 50 mv V Switched Off —
SerDes I/O digital pow er XPADVSS 0.0 V — —
SerDes analog power for PLL SDAVDD 1.0 ± 50 mv V Sw itched Off —
SerDes analog power for PLL SDAVSS 0.0 V — —
Dedicated 3.3 V analog power for USB PLL USB_PLL_PWR3 3.3 ± 165mv V Switched Off —
Dedicated 1.0 Vanalog power for USB PLL USB_PLL_PWR1 1.0 ± 50 mv V Switched Off —
Dedicated analog ground for USB PLL USB_PLL_GND 0.0 V — —
Dedicated USB power for USB bias circuit USB_VDD A_BIAS 3.3 ± 300 mv V Switched Off —
Table 1. Absolute Maximum Ratings 1 (continued)
Characteristic Symbol Max Value Unit Note
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
10 Freescale Semiconductor
Electrical Characteristics
Dedicated USB ground for USB bias circuit USB_VSSA_BIAS 0.0 V — —
Dedicated power for USB transceiver USB_VDDA 3.3 ± 300 mv V Switched Off —
Dedicated ground for USB transceiver USB_VSSA 0.0 V — —
SATA digital power SATA_ VDD 1.0 ± 50 mv V Switched Off —
SATA digital ground SATA_VSS 0.0 V — —
SATA analog I/O power VDD1IO 1.0 ± 50 mv V Switched Off —
SATA analog I/O ground VSS1IO 0.0 V — —
SATA core analog power VDD1ANA 1.0 ± 50 mv V Switched Off —
SATA analog ground VSS1ANA 0.0 V — —
SATA analog power PLL VDD33PLL 3.3 ± 165 mv V Switched Off —
SATA 3.3 analog power VDD33ANA 3.3 ± 165 mv V Switched Off —
SATA reference analog ground VSSRESREF 0.0 V — —
Core supply voltage VDD 1.0 ± 50 mv V Switched Off —
Core supply voltage VDDC 1.0 ± 50 mv V Switched On —
Analog power for e300 core APLL AVDD1 1.0 ± 50 mv V Switched Off 6
Analog power for system APLL AVDD2 1.0 ± 50 mv V Switched On 6
DDR and DDR2 DRAM I/O voltage GVDD 2.5 ± 200 mv
1.8 ± 100 mv V Switched Off —
Diff erential ref erence voltage for DDR and DDR2
controller MVREF GVDD /2 V Switched Off —
Standard I/O voltage NVDD1_ON 3.3 ± 300 mv V Switched On 1
Standard I/O voltage NVDD2_ON 3.3 ± 300 mv V Switched On 1
Standard I/O voltage NVDD1_OFF 3.3 ± 300 mv V Switched Off 2
Standard I/O voltage NVDD2_OFF 3.3 ± 300 mv V Switched Off 2
Standard I/O voltage NVDD3_OFF 3.3 ± 300 mv V Switched Off 2
Standard I/O voltage NVDD4_OFF 3.3 ± 300 mv V Switched Off 2
eTSEC/USBdr I/O supply LVDD1_OFF 2.5 ± 125 mv
3.3 ± 300 mv V Switched Off —
eTSEC I/O supply LVDD2_ON 2.5 ± 125 mv
3.3 ± 300 mv V Switched On —
Analog and digital ground VSS 0.0 V — —
Junction temperature range TA/TJ0 to105 C— 3
Table 2. Recommended Operating Conditions (continued)
Characteristic Symbol Recommended
Value1Unit Status in D3
Warm mode Note
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
Freescale Semiconductor 11
Electrical Characteristics
This figure shows the undershoot and overshoot voltages at the interfaces of the MPC8315E.
Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD
3.1.3 Output Driver Characteristics
This table provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Note:
1. The NVDDx_ON are static power supplies and can be connected together.
2. The NVDDx_OFF are switchable power supplies and can be connected together.
3. Minimum Temperature is specified with TA;maximum temperature is specified with TJ.
4. All Power rails must be connected and power applied to the MPC8315 even if the IP interfaces are not used.
5. All I/O pins should be interfaced with peripherals operating at same voltage level.
6. This vo ltage is the input to the filter discussed in Section 26.2, “PLL Po wer Supply Filtering” and not necessarily the voltage
at the AVDD pin.
7. All 1V power supplies should be derived from the same source.
Table 3. Output Drive Capability
Driver Type Output
Impedance ()Supply
Voltage
Local bus interface utilities signals 42 NVDD = 3.3 V
PCI signals 25
DDR signal118 GVDD = 2.5 V
DDR2 signal 1 18 GVDD = 1.8 V
Table 2. Recommended Operating Conditions (continued)
Characteristic Symbol Recommended
Value1Unit Status in D3
Warm mode Note
GND
GND – 0.3 V
GND – 0.7 V Not to Exceed 10%
G/L/NVDD + 20%
G/L/NVDD
G/L/NVDD + 5%
of tinterface1
1. tinterface refers to the clock period associated with the bus clock interface.
VIH
VIL
Note:
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
12 Freescale Semiconductor
Electrical Characteristics
3.2 Power Sequencing
The MPC8315E does not require the core supply voltage (VDD and VDDC) and I/O supply voltages
(GVDD, LVDDx_ON, LVDDx_OFF, NVDDx_ON and NVDDx_OFF) to be applied in any particular
order. During the power ramp up, before the power supplies are stable, if the I/O voltages are supplied
before the core voltage, there may be a period of time when all input and output pins be actively driven
and cause contention and/or excessive current. In order to avoid actively driving the I/O pins and to
eliminate excessive current draw, apply the continuous core voltage (VDDC) before the continuous I/O
voltages (LVDDx_ON and NVDDx_ON) and switchable core voltage (VDD) before the switchable I/O
voltages (GVDD, LVDDx_OFF, and NVDDx_OFF). PORESET should be asserted before the continuous
power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply
must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 3. Once all the power
supplies are stable, wait for a minimum of 32 clock cycles before negating PORESET.
The I/O power supply ramp-up slew rate should be slower than 4V/100 s, this requirement is for ESD
circuit.
This figure shows the power-up sequencing for switchable and continuous supplies.
Figure 3. Power-Up Sequencing
When switching from nor mal mode to D3 warm (s tandby) mode, first turn off the switchable I/O voltage
supply and then turn off the switchable core voltage supply. Similarly, when switching from D3 warm
(standby) mode to normal mode, first turn on the switchable core voltage supply and then turn on the
switchable I/O voltage supply.
DUART, system control, I2C, JTAG,SPI 42 NVDD = 3.3 V
GPIO signals 42 NVDD = 3.3 V
eTSEC 42 LVDD = 3.3 V / 2.5 V
1Output Impedance can also be adjusted through configurable options in DDR
Control Dr iver Register (DDRCDR). See the MPC8315E PowerQUICC II Pro
Integrated Host Processor Family Reference Manual.
Table 3. Output Drive Capability (continued)
Driver Type Output
Impedance ()Supply
Voltage
Continuous I/O Voltage
Continuous Core Voltage
0.7 V
90%
t
VSwitchab le I/O Voltage
Switchable Core Voltage (VDD)
0.7 V
90%
t
V
Power sequence for continuous power supplies Power sequence for switchable power supplies
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
Freescale Semiconductor 13
Electrical Characteristics
CAUTION
When the device is in D3 warm (standby) mode, all external voltage
supplies applied to any I/O pins, with the exception of wake-up pins, must
be turned off. Applying supplied external voltage to any I/O pins, except the
wake up pins, while the device is in D3 warm standby mode may cause
permanent damage to the device.
An example of the power-u p sequence is shown in Figure 4 when implemented along with low power D3
warm mode.
Figure 4. Power Up Sequencing Example with Low power D3 Warm Mode
The switchable and continuous supplies can be combined when the D3 warm mode is not used.
The SATA power supplies VDD33PLL and VDD33ANA should go high after NVDD3_OFF supply and
go low before NVDD3_OFF supply. The NVDD3_OFF voltage levels should not drop below the
VDD33PLL, VDD33ANA voltages at any time.
Continuous I/O Voltage
Continuous Core Voltage
90%
PORESET
tSYS_CLK_IN / tPCI_SYNC_IN >= 32 clock
t
V
Switchable Core Voltage
Switchable I/O Voltage
(LVDDx_ON, NVDDx_ON) (GVDD, LVDDx_OFF, NVDDx_OFF)
VDDC (VDD)
0
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
14 Freescale Semiconductor
Power Characteristics
This figure shows the SATA power supplies.
Figure 5. SATA Power Supplies
4 Power Characteristics
This table shows the estimated typical power dissipation for this family of devices.
This table shows the estimated typical I/O power dissipation for this family of devices.
Table 4. MPC8315E Power Dissipation
(Does not include I/O power dissipation)
Core Frequency (MHz) CSB Frequency (MHz) Typical 1,3 Maximum 1,2 Unit
266 133 1.116 1.646 W
333 133 1.142 1.665 W
400 133 1.167 1.690 W
Note:
1. The values do not include I/O supply power, but do include core, AVDD, USB PLL, digital SerDes power, and
SATA PHY power.
2. Maximum power is based on a voltage of Vdd = 1.05V, a junction temperature of Tj = 105°C, and an artificial
smoker test.
3. Typical power is based on a voltage of Vdd = 1.05V, and an artificial smoker test running at room temp erature.
Table 5. MPC8315E Power Dissipation
Interface Frequency GVDD
(1.8 V) GVDD
(2.5 V) NVDD
(3.3 V)
LVDD1_OFF/
LVDD2_ON
(3.3V)
LVDD2
_ON
(3.3V)
VDD33PLL,
VDD33ANA
(3.3V)
SATA_VDD ,
VDD1IO,
VDD1ANA
(1.0V)
XCOREVDD,
XPADVDD,
SDAVDD
(1.0V)
Unit
DDR 1
Rs = 22
Rt = 50
266MHz,
32 bits —0.323— — — — — — W
200MHz,
32 bits —0.291— — — — — — W
VDD33_PLL &
VDD33_ANA
NVDD3_OFF
Voltage
Time
NVDD3_OFF
t Š 0
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
Freescale Semiconductor 15
Clock Input Timing
5 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8315E.
DDR 2
Rs = 22
Rt = 75
266MHz,
32 bits 0.246 — — — — — — — W
200MHz,
32bits 0.225 — — — — — — — W
PCI I/O
load = 50pF 33 MHz — — 0.120 — — — — — W
66 MHz — — 0.249 — — — — — W
Local bus I/O
load = 20pF 66 MHz——— — 0.056 — — — W
50 MHz——— — 0.040 — — — W
eTSEC I/O
load = 20pF
Multiple by
number of
interface
used
MII, 25MHz — — — 0.008 — — — — W
RGMII,
125MHz
(3.3V)
— — — 0.078 — — — — W
RGMII,
125MHz
(2.5V)
— — — 0.044 — — — — W
USBDR
Controller
(ULPI mode)
load =20pF
60 MHz — — — 0.078 — — — — W
USBDR+
Internal PHY
(UTMI mode)
480 MHz — — — 0.274 — — — — W
PCI Express
two x1lane 2.5 GHz — — — — — — — 0.190 W
SATA two
ports 3.0 GHz — — — — — 0.021 0.20 6 — W
Other I/O — — — 0.015 — — — — — W
Table 5. MPC8315E Power Dissipation (continued)
Interface Frequency GVDD
(1.8 V) GVDD
(2.5 V) NVDD
(3.3 V)
LVDD1_OFF/
LVDD2_ON
(3.3V)
LVDD2
_ON
(3.3V)
VDD33PLL,
VDD33ANA
(3.3V)
SATA_VDD ,
VDD1IO,
VDD1ANA
(1.0V)
XCOREVDD,
XPADVDD,
SDAVDD
(1.0V)
Unit
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
16 Freescale Semiconductor
Clock Input Timing
5.1 DC Electrical Characteristics
This table provides the clock input (SYS_CLK_IN/PCI_SYNC_IN) DC timing specifications for the
MPC8315E.
5.2 AC Electrical Characteristics
The primary clock source for the MPC8315E can be one of two inputs, SYS_CLK_IN or PCI_CLK,
depending on whether the device is configured in PCI host or PCI agent mode. This table provides the
clock input (SYS_CLK_IN/PCI_CLK) AC timing specifications for the MPC8315E.
Table 6. SYS_CLK_IN DC Electrical Characteristics
Parameter Condition Symbol Min Max Unit
Input high voltage — VIH 2.4 NVDD + 0.3 V
Input low voltage — VIL -0.3 0.4 V
SYS_CLK_IN input current 0 V VIN NVDD IIN —±10A
SYS_XTAL_IN input current 0 V VIN NVDD IIN —±40A
PCI_SYNC_IN input current 0 V VIN NVDD IIN —±10A
RTC_CLK input current 0 V VIN NVDD IIN —±10A
USB_CLK_IN input current 0 V VIN NVDD IIN —±10A
USB_XTAL_IN input current 0 V VIN NVDD IIN —±40A
SATA_CLK_IN input current 0 V VIN NVDD IIN —±10A
Table 7. SYS_CLK_IN A C Timing Specifications
Parameter/Condition Symbol Min Typical Max Unit Note
SYS_CLK_IN/PCI_CLK frequency fSYS_CLK_IN 24 — 66.67 MHz 1, 6, 7
SYS_CLK_IN/PCI_CLK cycle time tSYS_CLK_IN 15 — 41.6 ns 6
SYS_CLK_IN rise and fall time tKH, tKL 0.6 — 4 ns 2, 6
PCI_CLK rise and fall time tPCH, tPCL 0.6 0.8 1.2 ns 2
SYS_CLK_IN/PCI_CLK duty cycle tKHK/tSYS_CLK_IN 40 — 60 % 3, 6
SYS_CLK_IN/PCI_CLK jitter — — — ±150 ps 4, 5, 6
Note:
1. Caution: The system, core, and security block must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for SYS_CLK_IN/PCI_CLK are specified at 20% to 80% of signal swing.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN/PCI_CLK driv er’ s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set
low to allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
6. The parameter names PCI_CLK and PCI_SYNC_IN are used interchangeably in this document.
7. Spread spectrum is allowed up to 1% down-spread at 33kHz.(max. rate).
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
Freescale Semiconductor 17
RESET Initialization
6 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8315E.
6.1 RESET DC Electrical Characteristics
This table provides the DC electrical characteristics for the RESET pins of the MPC8315E.
6.2 RESET AC Electrical Characteristics
This table provides the reset initialization AC timing specifications of the MPC8315E.
Table 8. RESET Pins DC Electrical Characteris tics
Characteristic Symbol Condition Min Max Unit
Input high voltage VIH — 2.0 NVDD + 0.3 V
Input low voltage VIL —–0.30.8V
Input current IIN 0 V VIN NVDD — ±5 A
Output high voltage VOH IOH = –8.0 mA 2.4 — V
Output low voltage VOL IOL = 8.0 mA — 0.5 V
Output low voltage VOL IOL = 3.2 mA — 0.4 V
Table 9. RESET Initialization Timing Specifications
Parameter/Condition Min Max Unit Note
Required assertion time of HRESET to activate reset flow 32 — tPCI_SYNC_IN 1
Required ass ertion time of PORESET with stable clock applied to SYS_CLK_IN
when the device is in PCI host mode 32 — tSYS_CLK_IN 2
Required ass ertion time of PORESET with stable clock applied to PCI_SYNC_IN
when the device is in PCI agent mode 32 — tPCI_SYNC_IN 1
HRESET assertion (output) 512 — tPCI_SYNC_IN 1
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3] and
CFG_SYS_CLKIN_DIV) with respect to negation of PORESET when the device is
in PCI host mode
4—t
SYS_CLK_IN 2, 4
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3] and
CFG_SYS_CLKIN_DIV) with respect to negation of PORESET when the device is
in PCI agent mode
4—t
PCI_SYNC_IN 1
Input hold time for POR configuration signals with respect to negation of HRESET 0— ns —
Time fo r the device to turn off POR configuration signals with respect to the
assertion of HRESET —4 ns 3
Time fo r the device to turn on POR config signals with respect to the negation of
HRESET 1—t
PCI_SYNC_IN 1, 3
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
18 Freescale Semiconductor
DDR and DDR2 SDRAM
This table provides the PLL lock times.
7 DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8315E. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
7.1 DDR and DDR2 SDRAM DC Electrical Characteristics
This table provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
MPC8315E when GVDD(typ) = 1.8 V.
Note:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the de vice is In PCI host mode the primary
clock is applied to the SYS_CLK_IN input, and PCI_SYNC_IN period depends on the value of CFG_SYS_CLKIN_DIV.
2. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. It is only v alid when the device is in PCI host mode.
3. POR configuration signals consists of CFG_RESET_SOURCE[0:3] and CFG_SYS_CLKIN_DIV.
4. The parameter names CFG_SYS_CLKIN_DIV and CFG_CLKIN_DIV are used interchangeably in this document.
Table 10. PLL Lock Times
Parameter/Condition Min Max Unit Note
System PLL lock times — 100 s—
e300 core PLL lock times — 100 s—
SerDes (SGMII/PCI Exp Phy) PLL lock times — 100 s—
USB phy PLL lock times — 100 s—
SATA phy PLL lock times — 100 s—
Table 11. DDR2 SDRAM DC Electrical Characteri stic s for GVDD(typ) = 1.8 V
Parameter/Condition Symbol Min Max Unit Note
I/O supply voltage GVDD 1.7 1.9 V 1
I/O reference voltage MVREF 0.49 GVDD 0.51 GVDD V 2
I/O ter mi nation voltage VTT MVREF – 0.04 MVREF + 0.04 V 3
Input high voltage VIH MVREF+ 0.125 GVDD + 0.3 V —
Input low voltage VIL –0.3 MVREF – 0.125 V —
Output leakage current IOZ –9.9 9.9 A4
Output high current (VOUT = 1.420 V,
GVDD= 1. 7V) IOH –13.4 — mA —
Output low current (VOUT = 0.280 V) IOL 13.4 — mA
Table 9. RESET Initialization Timing Specifications (continued)
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
Freescale Semiconductor 19
DDR and DDR2 SDRAM
This table provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
This table provides the recommended operating conditions for the DDR SDRAM component(s) of the
MPC8315E when GVDD(typ) = 2.5 V.
This table provides the DDR capacitance when GVDD(typ) = 2.5 V.
Note:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 GVDD , and to track GVDD DC variations as measured at the receiver . Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device . It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track var iations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD.
Table 12. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
Parameter/Condition Symbol Min Max Unit Note
Input/output capacitance: DQ, DQS CIO 68pF1
Delta input/output capacitan ce: DQ, DQS CDIO —0.5pF1
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, V OUT (peak- to-peak) = 0.2 V.
Table 13. DDR SDRAM DC Electrical Charact eristics for GVDD(typ) = 2.5 V
Parameter/Condition Symbol Min Max Unit Note
I/O supply vo lt age GVDD 2.3 2.7 V 1
I/O reference voltage MVREF 0.49 GVDD 0.51 GVDD V 2
I/O termination voltage VTT MVREF – 0.04 MVREF + 0.04 V 3
Input high voltage VIH MVREF + 0.15 GVDD + 0.3 V —
Input low voltage VIL –0.3 MVREF – 0.15 V —
Output leakage current IOZ –9.9 –9.9 A4
Output high current (VOUT = 1.95 V,
GVDD = 2.3V) IOH –16.2 — mA —
Output low current (VOUT = 0.35 V) IOL 16.2 — mA —
Note:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 GVDD , and to track GVDD DC variations as measured at the receiver . P eak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal ter m ination is made and is expected to be
equal to MVREF. This rail should track variati ons in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD.
Table 14. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V Interface
Parameter/Condition Symbol Min Max Unit Note
Input/output capacitance: DQ,DQS CIO 68pF1
Table 11. DDR2 SDRAM DC Electrical Characteristics for GVDD(t yp) = 1.8 V (continued)
Parameter/Condition Symbol Min Max Unit Note
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
20 Freescale Semiconductor
DDR and DDR2 SDRAM
This table provides the current draw characteristics for MVREF.
7.2 DDR and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.
7.2.1 DDR and DDR2 SDRAM Input AC Timing Specifications
This table lists the input AC timing specifications for the DDR2 SDRAM (GVDD(typ) = 1.8 V).
This table lists the input AC timing specifications for the DDR SDRAM when GVDD(typ)=2.5 V.
The following two tables list the input AC timing specifications for the DDR SDRAM interface.
Delta input/output capacitan ce: DQ, DQS CDIO —0.5pF1
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, T A =25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 15. Current Draw Characteristics f or MVREF
Pa rameter / Condition Symbol Min Max Unit Note
Current draw for MVREF IMVREF — 500 A1
Note:
1. The voltage regulator for MVREF must be able to supply up to 500 A current.
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with GVDD of 1.8V ± 100 mV
Parameter Symbol Min Max Unit Note
A C input low voltage VIL — MVREF – 0.45 V —
A C input high voltage VIH MVREF + 0.45 — V —
Table 17. DDR SDRAM Input AC Timing Specifications for 2.5 V Interface
At recommended operating conditions with GVDD of 2.5V ± 200 mV
Parameter Symbol Min Max Unit Note
A C input low voltage VIL — MVREF – 0.51 V
A C input high voltage VIH MVREF + 0.51 — V
Table 18. DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 V± 100 mV)
Parameter Symbol Min Max Unit Note
Controller Skew for MDQS—MDQ 266 MHz
200 MHz
tCISKEW –875
–1250 875
1250
ps 1, 2, 3
Table 14. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V Interface
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
Freescale Semiconductor 21
DDR and DDR2 SDRAM
This figure shows the DDR SDRAM input AC timing for the tolerated MDQS to MDQ skew (tDISKEW)
Figure 6. Timing Diagram for tDISKEW
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit to
be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is
the absolute value of tCISKEW.
3. Memory controller ODT value of 150 is recommended.
Table 19. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of (2.5V ± 200 mV)
Parameter Symbol Min Max Unit Note
Controller Skew for MDQS—MDQ 266 MHz
200 MHz
tCISKEW –750
–1250 750
1250
ps 1, 2
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit to
be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the f ollowing equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
Table 18. DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 V± 100 mV)
Parameter Symbol Min Max Unit Note
MCK[n]
MCK[n] tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1D0
tDISKEW
MPC8315E PowerQUICC II Pro Processor Hardware Specifications , Rev. 2
22 Freescale Semiconductor
DDR and DDR2 SDRAM
7.2.2 DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions
Parameter Symbol 1Min Max Unit Note
MCK[n] cycle time at MCK[n]/MCK[n] crossing tMCK 7.5 10 ns 2
ADDR/CMD output setup with respect to MCK266 MHz
200 MHz
tDDKHAS 2.9
3.5 —
—
ns 3
ADDR/CMD output hold with respect to MCK 266 MHz
200 MHz
tDDKHAX 3.15
4.20 —
—
ns 3
MCS[n] output setup with respect to MCK 266 MHz
200 MHz
tDDKHCS 3.15
4.20 —
—
ns 3
MCS[n] output hold with respect to MCK 266 MHz
200 MHz
tDDKHCX 3.15
4.20 —
—
ns 3
MCK to MDQS Skew tDDKHMH –0.6 0.6 ns 4
MDQ//MDM output setup with respect to MDQS
266 MHz
200 MHz
tDDKHDS,
tDDKLDS 900
1000 —
—
ps 5
MDQ//MDM output hold with respect to MDQS266 MHz
200 MHz
tDDKHDX,
tDDKLDX 1100
1200 —
—
ps 5
MDQS preamble start tDDKHMP –0.5 tMCK – 0.6 –0.5 tMCK + 0.6 ns 6
MDQS epilogue end tDDKHME –0.6 0.6 ns 6
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal) (state) (reference)(state) for
inputs and t(first two letters of functional b lock)(ref ere nce)(state)(signal)(state) f or outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference cl ock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time . Also , tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory cloc k ref erence
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM /MDQ S.
4. Not e th at tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through
control of the DQSS ov erride bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust
in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters hav e been set to the
same adjustment value . See the MPC8315E P owerQ UICC II Pro Integrated Host Processor F amily Reference Manual for a
description and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possib le sk e w between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (),
or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions descr ibed in note 1.