Publication Number S71PL-N_00 Revision AAmendment 11 Issue Date June 9, 2010
S71PL-N MirrorBit® MCPs
S71PL-N MirrorBit® MCPs Cover Sheet
S71PL256N, S71PL127N, S71PL129N
256/128/128 Megabit (16/8/8 M x 16-Bit)
CMOS 3.0 Volt-only Simultaneous Read/Write,
Page Mode Flash Memory
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
ii S71PL-N MirrorBit® MCPs S71PL-N_00_A11 June 9, 2010
Data Sheet
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
Publication Number S71PL-N_00 Revision AAmendment 11 Issue Date June 9, 2010
Features
Speed
– Flash: 70 ns
– pSRAM: 70 ns
8.0 x 11.6 x 1.2 mm Packages
– 84-Ball Fine-Pitch Ball Grid Array (FBGA)
S71PL256NC0
S71PL256ND0
– 64 Ball Fine-Pitch Ball Grid Array (FBGA)
S71PL129NB0
S71PL129NC0
S71PL127NB0
S71PL127NC0
Speed
– Flash: 70 ns
– pSRAM: 70 ns
Operating Temperature Range
– Temperature Range of –25°C to +85°C
General Description
This document contains information for the S71PL-N MirrorBit MCP product. For detailed specifications, please refer to the
individual data sheets:
S71PL-N MirrorBit® MCPs
S71PL256N, S71PL127N, S71PL129N
256/128/128 Megabit (16/8/8 M x 16-Bit)
CMOS 3.0 Volt-only Simultaneous Read/Write,
Page Mode Flash Memory
Data Sheet
Document Publication Identification Number (PID)
S29PL-N S29PL-N_00
32M pSRAM Type 8 (90 nm) comspec_02
32M pSRAM Type 8 (130 nm) pSRAM_31
32M pSRAM Type 7 pSRAM_29
32M pSRAM Type 2 pSRAM_19
64M pSRAM Type 2 pSRAM_20
64M pSRAM Type 8 (90 nm) SPH064D970R1R
64M pSRAM Type 8 (130 nm) pSRAM_32
128M pSRAM Type 2 pSRAM_15
2 S71PL-N MirrorBit® MCPs S71PL-N_00_A11 June 9, 2010
Data Sheet
1. Flash/RAM Combinations Table
2. Product Selector Guide
pSRAM Density
32 Mb 64 Mb 128 Mb
Flash Density
PL127N S71PL127NB0 S71PL127NC0
PL129N S71PL129NB0 S71PL129NC0
PL256N S71PL256NC0 S71PL256ND0
Device pSRAM Density pSRAM Type
S71PL127NB0 32 Mb pSRAM Type 2
S71PL127NB0 32 Mb pSRAM Type 7
S71PL127NB0 32 Mb pSRAM Type 8 (90 & 130 nm)
S71PL127NC0 64 Mb pSRAM Type 2
S71PL127NC0 64 Mb pSRAM Type 8 (90 & 130 nm)
S71PL129NB0 32 Mb pSRAM Type 2
S71PL129NB0 32 Mb pSRAM Type 7
S71PL129NB0 32 Mb pSRAM Type 8 (130 nm)
S71PL129NC0 64 Mb pSRAM Type 2
S71PL129NC0 64 Mb pSRAM Type 8 (90 & 130 nm)
S71PL256NC0 64 Mb pSRAM Type 2
S71PL256NC0 64 Mb pSRAM Type 8 (90 & 130 nm)
S71PL256ND0 128 Mb pSRAM Type 2
June 9, 2010 S71PL-N_00_A11 S71PL-N MirrorBit® MCPs 3
Data Sheet
3. Ordering Information
The order number is formed by a valid combinations of the following:
S71PL 256 N C0 HF W 5B 0
Packing Type
0=Tray
2 = 7” Tape and Reel
3 = 13” Tape and Reel
Model Number (VIO Range, Package Type)
Refer to the Valid Combinations table below
Temperature Range
W = Wireless (–25°C to +85°C)
Package Type & Material Set
HA = MCP BGA, 1.2 mm height, 0.8 mm pitch, Lead (Pb)-free Compliant package
HF = MCP BGA, 1.2 mm height, 0.8 mm pitch, Lead (Pb)-free package
HH = MCP BGA, 1.2 mm height, 0.8 mm pitch, Low-Halogen, Lead (Pb)-free
package
pSRAM Density
B0 = 32 Mb pSRAM
C0 = 64 Mb pSRAM
D0 = 128 Mb pSRAM
Process Technology
N = 110 nm MirrorBit® Te chn ol ogy
Flash Density
256= 256 Mb
129= 128 Mb (Dual CE#)
127= 128 Mb (Single CE#)
Product Family
S71PL =3.0 Volt-only Simultaneous Read/Write, Page Mode Flash Memory
4 S71PL-N MirrorBit® MCPs S71PL-N_00_A11 June 9, 2010
Data Sheet
3.1 Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
Notes:
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type designator from ordering part number.
3. Contact factory for availability for any of the OPNs listed since RAM type availability may vary over time.
4. Part not recommended for new designs.
5. MCP with 90 nm Type 8 pSRAM has package material character F for Pb-free but also satisfies low-Halogen requirement.
Table 3.1 Valid Combinations
Base Ordering
Part Number (2)
Package &
Temperature
Model
Number
Packing
Type
pSRAM
Type
Flash
Speed
Option
pSRAM
Speed
Options Package Name
S71PL127NB0 HAW, HFW
4B (4)
0, 2, 3
(1), (2)
Ty p e 2
70 ns 70 ns
TLA064 -
8 x 11.6 x 1.2 mm,
64-ball
4U Type 8
4Z (4) Typ e 7
HHW 4U Type 8
S71PL127NC0
HAW, HFW
4B (4) Typ e 2
4U Type 8 (5)
S71PL129NB0
4B (4) Typ e 2
4U (4) Ty p e 8
4Z (4) Typ e 7
S71PL129NC0 4B (4) Ty pe 2
4U (4) Type 8 (5)
S71PL256NC0 5B (4) Ty pe 2 TLA084-
8 x 11.6 x 1.2 mm, 84-ball
5U (4) Type 8 (5)
S71PL256ND0 5B (4) Ty pe 2 TSB084 -
8 x 11.6 x 1.2, 84-ball
June 9, 2010 S71PL-N_00_A11 S71PL-N MirrorBit® MCPs 5
Data Sheet
4. Block Diagram
Notes:
1. RY/BY# is an open drain output.
2. AMAX = A23 (PL256N), A22 (PL127N), A21 (PL129N).
VSS
RESET#
Flash 1
IO15-IO0
VCCf
DQ15 to DQ0
RY/BY#
WP#/ACC
VCC
VCC
F1-CE#
Flash-only Address
Shared Address
OE#
WE#
VCCS
VCC
CE#s
UB#s
LB#s
CE#
UB#
LB#
pSRAM/SRAM
CE2
6 S71PL-N MirrorBit® MCPs S71PL-N_00_A11 June 9, 2010
Data Sheet
5. Physical Dimensions/Connection Diagrams
This section shows the I/O designations and package specifications for the S71PL-N.
5.1 Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
5.2 S71PL256N TLA084/TSB084
Figure 5.1 84-ball Fine-Pitch Ball Grid Array (S71PL256N)
Note:
Top view—balls facing down.
The addresses that are shared vary by MCP combination as shown in the table below:
Flash-only Addresses Shared Addresses
S71PL256NC0 A23-A22 A21:A0
S71PL256ND0 A23 A22:A0
Legend:
pSRAM Only
DNU
(Do Not Use)
All Shared
Flash Only
X
X
XX
X
X
XX
B2 B3 B4 B5 B6 B7 B8 B9
RFU RFURFURFURFURFU RFURFU
C2 C9
A7 A11A8WE#R-LB#RFU RFUWP#/ACC
C3C3
C3C3
C6C6
C6C6
C7C7
C7C7
C8C8
C8C8
D2 D4 D9
A6 A12A19R-CE2R-UB#A3 A15F-RST#
D3D3
D3D3
D6D6
D6D6
D7D7
D7D7
D8D8
D8D8
C5
D5
E2 E4 E9
A5 A13A9A20A18A2 A21RY/BY#
E3E3
E3E3
E6E6
E6E6
E7E7
E7E7
E8E8
E8E8
E5
C4C4
C4C4
F2 F4 F9
A4 A14A10A23A17A1 A22RFU
F3F3
F3F3
F7F7
F7F7
F8F8
F8F8
F5 F6
DNU
A1 DNU
A10
G2 G4 G9
VSS RFUDQ6RFUDQ1A0 A16RFU
G3G3
G3G3
G7G7
G7G7
G5 G6 G8
H2 H4 H9
OE# DQ15DQ13DQ4DQ9F-CE# RFUDQ3
H3H3
H3H3
H6H6
H6H6
H7H7
H7H7
H8H8
H8H8
H5
J2 J4 J9
DQ0 DQ7DQ12R-VCC
DQ10R-CE1# VSSF-VCC
J3J3
J3J3
J6J6
J6J6
J7J7
J7J7
J8J8
J8J8
J5
K2 K4 K9
DQ8 DQ14DQ5RFUDQ2RFU RFUDQ11
K3K3
K3K3
K7K7
K7K7
K8K8
K8K8
K5 K6
L2 L3 L4 L5 L6 L7 L8 L9
RFU RFURFURFURFURFU RFUF-VCC
DNU
M1 DNU
M10
June 9, 2010 S71PL-N_00_A11 S71PL-N MirrorBit® MCPs 7
Data Sheet
Figure 5.2 TSB084 Physical Dimensions
3439 \ 16-038.22 \ 01.04.05
PACKAGE TSB 084
JEDEC N/A
D x E 11.60 mm x 8.00 mm
PACKAGE
SYMBOL MIN NOM MAX NOTE
A --- --- 1.20 PROFILE
A1 0.17 --- --- BALL HEIGHT
A2 0.81 --- 0.97 BODY THICKNESS
D 11.60 BSC. BODY SIZE
E 8.00 BSC. BODY SIZE
D1 8.80 BSC. MATRIX FOOTPRINT
E1 7.20 BSC. MATRIX FOOTPRINT
MD 12 MATRIX SIZE D DIRECTION
ME 10 MATRIX SIZE E DIRECTION
n 84 BALL COUNT
φb 0.35 0.40 0.45 BALL DIAMETER
eE 0.80 BSC BALL PITCH
eD 0.80 BSC BALL PITCH
SD / SE 0.40 BSC SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
C
C
0.08
A1
b
84X
0.15 M C
MC
AB
0.08
6SIDE VIEW
7
SE
E1
CORNER
PIN A1
ACDB
D1
A
10
eD
9
8
6
5
3
eE
2
4
7
E
D
0.15 C
(2X)
GFE
KJH
SD
7
ML
1
C
C
0.15
B
(2X)
0.20
10
PIN A1
CORNER
INDEX MARK
A2
A
TOP VIEW
BOTTOM VIEW
8 S71PL-N MirrorBit® MCPs S71PL-N_00_A11 June 9, 2010
Data Sheet
Figure 5.3 TLA084 Physical Dimensions
3372-2 \ 16-038.22a
PACKAGE TLA 084
JEDEC N/A
D x E 11.60 mm x 8.00 mm
PACKAGE
SYMBOL MIN NOM MAX NOTE
A --- --- 1.20 PROFILE
A1 0.17 --- --- BALL HEIGHT
A2 0.81 --- 0.97 BODY THICKNESS
D 11.60 BSC. BODY SIZE
E 8.00 BSC. BODY SIZE
D1 8.80 BSC. MATRIX FOOTPRINT
E1 7.20 BSC. MATRIX FOOTPRINT
MD 12 MATRIX SIZE D DIRECTION
ME 10 MATRIX SIZE E DIRECTION
n 84 BALL COUNT
Ø b 0.35 0.40 0.45 BALL DIAMETER
eE 0.80 BSC. BALL PITCH
eD 0.80 BSC BALL PITCH
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS
B1,B10,C1,C10,D1,D10,
E1,E10,F1,F10,G1,G10,
H1,H10,J1,J10,K1,K10,L1,L10,
M2,M3,M4,M5,M6,M7,M8,M9
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
C
0.08
0.20 C
A
E
B
C
0.15
(2X)
C
D
C
0.15
(2X)
INDEX MARK
10
6
b
TOP VIEW
SIDE VIEW
CORNER
84X
A1
A2
A
0.15 C A BM
CM
0.08
PIN A1
ML
E1
7
SE
A
D1
eD
DCEFGHJ
K
10
8
9
7
6
4
3
2
1
eE
5
B
PIN A1
CORNER
7
SD
BOTTOM VIEW
June 9, 2010 S71PL-N_00_A11 S71PL-N MirrorBit® MCPs 9
Data Sheet
5.3 S71PL127N—TLA064
Figure 5.4 64-ball Fine-Pitch Ball Grid Array (S71PL127N)
Note:
Top view—balls facing down.
The addresses that are shared vary by MCP combination as shown in the table below:
Flash-only Addresses Shared Addresses
S71PL127NB0 A22-A21 A20:A0
S71PL127NC0 A22 A21:A0
A1 A10
B5 B6
C3 C4 C5 C6 C7 C8
D2 D3 D4 D5 D6 D7 D8 D9
E2 E3 E4 E5 E6 E7 E8 E9
F2 F3 F4 F7 F8 F9
G2 G3 G4 G7 G8 G9
H2 H3 H4 H5 H6 H7 H8 H9
J2 J3 J4 J5 J6 J7 J8 J9
K3 K4 K5 K6 K7 K8
L5 L6
M1 M10
DNU DNU
RFU RFU
A7 R-LB#
F-WP#/
ACC
WE# A8 A11
A3 A6 R-UB# F-RST R-CE2 A19 A12 A15
A2 A5 A18 F-RY/BY# A20 A9 A13 A21
A1 A4 A17 A10 A14 A22
A0 VSS DQ1 DQ6 RFU A16
F-CE# OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU
R-CE1# DQ0 DQ10 F-VCC R-VCC DQ12 DQ7 VSS
DQ8 DQ2 DQ11 RFU DQ5 DQ14
RFU RFU
DNU DNU
Shared
Flash Only
pSRAM Only
Do Not Use/
Reserved for Future Use
Legend
10 S71PL-N MirrorBit® MCPs S71PL-N_00_A11 June 9, 2010
Data Sheet
5.4 S71PL129N—TLA064
Figure 5.5 64-ball Fine-Pitch Ball Grid Array (S71PL129N)
Note:
Top view—balls facing down.
The addresses that are shared vary by MCP combination as shown in the table below:
Flash-only Addresses Shared Addresses
S71PL129NB0 A21 A20:A0
S71PL129NC0 — A21:A0
A1 A10
B5 B6
C3 C4 C5 C6 C7 C8
D2 D3 D4 D5 D6 D7 D8 D9
E2 E3 E4 E5 E6 E7 E8 E9
F2 F3 F4 F7 F8 F9
G2 G3 G4 G7 G8 G9
H2 H3 H4 H5 H6 H7 H8 H9
J2 J3 J4 J5 J6 J7 J8 J9
K3 K4 K5 K6 K7 K8
L5 L6
M1 M10
DNU DNU
RFU RFU
A7 R-LB#
F-WP#/
ACC
WE# A8 A11
A3 A6 R-UB# F-RST R-CE2 A19 A12 A15
A2 A5 A18 F-RY/BY# A20 A9 A13 A21
A1 A4 A17 A10 A14 F-CE2#
A0 VSS DQ1 DQ6 RFU A16
F-CE1# OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU
R-CE1# DQ0 DQ10 F-VCC R-VCC DQ12 DQ7 VSS
DQ8 DQ2 DQ11 RFU DQ5 DQ14
RFU RFU
DNU DNU
Shared
Flash Only
pSRAM Only
Do Not Use/
Reserved for Future Use
Legend
June 9, 2010 S71PL-N_00_A11 S71PL-N MirrorBit® MCPs 11
Data Sheet
Figure 5.6 TLA064 Physical Dimensions
3352 \ 16-038.22a
PACKAGE TLA 064
JEDEC N/A
D x E 11.60 mm x 8.00 mm
PACKAGE
SYMBOL MIN NOM MAX NOTE
A --- --- 1.20 PROFILE
A1 0.17 --- --- BALL HEIGHT
A2 0.81 --- 0.97 BODY THICKNESS
D 11.60 BSC. BODY SIZE
E 8.00 BSC. BODY SIZE
D1 8.80 BSC. MATRIX FOOTPRINT
E1 7.20 BSC. MATRIX FOOTPRINT
MD 12 MATRIX SIZE D DIRECTION
ME 10 MATRIX SIZE E DIRECTION
n 64 BALL COUNT
φb 0.35 0.40 0.45 BALL DIAMETER
eE 0.80 BSC. BALL PITCH
eD 0.80 BSC BALL PITCH
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS
B1,B2,B3,B4,B7,B8,B9,B10
C1,C2,C9,C10,D1,D10,E1,E10,
F1,F5,F6,F10,G1,G5,G6,G10
H1,H10,J1,J10,K1,K2,K9,K10
L1,L2,L3,L4,L7,L8,L9,L10
M2,M3,M4,M5,M6,M7,M8,M9
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
C
0.20
C
0.08
C
b
64X
6
0.08 M C
0.15 M C A B
A2
A
A1 SIDE VIEW
L
M
eD
CORNER
E1
7
SE
D1
ABDCEFHG
10
8
9
7
5
6
4
2
3
J
K
1
eE
SD
BOTTOM VIEW
PIN A1
7
10
INDEX MARK
C
0.15
(2X)
(2X)
C
0.15
B
A
D
E
PIN A1
TOP VIEW
CORNER
12 S71PL-N MirrorBit® MCPs S71PL-N_00_A11 June 9, 2010
Data Sheet
6. Revision History
Section Description
Revision A (March 11, 2005)
Initial release
Revision A1 (April 27, 2005)
Performance Characteristics pSRAM
Density table Added 128 Mb pSRAM device
Ordering Information and Valid
Combination tables Updated options to include 128 Mb pSRAM device
Block Diagram Changed chip enable pin from CE#f1 to F1-CE#
Physcial Dimensions/Connection
Diagrams
Replaced VBH084 with TLA084 and VSA084
Replaced VBU056 with TLC056
VCC Power Up Changed tVCS speed from 30 µs to 50 µs
DC Characteristics Changed ICC4 Max. to 50 µA
Revision A2 (August 18, 2005)
Global Removed all references to 56-ball package
Performance Characteristis Updated the product selector tables
Ordering Information Updated model number
Valid Combinations table Added new ordering options
Connection Diagram Updated the PL127N connection diagram
Updated the PL12xN connection diagram
Revision A3 (October 21, 2005)
Performance Characteristics Updated the Typical Sector Erase times
Revision A4 (November 29, 2005)
Global Added the 1.2 mm option to S71PL256ND0
Updated the S29PL-N Flash data sheet
Revision A5 (January 3, 2006)
Global
Changed the name of in F3 from A14 to A4 in pinout figure of section 3.2
Removed all references to Type 6 pSRAMs from the Product Selector Guide
Added a document reference table
Modified the Package Type and Material options
Removed the VSA084 package option
Removed the datasheet from the MCP wrapper
Revision A6 (April 12, 2006)
Global Added pSRAM Type 7 as an option to S71PL127NB0 and S71PL129NB0
Revision A7 (September 6, 2006)
Global Updated document to new template.
Revision A8 (October 6, 2006)
Global Added 32 Mb pSRAM Type 8 to the valid combinations
Revision A9 (December 8, 2006)
Global Added 64 Mb pSRAM Type 8 to the valid combinations.
Revision A10 (June 27, 2008)
Global Added OPN S71PL127NB0HHW4U
General Description Added 32M pSRAM Type 8 (90 nm)
Ordering Information Added Package Type & Material Set ordering option HH
Valid Combinations Added Note 4 for parts with pSRAM Type 2 or 7
June 9, 2010 S71PL-N_00_A11 S71PL-N MirrorBit® MCPs 13
Data Sheet
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2005-2010 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,
EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries.
Other names used are for informational purposes only and may be trademarks of their respective owners.
Revision A11 (June 9, 2010)
General Description
Corrected 32 Mb pSRAM Type 8 (90 nm) PID to comspec_02
Clarified that PID pSRAM_32 is for 64 Mb pSRAM Type 8 (130 nm)
Added PID SPH064D970R1R for 64 Mb pSRAM Type 8 (90 nm)
Product Selector Guide Clarified that pSRAM Type 8 may be of either 90 nm or 130 nm node for both 32 and 64 Mb
Valid Combinations Added Note 5 for MCPs with pSRAM Type 8 (90 nm)
Added Note 4 to all PL129N and PL256N MCP combinations
Section Description
