655 MHz Low Jitter Clock Generator AD9540 Data Sheet FEATURES APPLICATIONS Excellent intrinsic jitter performance 200 MHz phase frequency detector inputs 655 MHz programmable input dividers for the phase frequency detector (/M, /N) {M, N = 1 to 16} (bypassable) Programmable RF divider (/R) {R = 1, 2, 4, 8} (bypassable) 8 programmable phase/frequency profiles 400 MSPS internal DDS clock speed 48-bit frequency tuning word resolution 14-bit programmable phase offset 1.8 V supply for device operation 3.3 V supply for I/O, CML driver, and charge pump output Software controlled power-down 48-lead LFCSP package Programmable charge pump current (up to 4 mA) Dual-mode PLL lock detect 655 MHz CML-mode PECL-compliant output driver Clocking high performance data converters Base station clocking applications Network (SONET/SDH) clocking Gigabit Ethernet (GbE) clocking Instrumentation clocking circuits Agile LO frequency synthesis Automotive radar FM chirp source for radar and scanning systems Test and measurement equipment Acousto-optic device drivers FUNCTIONAL BLOCK DIAGRAM AVDD AGND DVDD DGND CP_VDD CP_RSET CP REF, AMP REFIN M DIVIDER PHASE FREQUENCY DETECTOR REFIN N DIVIDER SYNC_IN/STATUS CHARGE PUMP CP_OUT CLK2 SYNC, PLL LOCK CLK2 CLK1 DRV_RSET CML CLK1 DIVIDER 1, 2, 4, 8 OUT0 OUT0 SCLK SDO SERIAL CONTROL PORT AD9540 CS CLK TIMING AND CONTROL LOGIC S2 S1 S0 PHASE/ FREQUENCY PROFILES DIVCLK 48 14 DDS 10 IOUT DAC IOUT DAC_RSET 04947-001 SDI/O Figure 1. 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Technical Support www.analog.com AD9540 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 PLL Circuitry .............................................................................. 19 Applications ....................................................................................... 1 CML Driver ................................................................................. 19 Functional Block Diagram .............................................................. 1 DDS and DAC............................................................................. 20 Revision History ............................................................................... 2 Modes of Operation ....................................................................... 21 Product Overview............................................................................. 3 Selectable Clock Frequencies and Selectable Edge Delay ..... 21 Specifications..................................................................................... 4 Synchronization Modes for Multiple Devices .............................. 21 Loop Measurement Conditions .................................................. 8 Serial Port Operation ..................................................................... 22 Absolute Maximum Ratings ............................................................ 9 Instruction Byte .......................................................................... 23 ESD Caution .................................................................................. 9 Serial Interface Port Pin Description ....................................... 23 Pin Configuration and Function Descriptions ........................... 10 MSB/LSB Transfers .................................................................... 23 Typical Performance Characteristics ........................................... 12 Register Map and Description ...................................................... 24 Typical Application Circuits.......................................................... 17 Control Register Bit Descriptions ............................................ 27 Application Circuit Descriptions ............................................. 18 Outline Dimensions ....................................................................... 32 Theory of Operation ...................................................................... 19 Ordering Guide .......................................................................... 32 REVISION HISTORY 4/2018--Rev. B to Rev. C Changes to Figure 3 ........................................................................ 10 Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 32 9/2016--Rev. A to Rev. B Change to Features ........................................................................... 1 Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 32 2/2006--Rev. 0 to Rev. A Changes to Features Section ............................................................1 Changes to Applications Section .....................................................1 Changes to Functional Block Diagram...........................................1 Changes to Table 1.............................................................................4 Changes to Typical Application Circuits Section ....................... 17 Updates to Ordering Guide ........................................................... 32 7/2004--Revision 0: Initial Version Rev. C | Page 2 of 32 Data Sheet AD9540 PRODUCT OVERVIEW The AD9540 is Analog Devices' first dedicated clocking product specifically designed to support the extremely stringent clocking requirements of the highest performance data converters. The device features high performance PLL (phaselocked loop) circuitry, including a flexible 200 MHz phase frequency detector and a digitally controlled charge pump current. The device also provides a low jitter, 655 MHz CMLmode, PECL-compliant output driver with programmable slew rates. External VCO rates up to 2.7 GHz are supported. Extremely fine tuning resolution (steps less than 2.33 Hz) is another feature supported by this device. Information is loaded into the AD9540 via a serial I/O port that has a device write speed of 25 Mbps. The AD9540 frequency divider block can also be programmed to support a spread spectrum mode of operation. The AD9540 is specified to operate over the extended automotive range of -40C to +85C. Rev. C | Page 3 of 32 AD9540 Data Sheet SPECIFICATIONS AVDD = DVDD = 1.8 V 5%; DVDD_I/O = CP_VDD = 3.3 V 5% (@ TA = 25C), DAC_RSET = 3.92 k, CP_RSET = 3.09 k, DRV_RSET = 4.02 k, unless otherwise noted. Table 1. Parameter TOTAL SYSTEM JITTER AND PHASE NOISE FOR 105 MHz ADC CLOCK GENERATION CIRCUIT Converter Limiting Jitter1 Resultant Signal-to-Noise Ratio (SNR) Phase Noise of Fundamental @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset 1 MHz Offset TOTAL SYSTEM PHASE NOISE FOR 210 MHz ADC CLOCK GENERATION CIRCUIT Phase Noise of Fundamental @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset TOTAL SYSTEM TIME JITTER FOR CLOCKS 155.52 MHz Clock 622.08 MHz Clock RF DIVIDER/CML DRIVER EQUIVALENT INTRINSIC TIME JITTER FIN = 414.72 MHz, FOUT = 51.84 MHz FIN = 1244.16 MHz, FOUT = 155.52 MHz FIN = 2488.32 MHz, FOUT = 622.08 MHz RF DIVIDER/CML DRIVER RESIDUAL PHASE NOISE FIN = 81.92 MHz, FOUT = 10.24 MHz @ 10 Hz @ 100 Hz @ 1 kHz @ 10 kHz @ 100 kHz 1 MHz FIN = 983.04 MHz, FOUT = 122.88 MHz @ 10 Hz @ 100 Hz @ 1 KHz @ 10 kHz @ 100 kHz @ 1 MHz >3 MHz Min Typ Max Unit Test Conditions/Comments 720 59.07 fS rms dB 80 92 101 110 147 153 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 79.2 86 95 105 144 151 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 581 188 fS rms fS rms 12 kHz to 1.3 MHz bandwidth 12 kHz to 5 MHz bandwidth 136 101 108 fS rms fS rms fS rms R = 8, BW = 12 kHz to 400 kHz R = 8, BW = 12 kHz to 1.3 MHz R = 4, BW = 12 kHz to 5 MHz 120 128 137 145 150 153 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 115 125 132 142 146 151 153 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz RF Divider R = 8 RF Divider R = 8 Rev. C | Page 4 of 32 Data Sheet Parameter FIN = 1966.08 MHz, FOUT = 491.52 MHz @ 10 Hz @ 100 Hz @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz >3 MHz FIN = 2488 MHz, FOUT = 622 MHz @ 10 Hz @ 100 Hz @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz 3 MHz PHASE FREQUENCY DETECTOR/CHARGE PUMP REFIN Input Input Frequency2 /M Set to Divide by at Least 4 /M Bypassed Input Voltage Levels Input Capacitance Input Resistance CLK2 Input Input Frequency /N Set to Divide by at Least 4 /N Bypassed Input Voltage Levels Input Capacitance Input Resistance Charge Pump Source/Sink Maximum Current Charge Pump Source/Sink Accuracy Charge Pump Source/Sink Matching Charge Pump Output Compliance Range3 STATUS Drive Strength PHASE FREQUENCY DETECTOR NOISE FLOOR @ 50 kHz PFD Frequency @ 2 MHz PFD Frequency @ 100 MHz PFD Frequency @ 200 MHz PFD Frequency RF DIVIDER (CLK1 ) INPUT SECTION (/R) RF Divider Input Range Input Capacitance (DC) Input Impedance (DC) Input Duty Cycle Input Power/Sensitivity Input Voltage Level AD9540 Min Typ Max Unit 105 112 122 130 141 144 146 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 100 108 115 125 135 140 142 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Test Conditions/Comments RF Divider R = 4 RF Divider R = 4 200 655 200 600 10 MHz MHz mV p-p pF 655 200 600 10 2 MHz MHz mV p-p pF mA % % V mA 148 133 116 113 dBc/Hz dBc/Hz dBc/Hz dBc/Hz 450 1500 200 450 1500 4 5 2 CP_VDD - 0.5 0.5 1 42 -10 200 3 1500 50 2700 MHz 58 +4 1000 pF % dBm mV p-p Rev. C | Page 5 of 32 DDS SYSCLK not to exceed 400 MSPS Single-ended, into a 50 load4 AD9540 Parameter CML OUTPUT DRIVER (OUT0) Differential Output Voltage Swing5 Maximum Toggle Rate Common-Mode Output Voltage Output Duty Cycle Output Current Continuous6 Rising Edge Surge Falling Edge Surge Output Rise Time Output Fall Time LOGIC INPUTS (SDI/O, I/O_RESET, RESET, I/O_UPDATE, S0, S1, S2, SYNC_IN) VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Maximum Input Capacitance LOGIC OUTPUTS (SDO, SYNC_OUT, STATUS)7 VOH, Output High Voltage VOH, Output Low Voltage IOH IOL POWER CONSUMPTION Total Power Consumed, All Functions On I(AVDD) I(DVDD) I(DVDD_I/O) I(CP_VDD) Power-Down Mode WAKE-UP TIME (FROM POWER-DOWN MODE) Digital Power-Down DAC Power-Down RF Divider Power-Down Clock Driver Power-Down Charge Pump Full Power-Down Charge Pump Quick Power-Down CRYSTAL OSCILLATOR (ON REFIN INPUT) Operating Range Residual Phase Noise (@ 25 MHz) @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset DIGITAL TIMING SPECIFICATIONS CS to SCLK Setup Time, TPRE Period of SCLK (Write), TSCLKW Period of SCLK (Read), TSCLKR Serial Data Setup Time, TDSU Serial Data Hold Time, TDHD Data Valid Time, TDV Data Sheet Min Typ Max 720 Unit Test Conditions/Comments mV 50 load to supply, both lines 655 1.75 42 58 7.2 20.9 13.5 250 250 mA mA mA ps ps 2.0 1 3 0.8 5 2.7 0.4 100 100 400 85 45 20 15 20 V % V V A pF V V A A 80 mW mA mA mA mA mW 12 7 400 6 10 150 ns s ns s s ns 25 30 95 120 140 157 164 168 6 40 400 6.5 0 40 MHz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ns ns ns ns ns ns Rev. C | Page 6 of 32 100 terminated, 5 pF load 100 terminated, 5 pF load Control Function Register 1[7] Control Function Register 3[39] Control Function Register 2[23] Control Function Register 2[20] Control Function Register 2[4] Control Function Register 2[3] Data Sheet Parameter I/O_Update to SYNC_OUT Setup Time PS[2:0> to SYNC_OUT Setup Time Latencies/Pipeline Delays I/O_Update to DAC Frequency Change I/O_Update to DAC Phase Change PS[2:0] to DAC Frequency Change PS[2:0] to DAC Phase Change I/O_Update to CP_OUT Scaler Change I/O_Update to Frequency Accumulator Step Size Change DAC OUTPUT CHARACTERISTICS Resolution Full-Scale Output Current Gain Error Output Offset Output Capacitance Voltage Compliance Range Wideband SFDR (DC to Nyquist) 10 MHz Analog Out 40 MHz Analog Out 80 MHz Analog Out 120 MHz Analog Out 160 MHz Analog Out Narrow-Band SFDR 10 MHz Analog Out (1 MHz) 10 MHz Analog Out (250 kHz) 10 MHz Analog Out (50 kHz) 40 MHz Analog Out (1 MHz) 40 MHz Analog Out (250 kHz) 40 MHz Analog Out (50 kHz) 80 MHz Analog Out (1 MHz) 80 MHz Analog Out (250 kHz) 80 MHz Analog Out (50 kHz) 120 MHz Analog Out (1 MHz) 120 MHz Analog Out (250 kHz) 120 MHz Analog Out (50 kHz) 160 MHz Analog Out (1 MHz) 160 MHz Analog Out (250 kHz) 160 MHz Analog Out (50 kHz) DAC RESIDUAL PHASE NOISE 19.7 MHz FOUT @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset AD9540 Min 7 7 Typ Max 33 33 29 29 4 4 Unit ns ns SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles 10 10 -10 15 +10 0.6 5 AVDD - 0.50 Bits mA % fS A pF AVDD + 0.50 65 62 57 56 54 dBc dBc dBc dBc dBc 83 85 86 82 84 87 80 82 86 80 82 84 80 82 84 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 122 134 143 150 158 160 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. C | Page 7 of 32 Test Conditions/Comments AD9540 Parameter 51.84 MHz FOUT @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset > 1 MHz Offset 105 MHz Analog Out @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset 155.52 MHz Analog Out @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset Data Sheet Min Typ Max Unit Test Conditions/Comments 110 121 135 142 148 153 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 105 115 126 132 140 145 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 100 112 123 131 138 144 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz The SNR of a 14-bit ADC was measured with an ENCODE rate of 105 MSPS and an AIN of 170 MHz. The resultant SNR was known to be limited by the jitter of the clock, not by the noise on the AIN signal. From this SNR value, the jitter affecting the measurement can be back calculated. 2 Driving the REFIN input buffer. The crystal oscillator section of this input stage performs up to only 30 MHz. 3 The charge pump output compliance range is functionally 0.2 V to (CP_VDD - 0.2 V). The value listed here is the compliance range for 5% matching. 4 The input impedance of the CLK1 input is 1500 . However, to provide matching on the clock line, an external 50 load is used. 5 Measured as peak-to-peak between DAC outputs. 6 For a 4.02 k resistor from DRV_RSET to GND. 7 Assumes a 1 mA load. 1 LOOP MEASUREMENT CONDITIONS 622 MHz OC-12 Clock 105 MHz Converter Clock VCO = Sirenza 190-640T VCO = Sirenza 190-845T Reference = Wenzel 500-10116 (30.3 MHz) Reference = Wenzel 500-10116 (30.3 MHz) Loop Filter = 10 kHz BW, 60 Phase Margin Loop Filter = 10 kHz BW, 45 Phase Margin C1 = 170 nF, R1 = 14.4 , C2 = 5.11 F, R2 = 89.3 , C3 Omitted C1 = 117 nF, R1 = 28 , C2 = 1.6 F, R2 = 57.1 , C3 = 53.4 nF /R = 8, /M = 1, /N = 1 /R = 2, /M = 1, /N = 1 R2 INPUT OUTPUT R1 C1 C3 C2 Figure 2. Generic Loop Filter Rev. C | Page 8 of 32 04947-041 CP_OUT = 4 mA (Scaler = x8) CP_OUT = 4 mA (Scaler = x8) Data Sheet AD9540 ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 2. Parameter Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD_I/O) Charge Pump Supply Voltage (CP_VDD) Maximum Digital Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Thermal Resistance (JA) Rating 2V 2V 3.6 V 3.6 V -0.5 V to DVDD_I/O + 0.5 V -65C to +150C -40C to +125C 300C ESD CAUTION 150C 26C/W Rev. C | Page 9 of 32 AD9540 Data Sheet AGND 1 AVDD 2 AGND 3 AVDD 4 IOUT 5 IOUT 6 AVDD 7 AGND 8 I/O_RESET 9 RESET 10 DVDD 11 DGND 12 CP_RSET AVDD AGND CLK2 CLK2 REFIN REFIN AVDD AGND 45 44 43 42 41 40 39 38 37 48 AVDD 47 DAC_RSET 46 DRV_RSET PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9540 18 19 20 21 22 23 24 CP_OUT CP_VDD AGND OUT0 OUT0 CP_VDD AGND CLK1 CLK1 AVDD AGND DVDD NOTES 1. THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION AS WELL AS A THERMAL ENHANCEMENT. IN ORDER FOR THE DEVICE TO FUNCTION PROPERLY, THE PADDLE MUST BE ATTACHED TO ANALOG GROUND. 04947-047 SDO SDI/O SCLK CS DVDD_I/O SYNC_OUT SYNC_IN/STATUS I/O_UPDATE S0 S1 S2 DGND 13 14 15 16 17 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 Figure 3. 48-Lead LFCSP Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 3, 8, 26, 30, 34, 37, 43, 2, 4, 7, 27, 38, 44, 48 5 6 9 Mnemonic AGND Description Analog Ground. AVDD Analog Core Supply (1.8 V). IOUT IOUT I/O_RESET DAC Analog Output. DAC Analog Complementary Output. Resets the serial port when synchronization is lost in communications but does not reset the device itself (active high). When not being used, this pin should be forced low, because it floats to the threshold value. Master Reset. Clears all accumulators and returns all registers to their default values (active high). Digital Core Supply (1.8 V). Digital Ground. Serial Data Output. Used only when the device is programmed for 3-wire serial data mode. Serial Data Input/Output. When the part is programmed for 3-wire serial data mode, this is input only; in 2-wire mode, it serves as both the input and output. Serial Data Clock. Provides the clock signal for the serial data port. Active Low Signal That Enables Shared Serial Buses. When brought high, the serial port ignores the serial data clocks. Digital Interface Supply (3.3 V). Synchronization Clock Output. Bidirectional Dual Function Pin. Depending on device programming, this pin is either the direct digital synthesizer's (DDS) synchronization input (allows alignment of multiple subclocks), or the PLL lock detect output signal. This input pin, when set high, transfers the data from the I/O buffers to the internal registers on the rising edge of the internal SYNC_CLK, which can be observed on SYNC_OUT. 10 11, 25 12, 24 13 14 RESET DVDD DGND SDO SDI/O 15 16 SCLK CS 17 18 19 DVDD_I/O SYNC_OUT SYNC_IN/STATUS 20 I/O_UPDATE Rev. C | Page 10 of 32 Data Sheet AD9540 Pin No. 21, 22, 23 Mnemonic S0, S1, S2 28 29 31, 35 32 33 36 39 40 41 42 45 46 47 Paddle CLK1 CLK1 CP_VDD OUT0 OUT0 CP_OUT REFIN REFIN CLK2 CLK2 CP_RSET DRV_RSET DAC_RSET Exposed Paddle Description Clock Frequency and Delay Select Pins. These pins specify one of eight clock frequency/delay profiles. RF Divider and Internal Clock Complementary Input. RF Divider and Internal Clock Input. Charge Pump and CML Driver Supply Pin. 3.3 V analog (clean) supply. CML Driver Complementary Output. CML Driver Output. Charge Pump Output. Phase Frequency Detector Reference Input. Phase Frequency Detector Reference Complementary Input. Phase Frequency Detector Oscillator (Feedback) Complementary Input. Phase Frequency Detector Oscillator (Feedback) Input. Charge Pump Current Set. Program charge pump current with a resistor to AGND. CML Driver Output Current Set. Program CML output current with a resistor to AGND. DAC Output Current Set. Program DAC output current with a resistor to AGND. The exposed paddle on this package is an electrical connection as well as a thermal enhancement. In order for the device to function properly, the paddle must be attached to analog ground. Rev. C | Page 11 of 32 AD9540 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS REF LVL 0dBm DELTA 1 [T1] -85.94dB -2.10420842kHz 0 RBW 100Hz VBW 100Hz SWT 25s DELTA 1 [T1] -84.94dB 2.10420842kHz RF ATT 20dB UNIT REF LVL 0dBm dB 0 1 -10 -20 -20 RF ATT 20dB UNIT dB 1 A -10 RBW 100Hz VBW 100Hz SWT 25s A -30 -30 1 AP 1 AP -40 -40 -50 -50 -60 -60 -70 -70 -80 1 -90 -100 CENTER 10.1MHz 5kHz/ -100 SPAN 50kHz CENTER 40.1MHz Figure 4. DAC Performance: 400 MSPS Clock, 10 MHz FOUT, 50 kHz Span REF LVL 0dBm DELTA 1 [T1] -86.03dB -368.73747495kHz 0 RBW 500Hz VBW 500Hz SWT 20s 1 -90 5kHz/ SPAN 50kHz Figure 7. DAC Performance: 400 MSPS Clock, 40 MHz FOUT, 50 kHz Span RF ATT 20dB UNIT 04947-006 04947-003 -80 REF LVL 0dBm dB 0 1 -10 -20 -20 -30 RF ATT 20dB UNIT dB 1 A -10 RBW 500Hz VBW 500Hz 20s SWT DELTA 1 [T1] -80.17dB -200.40080160kHz A -30 1 AP 1 AP -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 -90 -100 CENTER 10.1MHz 100kHz/ -90 -100 CENTER 40.1MHz SPAN 1MHz Figure 5. DAC Performance: 400 MSPS Clock, 10 MHz FOUT, 1 MHz Span REF LVL 0dBm 0 DELTA 1 [T1] -64.54dB 100.20040080MHz RBW 10kHz VBW 10kHz SWT 5s 04947-007 04947-004 1 1 Figure 8. DAC Performance: 400 MSPS Clock, 40 MHz FOUT, 1 MHz Span RF ATT 20dB UNIT SPAN 1MHz 100kHz/ REF LVL 0dBm dB 0 1 A -10 DELTA 1 [T1] -61.61dB 100.20040080MHz RBW 10kHz VBW 10kHz 5s SWT RF ATT 20dB UNIT dB 1 A -10 -20 -20 -30 -30 1 AP 1 AP -40 -40 -50 -50 -60 -60 1 1 -70 -70 -80 -100 START 0Hz 20MHz/ 04947-008 04947-005 -80 -90 -90 -100 STOP 200MHz START 0Hz Figure 6. DAC Performance: 400 MSPS Clock, 10 MHz FOUT, 200 MHz Span 20MHz/ STOP 200MHz Figure 9. DAC Performance: 400 MSPS Clock, 40 MHz FOUT, 200 MHz Span (Nyquist) Rev. C | Page 12 of 32 Data Sheet REF LVL 0dBm AD9540 DELTA 1 [T1] -83.72dB -2.70541082kHz 0 RBW 100Hz VBW 100Hz SWT 25s RF ATT 20dB UNIT REF LVL 0dBm dB DELTA 1 [T1] -85.98dB -2.90581162kHz RBW 100Hz VBW 100Hz SWT 25s RF ATT 20dB UNIT dB 0 1 1 A -10 -10 -20 -20 A -30 -30 1 AP 1 AP -40 -40 -50 -50 -60 -60 -70 -70 -90 04947-009 1 -100 CENTER 100.1MHz 5kHz/ -90 DELTA 1 [T1] -56.47dB -400.80160321kHz 0 RBW 500Hz VBW 500Hz SWT 20s 1 -100 SPAN 50kHz CENTER 159.5MHz Figure 10. DAC Performance: 400 MSPS Clock, 100 MHz FOUT, 50 kHz Span REF LVL 0dBm 5kHz/ SPAN 50kHz Figure 13. DAC Performance: 400 MSPS Clock, 160 MHz FOUT, 50 kHz Span RF ATT 20dB UNIT 04947-012 -80 -80 REF LVL 0dBm dB RBW 500Hz VBW 500Hz 20s SWT DELTA 1 [T1] -82.83dB 262.52505010kHz RF ATT 20dB UNIT dB 0 1 A -10 -10 -20 -20 -30 A 1 -30 1 AP 1 AP -40 -40 -50 -50 -60 1 -70 -80 -80 04947-010 -70 -90 -100 CENTER 100.1MHz 100kHz/ 0 DELTA 1 [T1] -48.71dB -400.80160321kHz RBW 10kHz VBW 10kHz SWT 5s 1 -90 -100 SPAN 1kHz SPAN 1MHz Figure 14. DAC Performance: 400 MSPS Clock, 160 MHz FOUT, 1 MHz Span RF ATT 20dB UNIT 100kHz/ CENTER 159.5MHz Figure 11. DAC Performance: 400 MSPS Clock, 100 MHz FOUT, 1 MHz Span REF LVL 0dBm 04947-013 -60 REF LVL 0dBm dB DELTA 1 [T1] -54.90dB -78.55711423MHz RBW 10kHz VBW 10kHz 5s SWT RF ATT 20dB UNIT dB 0 1 1 A -10 -10 -20 -20 -30 A -30 1 AP -40 1 AP -40 -50 -50 1 -60 -60 -80 -90 -100 START 0Hz 20MHz/ 04947-014 -70 -80 04947-011 -70 1 -90 -100 START 0Hz STOP 200MHz Figure 12. DAC Performance: 400 MSPS Clock, 100 MHz FOUT, 200 MHz Span 20MHz/ STOP 200MHz Figure 15. DAC Performance: 400 MSPS Clock, 160 MHz FOUT, 200 MHz Span Rev. C | Page 13 of 32 100k 1M L(f) (dBc/Hz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 L(f) (dBc/Hz) 100 1k 10k 100k FREQUENCY (Hz) 1M 10k 100k FREQUENCY (Hz) 1M 10M 100 1k 10k FREQUENCY (Hz) 100k 1M 2M Figure 20. RF Divider and CML Driver Residual Phase Noise (81.92 MHz In, 10.24 MHz Out) 04947-025 L(f) (dBc/Hz) Figure 17. DDS/DAC Residual Phase Noise 400 MHz Clock, 51.84 MHz Output 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 1k Figure 19. DDS/DAC Residual Phase Noise 400 MHz Clock, 155.52 MHz Output 04947-024 L(f) (dBc/Hz) Figure 16. DDS/DAC Residual Phase Noise 400 MHz Clock, 19.7 MHz Output 100 04947-0-027 1k 10k FREQUENCY (Hz) 10M Figure 18. DDS/DAC Residual Phase Noise 400 MHz Clock, 105.3 MHz Output 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 04947-0-028 100 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 04947-026 L(f) (dBc/Hz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 Data Sheet 04947-023 L(f) (dBc/Hz) AD9540 100 10k 1k FREQUENCY (Hz) 100k Figure 21. RF Divider and CML Driver Residual Phase Noise (157.6 MHz In, 19.7 MHz Out) Rev. C | Page 14 of 32 1M 2M 10k 100k FREQUENCY (Hz) 1M 10M L(f) (dBc/Hz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 L(f) (dBc/Hz) 100 1k 10k 100k FREQUENCY (Hz) 1M 10k 100k FREQUENCY (Hz) 1M 10M 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 26. RF Divider and CML Driver Residual Phase Noise (1680 MHz In, 210 MHz Out) 04947-031 L(f) (dBc/Hz) Figure 23. RF Divider and CML Driver Residual Phase Noise (842.4 MHz In, 105.3 MHz Out) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 1k Figure 25. RF Divider and CML Driver Residual Phase Noise (1240 MHz In, 155 MHz Out) 04947-030 L(f) (dBc/Hz) Figure 22. RF Divider and CML Driver Residual Phase Noise (410.4 MHz In, 51.3 MHz Out) 100 04947-033 1k 10M Figure 24. RF Divider and CML Driver Residual Phase Noise (983.04 MHz In, 122.88 MHz Out) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 04947-034 100 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 04947-032 L(f) (dBc/Hz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 AD9540 04947-029 L(f) (dBc/Hz) Data Sheet 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 27. RF Divider and CML Driver Residual Phase Noise (1966.08 MHz In, 491.52 MHz Out) Rev. C | Page 15 of 32 10M 1k 10k 100k FREQUENCY (Hz) 1M 10M L(f) (dBc/Hz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 10 100 1k 10k 100k FREQUENCY (Hz) 1M 1k 10k 100k FREQUENCY (Hz) 1M 20M Figure 30. Total System Phase Noise for 210 MHz Converter Clock 04947-0-036 L(f) (dBc/Hz) Figure 28. RF Divider and CML Driver Residual Phase Noise (2488 MHz In, 622 MHz Out) 100 20M Figure 29. Total System Phase Noise for 105 MHz Converter Clock Rev. C | Page 16 of 32 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 10 04947-0-038 100 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 10 04947-0-037 L(f) (dBc/Hz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 Data Sheet 04947-035 L(f) (dBc/Hz) AD9540 100 1k 10k 100k FREQUENCY (Hz) 1M 20M Figure 31. Total System Phase Noise for 622 MHz OC-12 Clock Data Sheet AD9540 TYPICAL APPLICATION CIRCUITS 25MHz CRYSTAL PHASE FREQUENCY DETECTOR/CHARGE PUMP M REFIN 400MHz CP_OUT N VCO LPF CLK2 CML DRIVER R DAC DDS CLOCK1 LPF ADCMP563 Figure 32. Dual Clock Configuration PHASE FREQUENCY DETECTOR 622MHz CHARGE PUMP CLK2 VCO LPF CML DRIVER R CLOCK1 AD9540 DAC DDS CLOCK2 ADCMP563 Figure 33. Optical Networking Clock REFIN CP_OUT VCO LPF CLK2 DAC DDS R LPF AD9540 Figure 34. Fractional-Divider Loop DAC DDS PHASE FREQUENCY DETECTOR REFIN LPF CLK2 CHARGE PUMP VCO LPF N AD9540 Figure 35. Direct Upconversion of DDS Output Spectrum Rev. C | Page 17 of 32 04947-043 N REFIN 04947-045 M 04947-044 EXTERNAL REFERENCE 04947-042 AD9540 CLOCK1 AD9540 Data Sheet DDS CML DRIVER 8-LEVEL FSK (FC = 100MHz) DAC BPF /R AD9540 BPF REFIN 25MHz CRYSTAL CP_OUT CLK2 2.5GHz TONE LPF 04947-046 /N VCO Figure 36. ISM Band Modulator (LO & Baseband Generation) APPLICATION CIRCUIT DESCRIPTIONS Dual Clock Configuration In this loop, M = 1, N = 16, and R = 4. The DDS (direct digital synthesizer) tuning word is also equal to 1/4, so that the frequency of CLOCK1' equals the frequency of CLOCK 1. Phase adjustments in the DDS provide 14-bit programmable rising edge delay capability of CLOCK1' with respect to CLOCK1 (see Figure 32). Optical Networking Clock This is the AD9540 configured as an optical networking clock. The loop can be used to generate a 622 MHz clock for OC12. The DDS can be programmed to output 8 kHz to serve as a base reference for other circuits in the subsystem (see Figure 33). Direct Upconversion The AD9540 is configured to use the DDS as a precision reference to the PLL. Since the VCO is <655 MHz, it can be fed straight into the phase frequency detector feedback. LO and Baseband Modulation Generation Using the AD9540 PLL section to generate LO and the DDS portion to generate a modulated baseband, this circuit uses an external mixer to perform some simple modulation at RF ISM band frequencies (see Figure 36). Fractional-Divider Loop This loop offers the precise frequency division (48-bit) of the DDS in the feedback path as well as the frequency sweeping capability of the DDS. Programming the DDS to sweep from 24 MHz to 25 MHz sweeps the output of the VCO from 2.7 GHz to 2.6 GHz. The reference in this case is a simple crystal (see Figure 34). Rev. C | Page 18 of 32 Data Sheet AD9540 THEORY OF OPERATION PLL CIRCUITRY CML DRIVER The AD9540 includes an RF divider (divide-by-R), a 48-bit DDS core, a 14-bit programmable delay adjustment, a 10-bit DAC (digital-to-analog converter), a phase frequency detector, and a programmable output current charge pump. Incorporating these blocks together, users can generate many useful circuits for clock synthesis. A few simple examples are shown in the Typical Performance Characteristics section. An on-chip current mode logic (CML) driver is also included. This CML driver generates very low jitter clock edges. The outputs of the CML driver are current outputs that drive PECL levels when terminated into a 100 load. The continuous output current of the driver is programmed by attaching a resistor from the DRV_RSET pin to ground (nominally 4.02 k for a continuous current of 7.2 mA). An optional on-chip current programming resistor is enabled by setting a bit in the control register. The rising edge and falling edge slew rates are independently programmable to help control overshoot and ringing by the application of surge current during rising edge and falling edge transitions (see Figure 37). There is a default surge current of 7.6 mA on the rising edge and of 4.05 mA on the falling edge. Bits in the control register enable additional rising edge and falling edge surge current, as well as disable the default surge current (see the Control Register Bit Descriptions section for details). The CML driver can be driven by: The on-chip phase frequency detector has two differential inputs, REFIN (the reference input) and CLK2 (the feedback or oscillator input). These differential inputs can be driven by single-ended signals. When doing so, tie the unused input through a 100 pF capacitor to the analog supply (AVDD). The maximum speed of the phase frequency detector inputs is 200 MHz. Each of the inputs has a buffer and a divider (/M on REFIN and /N on CLK2) that operates up to 655 MHz. If the signal exceeds 200 MHz, the divider must be used. The dividers are programmed through the control registers and take any integer value between 1 and 16. * * * RF divider input (CLK1 directly to the CML driver) RF divider output CLK2 input RISING EDGE SURGE I(t) CONTINUOUS CONTINUOUS The REFIN input also has the option of engaging an in-line oscillator circuit. Engaging this circuit means that the REFIN input can be driven with a crystal in the range of 20 MHz REFIN 30 MHz. The charge pump outputs a current in response to an error signal generated in the phase frequency detector. The output current is programmed through by placing a resistor (CP_RSET) from the CP_RSET pin to ground. The value is dictated by CP_IOUT = FALLING EDGE SURGE ~250ps ~250ps t Figure 37. Rising Edge and Falling Edge Surge Current Out of the CML Clock Driver, as Opposed to the Steady State Continuous Current 1.55 CP_RSET This sets the charge pump reference output current. Also, a programmable scaler multiplies this base value by any integer from 1 to 8, programmable through the CP current scale bits in the Control Function Register 2, CFR2[2:0]. Rev. C | Page 19 of 32 04947-017 The RF divider accepts differential or single-ended signals up to 2.7 GHz on the CLK1 input pin. The RF divider also supplies the SYSCLK input to the DDS. Because the DDS operates only up to 400 MSPS, device function requires that for any CLK1 signal >400 MHz, the RF divider must be engaged. The RF divider can be programmed to take values of 1, 2, 4, or 8. The ratio for the divider is programmed in the control register. The output of the divider can be routed to the input of the on-chip CML driver. For lower frequency input signals, it is possible to use the divider to divide the input signal to the CML driver and to use the undivided input of the divider as the SYSCLK input to the DDS, or vice versa. In all cases, the SYSCLK to the DDS should not exceed 400 MSPS. AD9540 Data Sheet DDS AND DAC The precision frequency division within the device is accomplished using DDS technology. The DDS can control the digital phase relationships by clocking a 48-bit accumulator. The incremental value loaded into the accumulator, known as the frequency tuning word, controls the overflow rate of the accumulator. Similar to a sine wave completing a 2 radian revolution, the overflow of the accumulator is cyclical in nature and generates a fundamental frequency according to fo = FTW x ( f s ) 2 48 {0 FTW 2 47 } The instantaneous phase of the sine wave is therefore the output of the phase accumulator block. This signal can be phase-offset by programming an additive digital phase that is added to each phase sample coming out of the accumulator. Finally, the amplitude words are piped to a 10-bit DAC. Because the DAC is a sampled data system, the output is a reconstructed sine wave that needs to be filtered to take high frequency images out of the spectrum. The DAC is a current steering DAC that is AVDD referenced. To get a measurable voltage output, the DAC outputs must be terminated through a load resistor to AVDD, typically 50 . At positive full scale, IOUT sinks no current and the voltage drop across the load resistor is 0. However, the IOUT output sinks the programmed full-scale output current of the DAC, causing the maximum output voltage drop across the load resistor. At negative full-scale, the situation is reversed and IOUT sinks the full-scale current (and generates the maximum drop across the load resistor), while IOUT sinks no current (and generates no voltage drop). At midscale, the outputs sink equal amounts of current, generating equal voltage drops. These instantaneous phase values are then piped through a phase-to-amplitude conversion (sometimes called an angle-toamplitude conversion or AAC) block. This algorithm follows a COS(x) relationship, where x is the phase coming out of the phase offset block, normalized to 2. Rev. C | Page 20 of 32 Data Sheet AD9540 MODES OF OPERATION Automatic Synchronization SELECTABLE CLOCK FREQUENCIES AND SELECTABLE EDGE DELAY Because the precision driver is implemented using a DDS, it is possible to store multiple clock frequency words to enable externally switchable clock frequencies. The phase accumulator runs at a fixed frequency, according to the active profile clock frequency word. Likewise, any delay applied to the rising and falling edges is a static value that comes from the delay shift word of the active profile. The device has eight different phase/frequency profiles, each with its own 48-bit clock frequency word and 14-bit delay shift word. Profiles are selected by applying their digital values on the clock select pins (Pin S0, Pin S1, and Pin S2). It is not possible to use the phase offset of one profile and the frequency tuning word of another. SYNCHRONIZATION MODES FOR MULTIPLE DEVICES In a DDS system, the SYNC_CLK is derived internally from the master system clock, SYSCLK, with a /4 divider. Because the divider does not power up to a known state, multiple devices in a system might have staggered clock phase relationships, because each device can potentially generate the SYNC_CLK rising edge from any one of four rising edges of SYSCLK. This ambiguity can be resolved by employing digital synchronization logic to control the phase relationships of the derived clocks among different devices in the system. Note that the synchronization functions included on the AD9540 control only the timing relationships among different digital clocks. They do not compensate for the analog timing delay on the system clock due to mismatched phase relationships on the input clock, CLK1 (see Figure 38). SYNCHRONIZATION FUNCTIONS CAN ALIGN DIGITAL CLOCK RELATIONSHIPS, THEY CANNOT DESKEW THE EDGES OF CLOCKS SYSCLK DUT1 0 2 1 3 0 SYNC_CLK DUT1 SYSCLK DUT2 3 0 1 2 In automatic synchronization mode, the device is placed in slave mode and automatically aligns the internal SYNC_CLK to a master SYNC_CLK signal, supplied on the SYNC_IN input. When this bit is enabled, the STATUS is not available as an output; however, an out-of-lock condition can be detected by reading Control Function Register 1 and checking the status of the STATUS_Error bit. The automatic synchronization function is enabled by setting the Control Function Register 1, Automatic Synchronization Bit CFR1[3]. To employ this function at higher clock rates (SYNC_CLK > 62.5 MHz, SYSCLK > 250 MHz), the high speed sync enable bit (CFR1[0]) should be set as well. Manual Synchronization, Hardware Controlled In this mode, the user controls the timing relationship of the SYNC_CLK with respect to SYSCLK. When hardware manual synchronization is enabled, the SYNC_IN/STATUS pin becomes a digital input. For each rising edge detected on the SYNC_IN input, the device advances the SYNC_IN rising edge by one SYSCLK period. When this bit is enabled, the STATUS is not available as an output; however, an out-of-lock condition can be detected by reading Control Function Register 1 and checking the status of the STATUS_Error bit. This synchronization function is enabled by setting the Hardware Manual Synchronization Enable Bit CFR1[1]. Manual Synchronization, Software Controlled In this mode, the user controls the timing relationship between SYNC_CLK and SYSCLK through software programming. When the software manual synchronization bit (CFR1[2]) is set high, the SYNC_CLK is advanced by one SYSCLK cycle. Once this operation is complete, the bit is cleared. The user can set this bit repeatedly to advance the SYNC_CLK rising edge multiple times. Because the operation does not use the SYNC_IN/STATUS pin as a SYNC_IN input, the STATUS signal can be monitored on the STATUS pin during this operation. 3 SYNC_CLK DUT2 w/ SYNC_CLK ALIGNED 04947-018 SYNC_CLK DUT2 w/o SYNC_CLK ALIGNED Figure 38. Synchronization Functions: Capabilities and Limitations Rev. C | Page 21 of 32 AD9540 Data Sheet SERIAL PORT OPERATION The number of bytes transferred during Phase 2 of the communication cycle is a function of the register being accessed. For example, when accessing Control Function Register 2, which is four bytes wide, Phase 2 requires that four bytes be transferred. If accessing a frequency tuning word, which is six bytes wide, Phase 2 requires that six bytes be transferred. After transferring all data bytes per the instruction, the communication cycle is completed. An AD9540 serial data port communication cycle has two phases. Phase 1 is the instruction cycle, writing an instruction byte to the AD9540, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9540 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines the serial address of the register being accessed and whether the upcoming data transfer is read or write. At the completion of any communication cycle, the AD9540 serial port controller expects the next eight rising SCLK edges to be the instruction byte of the next communication cycle. All data input to the AD9540 is registered on the rising edge of SCLK. All data is driven out of the AD9540 on the falling edge of SCLK. Figure 39 through Figure 42 are useful in understanding the general operation of the AD9540 serial port. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9540. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9540 and the system controller. . DATA TRANSFER CYCLE INSTRUCTION CYCLE CS I7 SDI/O I6 I1 I2 I3 I4 I5 I0 D7 D6 D5 D0 D1 D2 D3 D4 04947-019 SCLK Figure 39. Serial Port Write Timing--Clock Stall Low DATA TRANSFER CYCLE INSTRUCTION CYCLE CS SCLK I7 I5 I6 I0 I1 I2 I3 I4 DON'T CARE D6 D7 SDO D3 D4 D5 D1 D2 D0 04947-020 SDI/O Figure 40. 3-Wire Serial Port Read Timing--Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS I7 SDI/O I6 I2 I3 I4 I5 I1 I0 D6 D7 D5 D4 D3 D2 D1 D0 04947-021 SCLK Figure 41. Serial Port Write Timing--Clock Stall High INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDI/O I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 Figure 42. 2-Wire Serial Port Read Timing--Clock Stall High Rev. C | Page 22 of 32 D3 D2 D1 D0 04947-022 SCLK Data Sheet AD9540 INSTRUCTION BYTE MSB/LSB TRANSFERS The instruction byte contains the following information. The AD9540 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSB first bit in Control Register 1 (CFR1[15]). The default value of this bit is low (MSB first). When CFR1[15] is set high, the AD9540 serial port is in LSB first format. The instruction byte must be written in the format indicated by CFR1[15]. If the AD9540 is in LSB first mode, the instruction byte must be written from LSB to MSB. However, the instruction byte phase of the communication cycle still precedes the data transfer cycle. D5 X D4 A4 D3 A3 D2 A2 D1 A1 LSB D0 A0 R/Wb--Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation. Logic 0 indicates a write operation. X, X--Bit 6 and Bit 5 of the instruction byte are don't care. A4, A3, A2, A1, and A0--Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. SERIAL INTERFACE PORT PIN DESCRIPTION SCLK--Serial Clock. The serial clock pin is used to synchronize data to and from the AD9540 and to run the internal state machines. The SCLK maximum frequency is 25 MHz. CS--Chip Select Bar. CS is the active low input that allows more than one device on the same serial communications line. The SDO pin and SDI/O pin go to a high impedance state when this input is high. If driven high during any communications cycle, that cycle is suspended until CS is reactivated low. Chip select can be tied low in systems that maintain control of SCLK. SDI/O--Serial Data Input/Output. Data is always written to the AD9540 on this pin. However, this pin can be used as a bidirectional data line. CFR1[7] controls the configuration of this pin. The default value (0) configures the SDI/O pin as bidirectional. SDO--Serial Data Output. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. When the AD9540 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. For MSB first operation, all data written to (or read from) the AD9540 are in MSB first order. If the LSB mode is active, all data written to (or read from) the AD9540 are in LSB first order. TPRE TSCLKW CS TDSU SCLK TDHLD SDI/O SECOND BIT FIRST BIT SYMBOL TPRE TSCLKW TDSU TDHLD MIN 6ns 40ns 6.5ns 0ns DEFINITION CS SETUP TIME PERIOD OF SERIAL DATA CLOCK (WRITE) SERIAL DATA SETUP TIME SERIAL DATA HOLD TIME 04947-039 D6 X Figure 43. Timing Diagram for Data Write to AD9540 TSCLKR CS SCLK SDI/O SDO I/O_RESET--A high signal on this pin resets the I/O port state machines without affecting the addressable registers' contents. An active high input on the I/O_RESET pin causes the current communication cycle to abort. After I/O_RESET returns low (0), another communication cycle can begin, starting with the instruction byte write. Note that when not in use, this pin should be forced low, because it floats to the threshold value. Rev. C | Page 23 of 32 FIRST BIT SECOND BIT TDV SYMBOL TDV TSCLKR MAX DEFINITION 40ns DATA VALID TIME 400ns PERIOD OF SERIAL DATA CLOCK (READ) Figure 44. Timing Diagram for Data Read from AD9540 04947-040 MSB D7 R/Wb AD9540 Data Sheet REGISTER MAP AND DESCRIPTION Table 4. Register Map Register Name (Serial Address) Control Function Register 1 (CFR1) (0x00) Control Function Register 2 (CFR2) (0x01) Bit Range [31:24] [23:16] Bit 6 Open1 AutoClear Freq. Accum. SDI/O Input Only PFD Input PowerDown Open1 Bit 5 Open1 AutoClear Phase Accum. Open1 Bit 4 Open1 Enable Sine Output Bit 3 Open1 Clear Freq. Accum. Bit 2 Open1 Clear Phase Accum. Bit 1 Open1 Open1 Bit 0 (LSB) STATUS_Error Open1 Open1 Open1 Open1 Open1 Open1 0x00 REFIN Cyrstal Enable SYNC_CLK Out Disable Software Manual Sync Hardware Manual Sync High Speed Sync Enable 0x00 Open1 Open1 Auto Sync Multiple AD9540s Open1 Open1 Internal Band Gap PowerDown PLL Lock Detect Enable Slew Rate Control Internal CML Driver DRV_RSET 0x00 PLL Lock Detect Mode 0x00 RF Div CLK1 Mux Bit 0x78 [15:8] LSB First [7:0] Digital PowerDown [39:32] DAC PowerDown [31:24] Clock Driver Rising Edge [31:29] [23:16] RF Divider PowerDown [15:8] [7:0] Rising Delta Frequency Tuning Word (RDFTW) (0x02) Falling Delta Frequency Tuning Word (FDFTW) (0x03) Rising Sweep Ramp Rate (RSRR) (0x04) Falling Sweep Ramp Rate (FSRR) (0x05) Bit 7 (MSB) Open1 Load SRR @ I/O_UPDATE Default Value/ Profile 0x00 0x00 [23:16] [15:8] [7:0] Open1 RF Divider Ratio[22:21] Clock Driver Falling Edge Control [28:26] Clock Driver PowerDown Clock Driver Input Select [19:18] Divider N Control[15:12] Divider M Control[11:8] Open1 CP CP Full PD CP Quick CP Current Scale[2:0] Polarity PD Rising Delta Frequency Tuning Word [23:16] Rising Delta Frequency Tuning Word [15:8] Rising Delta Frequency Tuning Word [7:0] 0x00 0x07 0x00 0x00 0x00 [23:16] [15:8] [7:0] Falling Delta Frequency Tuning Word [23:16] Falling Delta Frequency Tuning Word [15:8] Falling Delta Frequency Tuning Word [7:0] 0x00 0x00 0x00 [15:8] [7:0] Rising Sweep Ramp Rate [15:8] Rising Sweep Ramp Rate [7:0] 0x00 0x00 [15:8] [7:0] Falling Sweep Ramp Rate [15:8] Falling Sweep Ramp Rate [7:0] 0x00 0x00 Rev. C | Page 24 of 32 Data Sheet Register Name (Serial Address) Profile Control Register 0 (PCR0) (0x06) Profile Control Register 1 (PCR1) (0x07) Profile Control Register 2 (PCR2) (0x08) Profile Control Register 3 (PCR3) (0x09) Profile Control Register 4 (PCR4) (0x0A) Profile Control Register 5 (PCR5) (0x0B) Bit Range [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] AD9540 Bit 7 (MSB) Bit 6 1 Open Open1 Open1 Open1 Open1 Open1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Phase Offset Word 0 (POW0) [13:8] Phase Offset Word 0 (POW0) [7:0] Frequency Tuning Word 0 (FTW0) [47:40] Frequency Tuning Word 0 (FTW0) [39:32] Frequency Tuning Word 0 (FTW0) [31:24] Frequency Tuning Word 0 (FTW0) [23:16] Frequency Tuning Word. 0 (FTW0) [15:8] Frequency Tuning Word 0 (FTW0) [7:0] Phase Offset Word 1 (POW1) [13:8] Phase Offset Word 1 (POW1) [7:0] Frequency Tuning Word 1 (FTW1) [47:40] Frequency Tuning Word 1 (FTW1) [39:32] Frequency Tuning Word 1 (FTW1) [31:24] Frequency Tuning Word 1 (FTW1) [23:16] Frequency Tuning Word 1 (FTW1) [15:8] Frequency Tuning Word 1 (FTW1) [7:0] Phase Offset Word 2 (POW2) [13:8] Phase Offset Word 2 (POW2) [7:0] Frequency Tuning Word 2 (FTW1) [47:40] Frequency Tuning Word 2 (FTW2) [39:32] Frequency Tuning Word 2 (FTW2) [31:24] Frequency Tuning Word 2 (FTW2) [23:16] Frequency Tuning Word 2 (FTW2) [15:8] Frequency Tuning Word 2 (FTW2) [7:0] Phase Offset Word 3 (POW3) [13:8] Phase Offset Word 3 (POW3) [7:0] Frequency Tuning Word 3 (FTW3) [47:40] Frequency Tuning Word 3 (FTW3) [39:32] Frequency Tuning Word 3 (FTW3) [31:24] Frequency Tuning Word 3 (FTW3) [23:16] Frequency Tuning Word 3 (FTW3) [15:8] Frequency Tuning Word 3 (FTW3) [7:0] Phase Offset Word 4 (POW4) [13:8] Phase Offset Word 4 (POW4) [7:0] Frequency Tuning Word. 4 (FTW4) [47:40] Frequency Tuning Word 4 (FTW4) [39:32] Frequency Tuning Word 4 (FTW4) [31:24] Frequency Tuning Word 4 (FTW4) [23:16] Frequency Tuning Word 4 (FTW4) [15:8] Frequency Tuning Word 4 (FTW4) [7:0] Phase Offset Word 5 (POW5) [13:8] Phase Offset Word 5 (POW5) [7:0] Frequency Tuning Word 5 (FTW5) [47:40] Frequency Tuning Word 5 (FTW5) [39:32] Frequency Tuning Word 5 (FTW5) [31:24] Frequency Tuning Word 5 (FTW5) [23:16] Frequency Tuning Word 5 (FTW5) [15:8] Frequency Tuning Word 5 (FTW5) [7:0] Rev. C | Page 25 of 32 Bit 0 (LSB) Default Value/ Profile 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 AD9540 Register Name (Serial Address) Profile Control Register 6 (PCR6) (0x0C) Profile Control Register 7 (PCR7) (0x0D) 1 Data Sheet Bit Range [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] Bit 7 (MSB) Bit 6 1 Open Open1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Phase Offset Word 6 (POW6) [13:8] Phase Offset Word 6 (POW6) [7:0] Frequency Tuning Word 6 (FTW6) [47:40] Frequency Tuning Word 6 (FTW6) [39:32] Frequency Tuning Word 6 (FTW6) [31:24] Frequency Tuning Word 6 (FTW6) [23:16] Frequency Tuning Word 6 (FTW6) [15:8] Frequency Tuning Word 6 (FTW6) [7:0] Phase Offset Word 7 (POW7) [13:8] Phase Offset Word 7 (POW7) [7:0] Frequency Tuning Word 7 (FTW7) [47:40] Frequency Tuning Word 7 (FTW7) [39:32] Frequency Tuning Word 7 (FTW7) [31:24] Frequency Tuning Word 7 (FTW7) [23:16] Frequency Tuning Word 7 (FTW7) [15:8] Frequency Tuning Word 7 (FTW7) [7:0] In all cases, Open bits must be written to 0. Rev. C | Page 26 of 32 Bit 0 (LSB) Default Value/ Profile 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Data Sheet AD9540 CONTROL REGISTER BIT DESCRIPTIONS CFR1[22] = 0 (default). Issuing an I/O_UPDATE has no effect on the current state of the frequency accumulator. Control Function Register 1 (CFR1) This control register is comprised of four bytes that must be written during a write operation involving CFR1. CFR1 is used to control various functions, features, and operating modes of the AD9540. The functionality of each bit is described below. In general, the bit is named for the function it serves when the bit is set. CFR1[31:25] Open Unused locations. Write a Logic 0. CFR1[24] STATUS_Error (Read Only) When the device is operating in automatic synchronization mode or hardware manual synchronization mode the SYNC_IN/STATUS pin behaves as the SYNC_IN. To determine whether or not the PLL has become unlocked while in synchronization mode, this bit serves as a flag to indicate that an unlocked condition has occurred within the phase frequency detector. Once set, the flag stays high until it is cleared by a readback of the value even though the loop might have relocked. Readback of the CFR1 register clears this bit. CFR1[24] = 0 indicates that the loop has maintained lock since the last readback. CFR1[24] = 1 indicates that the loop became unlocked at some point since the last readback of this bit. CFR1[22] = 1. Issuing an I/O_UPDATE signal to the part clears the current contents of the frequency accumulator for one syncclock period. CFR1[21] Auto Clear Phase Accumulator This bit enables the auto clear function for the phase accumulator. The auto clear function serves as a reset function for the phase accumulator, which then begins accumulating from a known phase value of 0. CFR1[21] = 0 (default). Issuing an I/O_UPDATE has no effect on the current state of the phase accumulator. CFR1[21] = 1. Issuing an I/O_UPDATE clears the current contents of the phase accumulator for one SYNC_CLK period. CFR1[20] Enable Sine Output Two different trigonometric functions can be used to convert the phase angle to an amplitude value, cosine, or sine. This bit selects the function used. CFR1[20] = 0 (default). The phase-to-amplitude conversion block uses a cosine function. CFR1[20] = 1. The phase-to-amplitude conversion block uses a sine function. CFR1[19] Clear Frequency Accumulator CFR1[23] Load Sweep Ramp Rate at I/O_UPDATE, also known as Load SRR @ I/O_UPDATE The sweep ramp rate is set by entering a value to a downcounter that is clocked by the SYNC_CLK. Each time a new step is taken in the linear sweep algorithm, the ramp rate value is passed from the linear sweep ramp rate register to this downcounter. When set, CFR1[23] enables the user to force the part to restart the countdown sequence for the current linear sweep step by toggling the I/O_UPDATE pin. CFR1[23] = 0 (default). The linear sweep ramp rate countdown value is loaded only upon completion of a countdown sequence. CFR1[23] = 1. The linear sweep ramp rate countdown value is reloaded, if an I/O_UPDATE signal is sent to the part during a sweep. This bit serves as a static clear, or a clear-and-hold bit for the frequency accumulator. It prevents the frequency accumulator from incrementing the value as long as it is set. CFR1[19] = 0 (default). The frequency accumulator operates normally. CFR1[19] = 1. The frequency accumulator is cleared and held at 0. CFR1[18] Clear Phase Accumulator This bit serves as a static clear, or a clear-and-hold bit for the phase accumulator. It prevents the phase accumulator from incrementing the value as long as it is set. CFR1[18] = 0 (default). The phase accumulator operates normally. CFR1[18] = 1. The phase accumulator is cleared and held at 0. CFR1[22] Auto-Clear Frequency Accumulator This bit enables the auto clear function for the frequency accumulator. The auto clear function serves as a clear and release function for the frequency accumulator. This performs the linear sweep operation that then begins sweeping from a known value of FTW0. CFR1[17:16] Open Unused locations. Write a Logic 0. CFR1[15] LSB First Serial Data Mode The serial data transfer to the device can be either MSB first or LSB first. This bit controls that operation. Rev. C | Page 27 of 32 AD9540 Data Sheet CFR1[15] = 0 (default). Serial data transfer to the device is in MSB first mode. CFR1[15] = 1. Serial data transfer to the device is in LSB first mode. CFR1[14] SDI/O Input Only (3-Wire Serial Data Mode) The serial port on the AD9540 can act in 2-wire mode (SCLK and SDI/O) or 3-wire mode (SCLK, SDI/O, and SDO). This bit toggles the serial port between these two modes. CFR1[4] SYNC_CLK Disable If synchronization of multiple devices is not required, the spectral energy resulting from this signal can be reduced by gating the output buffer off. This function gates the internal clock reference SYNC_CLK (SYSCLK / 4) off of the SYNC_OUT pin. CFR1[4] = 0 (default). The SYNC_CLK signal is present on the SYNC_OUT pin and is ready to be ported to other devices. CFR1[14] = 0 (default). Serial data transfer to the device is in 2-wire mode. The SDI/O pin is bidirectional. CFR1[4] = 1. The SYNC_CLK signal is gated off, putting the SYNC_OUT pin into a high impedance state. CFR1[14] = 1. Serial data transfer to the device is in 3-wire mode. The SDI/O pin is input only. CFR1[3] Automatic Synchronization One of the synchronization modes of the AD9540 forces the DDS core to derive the internal reference from an external reference supplied on the SYNC_IN pin. For details on synchronization modes for the DDS core, see the Synchronization Modes for Multiple Devices section. CFR1[13:8] Open Unused locations. Write a Logic 0. CFR1[7] Digital Power-Down This bit powers down the digital circuitry not directly related to the I/O port. The I/O port functionality is not suspended, regardless of the state of this bit. CFR1[7] = 0 (default). Digital logic operating as normal. CFR1[7] = 1. All digital logic not directly related to the I/O port is powered down. Internal digital clocks are suspended. CFR1[3] = 0 (default). The automatic synchronization function of the DDS core is disabled. CFR1[3] = 1. The automatic synchronization function is on. The device is slaved to an external reference and adjusts the internal SYNC_CLK to match the external reference that is supplied on the SYNC_IN input. CFR1[2] Software Manual Synchronization CFR1[6] Phase Frequency Detector Input Power-Down This bit controls the input buffers on the phase frequency detector. It provides a way to gate external signals from the phase frequency detector. Rather than relying on the part to automatically synchronize the internal clocks, the user can program the part to advance the internal SYNC_CLK one system clock cycle. This bit is self clearing and can be set multiple times. CFR1[6] = 0 (default). Phase frequency detector input buffers are functioning normally. CFR1[2] = 0 (default). The SYNC_CLK stays in the current timing relationship to SYSCLK. CFR1[6] = 1. Phase frequency detector input buffers are powered down, isolating the phase frequency detector from the outside world. CFR1[2] = 1. The SYNC_CLK advances the rising and falling edges by one SYSCLK cycle. This bit is then self-cleared. CFR1[1] Hardware Manual Synchronization CFR1[5] REFIN Crystal Enable The AD9540 phase frequency detector has an on-chip oscillator circuit. When enabled, the reference input to the phase frequency detector (REFIN/REFIN) can be driven by a crystal. CFR1[5] = 0 (default). The phase frequency detector reference input operates as a standard analog input. CFR1[5] = 1. The reference input oscillator circuit is enabled, allowing the use of a crystal for the reference of the phase frequency detector. Similar to the software manual synchronization (CFR1[2]), this function enables the user to advance the SYNC_CLK rising edge by one system clock period. This bit enables the SYNC_IN/STATUS pin as a digital input. Once enabled, every rising edge on the SYNC_IN input advances the SYNC_CLK by one SYSCLK period. While enabled, the STATUS signal is not available on an external pin. However, loop out-of-lock events trigger a flag in the Control Register CFR1[24]. Rev. C | Page 28 of 32 Data Sheet AD9540 CFR1[1] = 0 (default). The hardware manual synchronization function is disabled. Either the part is outputting the STATUS (CFR1[3] = 0) or it is using the SYNC_IN to slave the SYNC_CLK signal to an external reference provided on SYNC_IN (CFR1[3] = 1). CFR1[1] = 1. The SYNC_IN/STATUS pin is set as a digital input. Each subsequent rising edge on this pin advances the SYNC_CLK rising edge by one SYSCLK period. CFR2[32] = 0 (default). The DRV_RSET pin is enabled, and an external resistor must be attached to the CP_RSET pin to program the output current. CFR2[32] = 1. The CML current is programmed by the internal resistor and ignores the resistor on the DRV_RSET pin. CFR2[31:29] Clock Driver Rising Edge CFR1[0] High Speed Synchronization Enable Bit This bit enables extra functionality in the autosynchronization algorithm, which enables the device to synchronize high speed clocks (SYNC_CLK > 62.5 MHz). CFR1[0] = 0 (default). High speed synchronization is disabled. These bits control the slew rate of the rising edge of the CML clock driver output. When these bits are on, additional current is sent to the output driver to increase the rising edge slew rate capability. Table 5 describes how the bits increase the current. The additional current is on only during the rising edge of the waveform for approximately 250 ps, not during the entire transition. Table 5. CML Clock Driver Rising Edge Slew Rate Control Bits and Associated Surge Current CFR1[0] = 1. High speed synchronization is enabled. Control Function Register 2 (CFR2) The Control Register 2 is comprised of five bytes, that must be written during a write operation involving CFR2. With some minor exceptions, the CFR2 primarily controls analog and timing functions on the AD9540. CFR2[39] DAC Power-Down Bit This bit powers down the DAC portion of the AD9540 and puts it into the lowest power dissipation state. CFR2[39] = 0 (default). DAC is powered on and operating. CFR2[39] = 1. DAC is powered down and the output is in a high impedance state. CFR2[31] = 1 CFR2[30] = 1 CFR2[29] = 1 7.6 mA 3.8 mA 1.9 mA CFR2[28:26] Clock Driver Falling Edge Control These bits control the slew rate of the falling edge of the CML clock driver output. When these bits are on, additional current is sent to the output driver to increase the rising edge slew rate capability. Table 6 describes how the bits increase the current. The additional current is on only during the rising edge of the waveform, for approximately 250 ps, not during the entire transition. Table 6. CML Clock Drive Falling Edge Slew Rate Control Bits and Associated Surge Current CFR2[38:34] Open CFR2[28] = 1 CFR2[30] = 1 CFR2[29] = 1 Unused locations. Write a Logic 0. CFR2[33] Internal Band Gap Power-Down 5.4 mA 2.7 mA 1.35 mA To shut off all internal quiescent current, the band gap needs to be powered down. This is normally not done because it takes a long time (~10 ms) for the band gap to power up and settle to its final value. CFR2[25] PLL Lock Detect Enable CFR2[33] = 0. Even when all other sections are powered down, the band gap is powered up and is providing a regulated voltage. CFR2[25] = 0 (default).The STATUS_DETECT signal is disabled. CFR2[33] = 1. The band gap is powered down. CFR2[25] = 1. The STATUS_DETECT signal is enabled. CFR2[32] Internal CML Driver DRV_RSET CFR2[24] PLL Lock Detect Mode To program the CML driver output current, a resistor must be placed between the DRV_RSET pin and ground. This bit enables an internal resistor to program the output current of the driver. This bit toggles the modes of the PLL lock detect function. The lock detect can either be a status indicator (locked or unlocked) or it can indicate a lead-lag relationship between the two phase frequency detector inputs. This bit enables the SYNC_IN/STATUS pin as a lock detect output for the PLL. Rev. C | Page 29 of 32 AD9540 Data Sheet CFR2[24] = 0 (default). The lock detect acts as a status indicator (PLL is locked 0 or unlocked 1). This bit disables all slew rate enhancement surge current, including the default values. CFR2[24] = 1. The lock detect acts as a lead-lag indicator. A 1 on the STATUS pin means that the CLK2 pin lags the reference. A 0 means that the CLK2 pin leads the reference. CFR2[17] = 0 (default). The CML driver applies default surge current to rising and falling edges. CFR2[23] RF Divider Power-Down This bit powers down the RF divider to save power when not in use. CFR2[17] = 1. Driver applies no surge current during transitions. The only current is the continuous current. CFR2[16] RF Divider CLK1 Mux CFR2[23] = 0 (default). The RF divider is on. This bit toggles the mux to control whether the RF divider output or input is supplying SYSCLK to the device. CFR2[23] = 1. The RF divider is powered down and an alternate path between the CLK1 inputs and SYSCLK is enabled. CFR2[16] = 0 (default). The RF divider output supplies the DDS SYSCLK. CFR2[22:21] RF Divider Ratio CFR2[22:21] = 11 (default). RF Divider R = 8. CFR2[16] = 1. The RF divider input supplies the DDS SYSCLK (bypass the divider). Note that regardless of the condition of the configuration of the clock input, the DDS SYSCLK must not exceed the maximum rated clock speed. CFR2[22:21] = 10. RF Divider R = 4. CFR2[15:12] CLK2 Divider (/N) Control Bits CFR2[22:21] = 01. RF Divider R = 2. These four bits set the CLK2 divider (/N) ratio where N is a value = 1 to 16, and CFR2[15:12] = 0000 means that N = 1 and CFR2[15:12] = 1111 means that N = 16 or simply, N = CFR2[15:12] + 1. These two bits control the RF divider ratio (/R). CFR2[22:21] = 00. RF Divider R = 1. Note that this is not the same as bypassing the RF divider. CFR2[20] Clock Driver Power-Down Table 7. CLK2 Divider Values (/N) This bit powers down the CML clock driver circuit. CFR2[15:12] 0000 0001 0010 0011 0100 0101 0110 0111 CFR2[20] =1 (default). The CML clock driver circuit is powered down. CFR2[20] = 0. The CML clock driver is powered up. CFR2[19:18] Clock Driver Input Select These bits control the mux on the input for the CML clock driver. CFR2[19:18] = 00. The CML clock driver is disconnected from all inputs (and does not toggle). CFR2[19:18] = 01. The CML clock driver is driven by the CLK2 input pin. CFR2[19:18] = 10 (default). The CML clock driver is driven by the output of the RF divider. CFR2[19:18] = 11. The CML clock driver is driven by the input of the RF divider CFR2[17] Slew Rate Control Bit Even without the additional surge current supplied by the rising edge slew rate control bits and the falling edge slew rate control bits, the device applies a default 7.6 mA surge current to the rising edge and a 4.05 mA surge current to the falling edge. N 1 2 3 4 5 6 7 8 CFR2[15:12] 1000 1001 1010 1011 1100 1101 1110 1111 N 9 10 11 12 13 14 15 16 CFR2[11:8] REFIN Divider (/M) Control Bits These 4 bits set the REFIN divider (/M) ratio where the M = 1 to 16 and CFR2[11:8] = 0000 means that M = 1, and CFR2[11:8] = 1111 means that M = 16 or M = CFR2[11:8] + 1. Table 8. REFIN Input Divider Values (/M) CFR2[15:12] 0000 0001 0010 0011 0100 0101 0110 0111 Rev. C | Page 30 of 32 M 1 2 3 4 5 6 7 8 CFR2[11:8] 1000 1001 1010 1011 1100 1101 1110 1111 M 9 10 11 12 13 14 15 16 Data Sheet AD9540 CFR2[7:6] Open CFR2[3] Charge Pump Quick Power-Down Unused locations. Write a Logic 0. Rather than power down the charge pump, which have a long recovery time, a quick power-down mode that powers down only the charge pump output buffer is included. Though this does not reduce the power consumption significantly, it does shut off the output to the charge pump and allows it to come back on rapidly. CFR2[5] CP Polarity This bit sets the polarity of the charge pump in response to a ground referenced or a supply referenced VCO. CFR2[5] = 0 (default). The charge pump is configured to operate with a supply referenced VCO. If CLK2 lags REFIN, the charge pump attempts to drive the VCO control node voltage higher. If CLK2 leads REFIN, the charge pump attempts to drive the VCO control node voltage lower. CFR2[5] = 1. The charge pump is configured to operate with a ground referenced VCO. If CLK2 lags REFIN, the charge pump attempts to drive the VCO control node voltage lower. If CLK2 leads REFIN, the charge pump attempts to drive the VCO control node voltage higher. CFR2[4] Charge Pump Full Power-Down This bit, when set, puts the charge pump into a full power-down mode. CFR2[4] = 0 (default). The charge pump is powered on and operating normally. CFR2[3] = 0 (default). The charge pump is powered on and operating normally. CFR2[3] = 1. The charge pump is on and running, but the output buffer is powered down. CFR2[2:0] Charge Pump Current Scale A base output current from the charge pump is determined by a resistor connected from the CP_RSET pin to ground (see the PLL Circuitry section). However, it is possible to multiply the charge pump output current by a value from 1:8 by programming these bits. The charge pump output current is scaled by CFR2[2:0] +1. CFR2[2:0] = 000 (default) Scale factor = 1 to CFR2[2:0] = 111 (8). CFR2[4] = 1. The charge pump is powered down completely. Rev. C | Page 31 of 32 AD9540 Data Sheet OUTLINE DIMENSIONS 0.30 0.23 0.18 0.60 MAX 0.60 MAX 37 48 1 36 PIN 1 INDICATOR 6.85 6.75 SQ 6.65 0.50 REF 5.25 5.10 SQ 4.95 EXPOSED PAD 12 25 0.50 0.40 0.30 TOP VIEW 12 MAX 1.00 0.85 0.80 SIDE VIEW PKG-001049 13 24 BOTTOM VIEW 0.20 MIN 5.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 11-13-2017-B 7.10 7.00 SQ 6.90 Figure 45. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm x 7 mm Body and 0.85 mm Package Height (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9540BCPZ AD9540BCPZ-REEL7 1 Temperature Range -40C to +85C -40C to +85C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP] 48-Lead Lead Frame Chip Scale Package [LFCSP] Tape and Reel Z = RoHS Compliant Part. (c)2004-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04947-0-4/18(C) Rev. C | Page 32 of 32 Package Option CP-48-1 CP-48-1 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: AD9540/PCBZ AD9540-VCO/PCBZ