This is information on a product in full production.
January 2017 DocID026284 Rev 4 1/128
STM32F091xB STM32F091xC
ARM®-based 32-bit MCU, up to 256 KB Flash, CAN, 12 timers,
ADC, DAC, and comm. interfaces, 2.0 - 3.6V
Datasheet - production data
Features
Core: ARM® 32-bit Cortex®-M0 CPU,
frequency up to 48 MHz
Memories
128 to 256 Kbytes of Flash memory
32 Kbytes of SRAM with HW parity
CRC calculation unit
Reset and power management
Digital & I/Os supply: VDD = 2.0 V to 3.6 V
Analog supply: VDDA = VDD to 3.6 V
Power-on/Power down reset (POR/PDR)
Programmable voltage detector (PVD)
Low power modes: Sleep, Stop, Standby
–V
BAT supply for RTC and backup registers
Clock management
4 to 32 MHz crystal oscillator
32 kHz oscillator for RTC with calibration
Internal 8 MHz RC with x6 PLL option
Internal 40 kHz RC oscillator
Internal 48 MHz oscillator with automatic
trimming based on ext. synchronization
Up to 88 fast I/Os
All mappable on external interrupt vectors
Up to 69 I/Os with 5V-tolerant capability
and 19 with independent supply VDDIO2
12-channel DMA controller
One 12-bit, 1.0 µs ADC (up to 16 channels)
Conversion range: 0 to 3.6 V
Separate analog supply: 2.4 V to 3.6 V
One 12-bit D/A converter (with 2 channels)
Two fast low-power analog comparators with
programmable input and output
Up to 24 capacitive sensing channels for
touchkey, linear and rotary touch sensors
Calendar RTC with alarm and periodic wakeup
from Stop/Standby
12 timers
One 16-bit advanced-control timer for
6 channel PWM output
One 32-bit and seven 16-bit timers, with up
to 4 IC/OC, OCN, usable for IR control
decoding or DAC control
Independent and system watchdog timers
SysTick timer
Communication interfaces
–Two I
2C interfaces supporting Fast Mode
Plus (1 Mbit/s) with 20 mA current sink, one
supporting SMBus/PMBus and wakeup
Up to eight USARTs supporting master
synchronous SPI and modem control, three
with ISO7816 interface, LIN, IrDA, auto
baud rate detection and wakeup feature
Two SPIs (18 Mbit/s) with 4 to 16
programmable bit frames, and with I2S
interface multiplexed
CAN interface
HDMI CEC wakeup on header reception
Serial wire debug (SWD)
96-bit unique ID
All packages ECOPACK®2
Table 1. Device summary
Reference Part number
STM32F091xB STM32F091CB, STM32F091RB, STM32F091VB
STM32F091xC STM32F091CC, STM32F091RC, STM32F091VC
LQFP100 14x14 mm
LQFP64 10x10 mm
LQFP48 7x7 mm
UFQFPN48
7x7 mm
)%*$
UFBGA100
7x7 mm
UFBGA64
5x5 mm
WLCSP64
3.3x3.6mm
www.st.com
Contents STM32F091xB STM32F091xC
2/128 DocID026284 Rev 4
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 ARM®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14
3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 17
3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 18
3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 22
3.14.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DocID026284 Rev 4 3/128
STM32F091xB STM32F091xC Contents
4
3.14.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23
3.16 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 25
3.18 Serial peripheral interface (SPI) / Inter-integrated sound interface (I2S) . 26
3.19 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.20 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.21 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.22 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 54
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 55
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Contents STM32F091xB STM32F091xC
4/128 DocID026284 Rev 4
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.18 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.20 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.21 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.22 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.3 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.4 WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.5 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
7.6 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
7.7 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 121
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
DocID026284 Rev 4 5/128
STM32F091xB STM32F091xC List of tables
6
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F091xB/xC family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . 11
Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Capacitive sensing GPIOs available on STM32F091xB/xC devices . . . . . . . . . . . . . . . . . 20
Table 6. Number of capacitive sensing channels available
on STM32F091xB/xC devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. STM32F091xB/xC I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. STM32F091xB/xC USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. STM32F091xB/xC SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. STM32F091xB/xC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 41
Table 15. Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 42
Table 16. Alternate functions selected through GPIOC_AFR registers for port C . . . . . . . . . . . . . . . 43
Table 17. Alternate functions selected through GPIOD_AFR registers for port D . . . . . . . . . . . . . . . 43
Table 18. Alternate functions selected through GPIOE_AFR registers for port E . . . . . . . . . . . . . . . 44
Table 19. Alternate functions selected through GPIOF_AFR registers for port F. . . . . . . . . . . . . . . . 44
Table 20. STM32F091xB/xC peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . 46
Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 25. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 27. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 28. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 29. Typical and maximum current consumption from VDD supply at VDD = 3.6 V . . . . . . . . . . 58
Table 30. Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . 59
Table 31. Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 60
Table 32. Typical and maximum current consumption from the VBAT supply. . . . . . . . . . . . . . . . . . . 61
Table 33. Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 34. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 35. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 36. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 37. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 38. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 39. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 41. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 42. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 43. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 44. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 45. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 46. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
List of tables STM32F091xB STM32F091xC
6/128 DocID026284 Rev 4
Table 47. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 48. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 49. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 50. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 51. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 52. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 53. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 54. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 55. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 56. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 57. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 58. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 59. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 60. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 61. Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 62. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 63. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 64. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 65. IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 66. WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 67. I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 68. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 69. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 70. UFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 71. UFBGA100 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 72. LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 73. UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 74. UFBGA64 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 75. WLCSP64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 76. WLCSP64 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 77. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 78. LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 79. UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 80. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 81. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 82. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
DocID026284 Rev 4 7/128
STM32F091xB STM32F091xC List of figures
8
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. UFBGA100 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 4. LQFP100 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 5. UFBGA64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 6. LQFP64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 7. WLCSP64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. LQFP48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 9. UFQFPN48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. STM32F091xC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 13. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 16. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 17. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 19. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 72
Figure 20. HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 21. HSI48 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 22. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 26. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 28. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 29. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 30. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 31. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 32. I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 33. UFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 34. Recommended footprint for UFBGA100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 35. UFBGA100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 36. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 37. Recommended footprint for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 38. LQFP100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 39. UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 40. Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 41. UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 42. WLCSP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 43. Recommended footprint for WLCSP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 44. WLCSP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 45. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 46. Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 47. LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 48. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
List of figures STM32F091xB STM32F091xC
8/128 DocID026284 Rev 4
Figure 49. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 50. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 51. UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 52. Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 53. UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 54. LQFP64 PD max versus TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
DocID026284 Rev 4 9/128
STM32F091xB STM32F091xC Introduction
27
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F091xB/xC microcontrollers.
This document should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM® Cortex®-M0 core, please refer to the Cortex®-M0 Technical
Reference Manual, available from the www.arm.com website.
Description STM32F091xB STM32F091xC
10/128 DocID026284 Rev 4
2 Description
The STM32F091xB/xC microcontrollers incorporate the high-performance
ARM® Cortex®-M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed
embedded memories (up to 256 Kbytes of Flash memory and 32 Kbytes of SRAM), and an
extensive range of enhanced peripherals and I/Os. The device offers standard
communication interfaces (two I2Cs, two SPIs/one I2S, one HDMI CEC and up to eight
USARTs), one CAN, one 12-bit ADC, one 12-bit DAC with two channels, seven 16-bit
timers, one 32-bit timer and an advanced-control PWM timer.
The STM32F091xB/xC microcontrollers operate in the -40 to +85 °C and -40 to +105 °C
temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
The STM32F091xB/xC microcontrollers include devices in seven different packages ranging
from 48 pins to 100 pins with a die form also available upon request. Depending on the
device chosen, different sets of peripherals are included.
These features make the STM32F091xB/xC microcontrollers suitable for a wide range of
applications such as application control and user interfaces, hand-held equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs.
DocID026284 Rev 4 11/128
STM32F091xB STM32F091xC Description
27
Ta bl e 2. STM 32 F 09 1x B/ xC family dev ice fea t ure s an d pe ri ph e r al coun ts
Peripheral STM32F091Cx STM32F091Rx STM32F091Vx
Flash memory (Kbyte) 128 256 128 256 128 256
SRAM (Kbyte) 32
Timers
Advanced
control 1 (16-bit)
General
purpose
5 (16-bit)
1 (32-bit)
Basic 2 (16-bit)
Comm.
interfaces
SPI [I2S](1) 2 [2]
I2C2
USART 6 8
CAN 1
CEC 1
12-bit ADC
(number of channels)
1
(10 ext. + 3 int.)
1
(16 ext. + 3 int.)
12-bit DAC
(number of channels)
1
(2)
Analog comparator 2
GPIOs 38 52 88
Capacitive sensing
channels 17 18 24
Max. CPU frequency 48 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature Ambient operating temperature: -40°C to 85°C / -40°C to 105°C
Junction temperature: -40°C to 105°C / -40°C to 125°C
Packages LQFP48
UFQFPN48
LQFP64
UFBGA64
WLCSP64
LQFP100
UFBGA100
1. The SPI interface can be used either in SPI mode or in I2S audio mode.
Description STM32F091xB STM32F091xC
12/128 DocID026284 Rev 4
Figure 1. Block diagram
06Y9
3RZHUGRPDLQRIDQDORJEORFNV 9%$7
FKDQQHOV
FRPSOFKDQQHOV
%5.(75LQSXWDV$)
#9
''
#9''$
6\VWHPDQGSHULSKHUDO
FORFNV
3$>@
3%>@
3&>@
3)>@3)
3)>@
JURXSVRI
FKDQQHOV
6<1&
$)
026,6'
0,620&.
6&.&.
166:6DV$)
#9
''$
9
''$
9
66$
6:&/.
6:',2
DV$)
[
$'LQSXW
26&B,1
26&B287
9
%$7
WR9
26&B,1
26&B287
7$03(557&
$/$50287
#9%$7
6<1&
026,6'
0,620&.
6&.&.
166:6DV$)
+6,
+6,
/6,
+6,
3//&/.
9''
,5B287DV$)
FKDQQHO
FRPSO%5.DV$)
FKDQQHO
FRPSO%5.DV$)
FKDQQHODV$)
FK(75DV$)
FK(75DV$)
*3'0$
FKDQQHOV
&257(;0&38
I
0$;
 0+]
6HULDO:LUH
'HEXJ
19,&
7RXFK
6HQVLQJ
&RQWUROOHU
3$'
$QDORJ
VZLWFKHV
(;7,7:.83
63,,6
63,,6
6<6&)*,)
'%*0&8
:LQGRZ:'*
$3%
$+%
&5&
5(6(7&/2&.
&21752/
3:07,0(5
7,0(5ELW
7,0(5
7,0(5
7,0(5
7,0(5
3RZHU
&RQWUROOHU
;7$/26&
0+]
,QG:LQGRZ:'*
65$0
.%
7HPS
VHQVRU
,)
ELW$'&
57& %DFNXS
UHJ
57&LQWHUIDFH
&56
65$0
%
5&0+]
5&0+]
5&N+]
3//
5&0+]
$+%GHFRGHU
;7$/N+]
65$0
FRQWUROOHU
%XVPDWUL[
)ODVK
PHPRU\
LQWHUIDFH
)ODVK*3/
XSWR.%
ELW
2EO
9''
FKDQQHOV
FRPSO%5.DV$)
7,0(5
5;7;&76576
&.DV$)
86$57
5;7;&76576
&.DV$)
86$57
5;7;&76576
&.DV$)
86$57
5;7;576&.DV$)
86$57
5;7;576&.DV$)
86$57
5;7;576&.DV$)
86$57
5;7;576&.DV$)86$57
5;7;&76576
&.DV$)
86$57
6&/6'$
P$)0DV$)
6&/6'$60%$
P$)0DV$)
&(&DV$)
,&
,&
+'0,&(&
ELW'$&
ELW'$&
,)
'$&B287
'$&B287
#9
''$
7,0(5
7,0(5
%[&$1
*3FRPSDUDWRU
*3FRPSDUDWRU
,1387
,1387
287387
DV$)
#9
''$
7;5;DV$)
*3,2SRUW)
*3,2SRUW(
*3,2SRUW'
*3,2SRUW&
*3,2SRUW%
*3,2SRUW$
3'>@
3(>@
9''$
6833/<
683(59,6,21
32:(5
#9
''$
#9''
9
''
325
5HVHW
,QW
9
''
WR9
9
66
1567
9
''$
9
66$
9
'',2
2.,1
9
''
39'
3253'5
92/75(*
9WR9
DocID026284 Rev 4 13/128
STM32F091xB STM32F091xC Functional overview
27
3 Functional overview
Figure 1 shows the general block diagram of the STM32F091xB/xC devices.
3.1 ARM®-Cortex®-M0 core
The ARM® Cortex®-M0 is a generation of ARM 32-bit RISC processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM® Cortex®-M0 processors feature exceptional code-efficiency, delivering the high
performance expected from an ARM core, with memory sizes usually associated with 8- and
16-bit devices.
The STM32F091xB/xC devices embed ARM core and are compatible with all ARM tools
and software.
3.2 Memories
The device has the following features:
32 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
The non-volatile memory is divided into two arrays:
up to 256 Kbytes of embedded Flash memory for programs and data
Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
Level 2: chip readout protection, debug features (Cortex®-M0 serial wire) and
boot in RAM selection disabled
3.3 Boot modes
At startup, the boot pin and boot selector option bits are used to select one of the three boot
options:
boot from User Flash memory
boot from System Memory
boot from embedded SRAM
The boot pin is shared with the standard GPIO and can be disabled through the boot
selector option bits. The boot loader is located in System Memory. It is used to reprogram
the Flash memory by using USART on pins PA14/PA15 or PA9/PA10 or I2C on pins
PB6/PB7.
Functional overview STM32F091xB STM32F091xC
14/128 DocID026284 Rev 4
3.4 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5 Power management
3.5.1 Power supply schemes
VDD = VDDIO1 = 2.0 to 3.6 V: external power supply for I/Os (VDDIO1) and the internal
regulator. It is provided externally through VDD pins.
VDDA = from VDD to 3.6 V: external analog power supply for ADC, DAC, Reset blocks,
RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC
are used). It is provided externally through VDDA pin. The VDDA voltage level must be
always greater or equal to the VDD voltage level and must be established first.
VDDIO2 = 1.65 to 3.6 V: external power supply for marked I/Os. VDDIO2 is provided
externally through the VDDIO2 pin. The VDDIO2 voltage level is completely independent
from VDD or VDDA, but it must not be provided without a valid supply on VDD. The
VDDIO2 supply is monitored and compared with the internal reference voltage
(VREFINT). When the VDDIO2 is below this threshold, all the I/Os supplied from this rail
are disabled by hardware. The output of this comparator is connected to EXTI line 31
and it can be used to generate an interrupt. Refer to the pinout diagrams or tables for
concerned I/Os list.
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 13: Power supply scheme.
3.5.2 Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
DocID026284 Rev 4 15/128
STM32F091xB STM32F091xC Functional overview
27
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.5.3 Voltage regulator
The regulator has two operating modes and it is always enabled after reset.
Main (MR) is used in normal operating mode (Run).
Low power (LPR) can be used in Stop mode where the power demand is reduced.
In Standby mode, it is put in power down mode. In this mode, the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption (but the
contents of the registers and SRAM are lost).
3.5.4 Low-power modes
The STM32F091xB/xC microcontrollers support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC, I2C1, USART1,
USART2, USART3, COMPx, VDDIO2 supply comparator or the CEC.
The CEC, USART1, USART2, USART3 and I2C1 peripherals can be configured to
enable the HSI RC oscillator so as to get clock for processing incoming data. If this is
used when the voltage regulator is put in low power mode, the regulator is first
switched to normal mode before the clock is provided to the given peripheral.
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the RTC
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pins, or an RTC event occurs.
Note: The RTC, the IWDG, and th e corresponding clock source s are not sto pped by enter ing Stop
or Standby mode.
3.6 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
Functional overview STM32F091xB STM32F091xC
16/128 DocID026284 Rev 4
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Figure 2. Clock tree
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
06Y9
26&B,1
26&B287
26&B,1
26&B287
,:'*
3//08/
0&2
0DLQFORFN
RXWSXW
3//&/.
+6,
+6(
3//&/.
$'&
DV\QFKURQRXV
FORFNLQSXW
/6(
/6,
+6,
+6(
57&
3//65&
6:
0&2
57&&/.
57&6(/
6<6&/.
7,0

)/,7)&/. )ODVKPHPRU\
SURJUDPPLQJ
LQWHUIDFH
+6,
+6,
/6(
,&
86$57
/6(
+6,
6<6&/.
3&/.
6<6&/.
+6,
3&/.
,663,
,663,
&(&
$3%
SHULSKHUDOV
/6,
/6(
35(',9
+6,
3//12',9
0&235(
7,0
/6(
+6(
/6(
6<1&
&66
7ULP
/HJHQG
ZKLWH FORFNWUHHFRQWUROHOHPHQW
FORFNOLQH
FRQWUROOLQH
EODFN FORFNWUHHHOHPHQW

0+]
+6(26&



0+]5&
+6,
«
«
0+]
+6,5&


N+]
/6(26&
N+]
/6,5&
3//
[[
[
0+]
+6,5&
[[


86$57[6:
335(
335(+35(
&(&6:

,&6:
6<6&/.
&56
+6,
+6,
+6, +6,
+6,
6<1&65&
86$57
86$57
+&/.
$+%FRUHPHPRU\'0$
&RUWH[)&/.IUHHUXQFORFN
&RUWH[
V\VWHPWLPHU

DocID026284 Rev 4 17/128
STM32F091xB STM32F091xC Functional overview
27
Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL
input source. This oscillator can be automatically fine-trimmed by the means of the CRS
peripheral using the external synchronization.
3.7 General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.8 Direct memory access controller (DMA)
The 12-channel general-purpose DMAs (seven channels for DMA1 and five channels for
DMA2) manage memory-to-memory, peripheral-to-memory and memory-to-peripheral
transfers.
The DMAs support circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers
(except TIM14), DAC and ADC.
3.9 Interrupts and events
3.9.1 Nested vectored interrupt controller (NVIC)
The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M0) and 4
priority levels.
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
Functional overview STM32F091xB STM32F091xC
18/128 DocID026284 Rev 4
3.9.2 Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 32 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 88
GPIOs can be connected to the 16 external interrupt lines.
3.10 Analog-to-digital converter (ADC)
The 12-bit analog-to-digital converter has up to 16 external and 3 internal (temperature
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1 Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
3.10.2 Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and comparators. VREFINT is internally connected to the ADC_IN17 input channel. The
Table 3. Temp era tu r e se n sor ca lib rat io n value s
Calibration value name Description Memory address
TS_CAL1
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA= 3.3 V (± 10 mV)
0x1FFF F7B8 - 0x1FFF F7B9
TS_CAL2
TS ADC raw data acquired at a
temperature of 110 °C (± 5 °C),
VDDA= 3.3 V (± 10 mV)
0x1FFF F7C2 - 0x1FFF F7C3
DocID026284 Rev 4 19/128
STM32F091xB STM32F091xC Functional overview
27
precise voltage of VREFINT is individually measured for each part by ST during production
test and stored in the system memory area. It is accessible in read-only mode.
3.10.3 VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC_IN18. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 2. As a consequence, the converted digital value is half the VBAT voltage.
3.11 Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert digital signals into analog
voltage signal outputs. The chosen design structure is composed of integrated resistor
strings and an amplifier in non-inverting configuration.
This digital Interface supports the following features:
8-bit or 12-bit monotonic output
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Six DAC trigger inputs are used in the device. The DAC is triggered through the timer trigger
outputs and the DAC interface is generating its own DMA requests.
3.12 Comparators (COMP)
The device embeds two fast rail-to-rail low-power comparators with programmable
reference voltage (internal or external), hysteresis and speed (low speed for low power) and
with selectable output polarity.
The reference voltage can be one of the following:
External I/O
DAC output pins
Internal reference voltage or submultiple (1/4, 1/2, 3/4).Refer to Table 28: Embedded
internal refe re nc e vo ltage for the value and precision of the internal reference voltage.
Table 4. Internal voltage reference calibration values
Calibration value name Description Memory address
VREFINT_CAL
Raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA= 3.3 V (± 10 mV)
0x1FFF F7BA - 0x1FFF F7BB
Functional overview STM32F091xB STM32F091xC
20/128 DocID026284 Rev 4
Both comparators can wake up from STOP mode, generate interrupts and breaks for the
timers and can be also combined into a window comparator.
3.13 Touch sensing controller (TSC)
The STM32F091xB/xC devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 24 capacitive sensing channels
distributed over 8 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists in
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
For operation, one capacitive sensing GPIO in each group is connected to an external
capacitor and cannot be used as effective touch sensing channel.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Table 5. Capacitive sensing GPIOs available on STM32F091xB/xC devices
Group Capacitive sensing
signal name Pin
name Group Capacitive sensing
signal name Pin
name
1
TSC_G1_IO1 PA0
5
TSC_G5_IO1 PB3
TSC_G1_IO2 PA1 TSC_G5_IO2 PB4
TSC_G1_IO3 PA2 TSC_G5_IO3 PB6
TSC_G1_IO4 PA3 TSC_G5_IO4 PB7
2
TSC_G2_IO1 PA4
6
TSC_G6_IO1 PB11
TSC_G2_IO2 PA5 TSC_G6_IO2 PB12
TSC_G2_IO3 PA6 TSC_G6_IO3 PB13
TSC_G2_IO4 PA7 TSC_G6_IO4 PB14
3
TSC_G3_IO1 PC5
7
TSC_G7_IO1 PE2
TSC_G3_IO2 PB0 TSC_G7_IO2 PE3
TSC_G3_IO3 PB1 TSC_G7_IO3 PE4
TSC_G3_IO4 PB2 TSC_G7_IO4 PE5
4
TSC_G4_IO1 PA9
8
TSC_G8_IO1 PD12
TSC_G4_IO2 PA10 TSC_G8_IO2 PD13
TSC_G4_IO3 PA11 TSC_G8_IO3 PD14
TSC_G4_IO4 PA12 TSC_G8_IO4 PD15
DocID026284 Rev 4 21/128
STM32F091xB STM32F091xC Functional overview
27
3.14 Timers and watchdogs
The STM32F091xB/xC devices include up to six general-purpose timers, two basic timers
and an advanced control timer.
Table 7 compares the features of the different timers.
Table 6. Number of capacitive sensing channels available
on STM32F091xB/xC devices
Analog I/O group Number of capacitive sensing channels
STM32F091Vx STM32F091Rx STM32F091Cx
G1 3 3 3
G2 3 3 3
G3 3 3 2
G4 3 3 3
G5 3 3 3
G6 3 3 3
G7 3 0 0
G8 3 0 0
Number of capacitive
sensing channels 24 18 17
Table 7. Timer feature comparison
Timer
type Timer Counter
resolution Counter
type Prescaler
factor
DMA
request
generation
Capture/compare
channels Complementary
outputs
Advanced
control TIM1 16-bit Up, down,
up/down
integer from
1 to 65536 Yes 4 3
General
purpose
TIM2 32-bit Up, down,
up/down
integer from
1 to 65536 Yes 4 -
TIM3 16-bit Up, down,
up/down
integer from
1 to 65536 Yes 4 -
TIM14 16-bit Up integer from
1 to 65536 No 1 -
TIM15 16-bit Up integer from
1 to 65536 Yes 2 1
TIM16
TIM17 16-bit Up integer from
1 to 65536 Yes 1 1
Basic TIM6
TIM7 16-bit Up integer from
1 to 65536 Yes - -
Functional overview STM32F091xB STM32F091xC
22/128 DocID026284 Rev 4
3.14.1 Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
input capture
output compare
PWM generation (edge or center-aligned modes)
one-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17)
There are six synchronizable general-purpose timers embedded in the STM32F091xB/xC
devices (see Table 7 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
TIM2, TIM3
STM32F091xB/xC devices feature two synchronizable 4-channel general-purpose timers.
TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based
on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM15, TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
DocID026284 Rev 4 23/128
STM32F091xB STM32F091xC Functional overview
27
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate
withTIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.
3.14.3 Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
3.14.4 Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.14.5 System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
3.14.6 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
a 24-bit down counter
autoreload capability
maskable system interrupt generation when the counter reaches 0
programmable clock source (HCLK or HCLK/8)
3.15 Real-time clock (RTC) and backup registers
The RTC and the five backup registers are supplied through a switch that takes power either
on VDD supply when present or through the VBAT pin. The backup registers are five 32-bit
registers used to store 20 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or at wake up from Standby mode.
Functional overview STM32F091xB STM32F091xC
24/128 DocID026284 Rev 4
The RTC is an independent BCD timer/counter. Its main features are the following:
calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
automatic correction for 28, 29 (leap year), 30, and 31 day of the month
programmable alarm with wake up from Stop and Standby mode capability
Periodic wakeup unit with programmable resolution and period.
on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize the RTC with a master clock
digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
Three anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection
timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection
reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
The RTC clock sources can be:
a 32.768 kHz external crystal
a resonator or oscillator
the internal low-power RC oscillator (typical frequency of 40 kHz)
the high-speed external clock divided by 32
3.16 Inter-integrated circuit interface (I2C)
Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both
can support Standard mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode
Plus (up to 1 Mbit/s) with 20 mA output drive on most of the associated I/Os.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two
addresses, one with configurable mask). They also include programmable analog and
digital noise filters.
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
Table 8. Comparison of I2C analog and digital filters
Aspect Analog filter Digital filter
Pulse width of
suppressed spikes 50 ns Programmable length from 1 to 15
I2Cx peripheral clocks
Benefits Available in Stop mode
–Extra filtering capability vs.
standard requirements
–Stable length
Drawbacks Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
DocID026284 Rev 4 25/128
STM32F091xB STM32F091xC Functional overview
27
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C peripherals can be served by the DMA controller.
Refer to Table 9 for the differences between I2C1 and I2C2.
3.17 Universal synchronous/asynchronous receiver/transmitter
(USART)
The device embeds up to eight universal synchronous/asynchronous receivers/transmitters
(USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8) which
communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
half-duplex communication mode. USART1, USART2 and USART3 support also SmartCard
communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud
rate feature, and have a clock domain independent of the CPU clock, allowing to wake up
the MCU from Stop mode.
The USART interfaces can be served by the DMA controller.
Table 9. STM32F091xB/xC I2C implementation
I2C features(1)
1. X = supported.
I2C1 I2C2
7-bit addressing mode X X
10-bit addressing mode X X
Standard mode (up to 100 kbit/s) X X
Fast mode (up to 400 kbit/s) X X
Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive I/Os X X
Independent clock X -
SMBus X -
Wakeup from STOP X -
Table 10. STM32F091xB/xC USART implementation
USART modes/features(1) USART1
USART2
USART3 USART4
USART5
USART6
USART7
USART8
Hardware flow control for modem X X -
Continuous communication using DMA X X X
Multiprocessor communication X X X
Synchronous mode X X X
Smartcard mode X - -
Functional overview STM32F091xB STM32F091xC
26/128 DocID026284 Rev 4
3.18 Serial peripheral interface (SPI) / Inter-integrated sound
interface (I2S)
Two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-duplex
and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
Two standard I2S interfaces (multiplexed with SPI1 and SPI2 respectively) supporting four
different audio standards can operate as master or slave at half-duplex communication
mode. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data
resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to
192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master
mode, they can output a clock for an external audio component at 256 times the sampling
frequency.
Single-wire half-duplex communication X X X
IrDA SIR ENDEC block X - -
LIN mode X - -
Dual clock domain and wakeup from Stop mode X - -
Receiver timeout interrupt X - -
Modbus communication X - -
Auto baud rate detection X - -
Driver Enable X X X
1. X = supported.
Table 10. STM32F091xB/xC USART implementation (continued)
USART modes/features(1) USART1
USART2
USART3 USART4
USART5
USART6
USART7
USART8
Table 11. STM32F091xB/xC SPI/I2S implementation
SPI features(1)
1. X = supported.
SPI1 and SPI2
Hardware CRC calculation X
Rx/Tx FIFO X
NSS pulse mode X
I2S mode X
TI mode X
DocID026284 Rev 4 27/128
STM32F091xB STM32F091xC Functional overview
27
3.19 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC
controller to wakeup the MCU from Stop mode on data reception.
3.20 Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.21 Clock recovery system (CRS)
The STM32F091xB/xC embeds a special block which allows automatic trimming of the
internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device
operational range. This automatic trimming is based on the external synchronization signal,
which could be either derived from LSE oscillator, from an external signal on CRS_SYNC
pin or generated by user software. For faster lock-in during startup it is also possible to
combine automatic trimming with manual trimming action.
3.22 Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.