HS-0548RH, HS-0549RH TM Data Sheet August 2001 Radiation Hardened Single 8/Differential 4 Channel CMOS Analog Multiplexers with Active Overvoltage Protection tle 8R S9R iadle ifn4 nOS ti- The HS-0548RH and HS-0549RH are radiation hardened analog multiplexers with Active Overvoltage Protection and guaranteed rON matching. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70V peak-to-peak levels with 15V supplies and digital inputs will sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur: each input presents 1k of resistance under this condition. These features make the HS-0548RH and HS-0549RH ideal for use in systems where the analog inputs originate from external equipment or separately powered circuitry. Both devices are fabricated with 44V dielectrically isolated CMOS technology. The HS-0548 is an 8 channel device and the HS-0549 is a 4 channel differential version. If input overvoltage protection is not needed, the HS-0508 and HS-509 multiplexers are recommended. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95694. A "hot-link" is provided on our homepage for downloading. http://www.intersil.com ve r- Ordering Information ec) tho 5962D9569401VEA HS1-0548RH-Q -55 to 125 5962D9569401VEC HS1B-0548RH-Q -55 to 125 5962D9569402VEA HS1-0549RH-Q -55 to 125 5962D9569402VEC HS1B-0549RH-Q -55 to 125 ORDERING NUMBER INTERNAL MKT. NUMBER TEMP. RANGE (oC) 3543.4 Features * Electrically Screened to SMD # 5962-95694 * QML Qualified per MIL-PRF-38535 Requirements * Gamma Dose . . . . . . . . . . . . . . . . . . . . . . 1 x 104RAD(Si) * No Latch-Up * No Channel Interaction During Overvoltage * Guaranteed rON Matching * Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V * Break-Before-Make Switching * Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . 15V * Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0s Applications * Data Acquisition Systems * Control Systems * Telemetry Pinouts HS-0548RH GDIP1-T16 (CERDIP) OR CDIP2-T16 (SBDIP) TOP VIEW AO 1 16 A1 ENABLE 2 15 A2 -VSUPPLY 3 14 GND IN 1 4 13 +VSUPPLY IN 2 5 12 IN 5 IN 3 6 11 IN 6 IN 4 7 10 IN 7 8 9 IN 8 OUT HS-0549RH GDIP1-T16 (CERDIP) OR CDIP2-T16 (SBDIP) TOP VIEW A0 1 ENABLE 2 -VSUPPLY 3 1 File Number 16 A1 15 GND 14 +VSUPPLY IN 1A 4 13 IN 1B IN 2A 5 12 IN 2B IN 3A 6 11 IN 3B IN 4A 7 10 IN 4B OUTA 8 9 OUT B CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2001, All Rights Reserved HS-0548RH, HS-0549RH Functional Diagrams HS-0548 HS-0549 IN1 IN1A OUT OUT A 1K 1K IN4A IN2 1K 1K DECODER/ DRIVER IN1B OUT B 1K 1K DECODER/ DRIVER IN4B IN8 OVERVOLTAGE CLAMP AND SIGNAL ISOLATION OVERVOLTAGE CLAMP AND SIGNAL ISOLATION LEVEL SHIFT 5V REF DIGITAL INPUT PROTECTION 5V REF LEVEL SHIFT DIGITAL INPUT PROTECTION A0 A1 A2 EN HS-0548 TRUTH TABLE A0 A1 EN HS-0549 TRUTH TABLE A2 A1 A0 EN "ON" CHANNEL X X X L NONE L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 A1 A0 EN "ON" CHANNEL PAIR X X L NONE L L H 1 L H H 2 H L H 3 H H H 4 Switching Waveforms +10V OUTPUT A -8V VA A1 IN 2 THRU IN 7 A0 IN 8 EN GND -10V VAH VA INPUT 2V/DIV. IN 1 VAL = 0V 1/2VAH 10V A2 VAH = 4.0 ADDRESS DRIVE (VA) 10V OUT VOUT CH 1 ON OUTPUT A 5V/DIV. 10K tA CH 8 ON 200ns/DIV. FIGURE 1. ACCESS TIME 2 HS-0548RH, HS-0549RH Switching Waveforms (Continued) VAH = 4.0 0V 50% IN 1 A1 VA 50% +5V A2 ADDRESS DRIVE (VA) OUTPUT VA INPUT 2V/DIV. IN 2 THRU IN 7 A0 IN 8 EN OUT GND CH8 ON CH 1 ON VOUT VAH 1K OUTPUT 1V/DIV. tOPEN 100ns/DIV. FIGURE 2. BREAK-BEFORE-MAKE DELAY (tOPEN) VAH = 4.0 A2 50% +10V IN 1 ENABLE DRIVE 2V/DIV. A1 IN 2 THRU IN 8 0V A0 EN OUTPUT GND VA 90% OUT CH 1 ON 1K 90% tON(EN) OUTPUT 4V/DIV. CH 1 OFF tOFF (EN) 100ns/DIV. FIGURE 3. ENABLE DELAY tON(EN) , t OFF(EN) Schematic Diagrams TTL REFERENCE CIRCUIT V+ R10 R9 Q1 Q4 D3 LEVEL SHIFTER V+ P P P P OVERVOLTAGE PROTECTION R3 V+ ADD IN. D2 R1 N P P N R5 R7 LEVEL SHIFTED ADDRESS TO DECODE R6 R8 R4 N N N N 200 D1 N N V- V- FIGURE 4. ADDRESS INPUT BUFFER AND LEVEL SHIFTER 3 P R2 N P P P N LEVEL SHIFTED ADDRESS TO DECODE HS-0548RH, HS-0549RH Schematic Diagrams (Continued) FROM DECODE OVERVOLTAGE +V P P P P P P PROTECTION N V+ P N A0 OR A0 N Q5 N R11 N D6 D7 D4 D5 IN A1 OR A1 OUT N 1K N N Q6 A2 OR A2 N V ENABLE P VTO N-CHANNEL DEVICE OF THE SWITCH PAIR TO P-CHANNEL DEVICE OF THE SWITCH PAIR FROM DECODE FIGURE 5. ADDRESS DECODER FIGURE 6. MULTIPLEX SWITCH Burn-In/Life Test Circuits V1 F0 1 16 F1 1 16 F3 2 15 F2 2 15 3 14 4 13 5 12 6 11 7 10 8 9 V1 D1 C1 R1 3 14 4 13 5 12 6 11 7 10 8 9 V2 V2 D2 D1 C1 C2 R1 HS-0548RH DYNAMIC BURN-IN AND LIFE TEST CIRCUIT V1 V2 R1 C1 = = = = D1 F0 F1 F2 F3 = = = = = -15V maximum, -16V minimum +15V minimum, +16V maximum 10k 5% 1/4W C 2 = 0.01F minimum (per socket) or 0.1F minimum (per row) D 2 = 1N4002 (or equivalent) 100kHz 50% duty cycle; VIL = 0.8V Max; VIH = 4.0V Min. F0/2 F1/2 F2/2 4 V3 D2 HS-0548RH STATIC BURN-IN TEST CIRCUIT V1 V2 V3 R1 C1 = = = = = 5V minimum, 6V maximum -15V maximum, -16V minimum +15V minimum, +16V maximum 10k 5% 1/4W C2 = 0.01F minimum (per socket) or 0.1F minimum (per row) D1 = D2 = 1N4002 (or equivalent) C2 HS-0548RH, HS-0549RH Burn-In/Life Test Circuits F0 1 16 F2 2 15 3 14 4 13 5 12 6 V3 D1 (Continued) C1 F1 1 16 2 15 3 14 4 13 5 12 11 6 11 7 10 7 10 8 9 8 9 V2 D1 R1 V3 C1 D1 C1 = = = = = = +15.5V, .0.5V -15.5V, 0.5V 10k, 5% 0.01F minimum (per socket) 1N4002 or equivalent (per board) 100kHz, 10%; F1 = F0/2; F2 = F1/2 , 50% duty cycle, VIL = 0.8V Max; VIH = 4.0V Min V2 D1 R1 R1 R1 HS-0549RH STATIC BURN-IN TEST CIRCUIT HS-0549RH DYNAMIC BURN-IN AND LIFE TEST CIRCUIT V2 V3 R1 C1 D1 F0 V1 V1 V2 V3 R1 C1 D1 = = = = = = +5.5V, 0.5V +15.5V, 0.5V -15.5V, 0.5V 10k, 10% 0.01F minimum (per socket) 1N4002 or equivalent (per board) Irradiation Circuits +5V -15V +1V 1 16 2 15 3 14 4 13 5 6 +5V 1 16 2 15 3 14 4 13 12 5 12 11 6 11 7 10 7 10 8 9 8 9 +15V +1V R2 R1 -15V +1V R1 HS-0549RH HS-0548RH R1 = R2 = 10k 5% R1 = 10k 5% 5 +15V +1V C1 HS-0548RH, HS-0549RH Die Characteristics DIE DIMENSIONS: Substrate: 83 mils x 108 mils x 19 mils CMOS, DI INTERFACE MATERIALS: ASSEMBLY RELATED INFORMATION: Glassivation: Substrate Potential: Type: Nitride Thickness: 7kA 0.7kA Floating ADDITIONAL INFORMATION: Top Metallization: Worst Case Current Density: Type: Al Thickness: 16kA 2kA 1.4 x 105 A/cm 2 Transistor Count: 253 Metallization Mask Layout HS-0548RH IN 6 IN 7 IN 8 HS-0549RH OUT IN 4 IN3B IN4B OUT B IN 3 OUT A IN4A IN3A IN 5 IN 2 IN2B IN2A +V IN 1 IN1B IN1A GND -V A2 A1 A0 EN V- +V GND A1 A0 EN NOTE: Pad Numbers Correspond to DIP Pin Numbers Only All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6