1
TM
File Number 3543.4
HS-0548RH, HS-0549R H
Rad iat ion Har dened S ing le 8/Di f f erential 4
Channel CMOS Analog Multiplexers with
Active Overvoltage Protection
The HS-0548RH and HS-0549RH are radiation hardened
analog multiplexers wit h Active Overvoltage Protection and
guaranteed rON matching. Anal og input levels may greatly
exceed either power supply wi thout damaging the devi ce or
disturbing the si gnal path of other channels. Act ive
protection circuitry assur es that signal fidelity is maintained
even under fault conditions that would dest roy other
multiplexers. Analog inputs can with stand const ant 70V
peak-to-peak levels with ±15V su pplies a nd digit al i nputs will
sust ain con ti nuous fau lts up to 4V great er than ei ther s upply.
In addi tio n, sign al sourc es ar e protec ted fr om short ci rcui ting
should multiplexer supply loss occur: each input pr esents
1kΩ of resis tance under this conditi on. These f eatures make
the HS-0548RH and HS-0549RH idea l fo r use i n systems
where the analog inp uts originat e from external equipment
or separately powered circuitry. Bot h devices are fabri cated
with 44V dielectrical ly isolated CMOS technology. The
HS-0548 is an 8 channel device and the HS-0549 is a
4 channel differential version. If input overvoltage protection
is not needed, the HS-0508 and HS-509 mult iplexers are
recommended.
S pecificati ons for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus ( DSCC). The
SMD numbers list ed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95694. A “hot-link” is prov ided
on our homepage for downloading.
http://www.intersil.com
Features
• Electrically Screened t o SMD # 5962-95694
• QML Qualified per MIL-PRF-38535 Requirements
• Gamma Dose. . . . . . . . . . . . . . . . . . . . . . 1 x 104RAD(Si)
• No Latch-Up
• No Channel Interaction During Overvoltage
• Guaranteed rON Matchi ng
• Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V
• Break-Before-Make Swit ch ing
• Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0µs
Applications
• Data Acquisition Systems
• Control Systems
• Telemetry
Pinouts
HS-0548RH GDIP1-T16 (CERDIP)
OR CDIP2-T16 (S BDIP)
TOP VIEW
HS-0549RH GDIP1-T16 (CERDIP)
OR CDIP2-T16 (S BDIP)
TOP VIEW
Order ing Information
ORDERING NUMBER INTERNAL
MKT. NUMBER TEMP. RANGE
(oC)
5962D9569401VEA HS1-0548RH-Q -55 to 125
5962D9569401VEC HS 1B-0 548RH-Q -55 to 125
5962D9569402VEA HS1-0549RH-Q -55 to 125
5962D9569402VEC HS 1B-0 549RH-Q -55 to 125
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
AO
ENABLE
-VSUPPLY
IN 1
IN 2
IN 3
OUT
IN 4
A1
GND
+VSUPPLY
IN 5
IN 6
IN 7
IN 8
A2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
ENABLE
-VSUPPLY
IN 1A
IN 2A
IN 3A
OUTA
IN 4A
A1
+VSUPPLY
IN 1B
IN 2B
IN 3B
IN 4B
OUT B
GND
Data S heet Augus t 200 1
tle
-
8R
S-
9R
-
ia-
d-
le
if-
n-
4
n-
OS
-
ti-
-
ve
r-
-
ec-
)
tho
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-8 88-IN TERSIL o r 321- 724-7143 |Intersil and Design i s a trademar k of Inters il Ameri cas Inc .
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
2
Funct ional Diagrams
HS-0548 HS-0549
HS-0548 TRUTH TABL E
A2 A1 A0 EN “ON”
CHANNEL
X X X L NONE
LLLH 1
LLHH 2
LHLH 3
LHHH 4
HLLH 5
HLHH 6
HHLH 7
HHHH 8
† DI GIT AL INPUT PROTECTION
LEVEL
SHIFT
OVER-
CLAMP AND
SIGNAL
ISOLATION
VOLTAGE
DRIVER
DECODER/
1K
1K
1K
IN1
IN2
IN8
A0 A1A2 EN
OUT
††††
5V
REF
HS-0549 TRUTH TABL E
A1 A0 EN
“ON”
CHANNEL
PAIR
XXL NONE
LLH 1
LHH 2
HLH 3
HHH 4
IN1B
† DIGITAL INPUT PROTECTION
LEVEL
SHIFT
OVER-
CLAMP AND
SIGNAL
ISOLATION
VOLTAGE 5V
REF
1K
1K
1K
IN1A
IN4A
IN4B
A0 A1 EN
OUT A
DRIVER
DECODER/
OUT B
†† †
Switching Waveforms
FIGURE 1. ACCESS TIME
ADDRESS
D RI VE (VA)
OUTPUT A
VAH = 4.0
VAL = 0V
-10V
-8V
+10V
1/2VAH
tA
EN
VAH
OUT
IN 1
10K
IN 8
IN 2 THRU IN 7
GND
VA
A2
A1
A0
VOUT
10V
±
±10V
200ns/DIV.
VA INPUT
2V/DIV.
OUTPUT A
5V/DIV.
CH 8 ON
CH 1 ON
HS-0548RH, HS-0549RH
3
FIGURE 2. BREAK-BEFORE-MAKE DELAY (tOPEN)
FIGURE 3. E NABLE DELAY tON(EN), tOFF(EN)
Switching Waveforms (Continued)
50%
0V
ADDRESS
DRIVE (VA)
50%
VAH = 4.0
tOPEN
OUTPUT EN
VAH
OUT
+5V
IN 1
1K
IN 8
IN 2 THRU IN 7
GND
VA
A2
A1
A0 VOUT
VA INPUT
2V/DIV.
OUTPUT
1V/DIV.
100ns/DIV.
CH 1 ON CH8 ON
0V
OUTPUT
50%
90%
90%
VAH = 4.0
tON(EN) (EN)
tOFF
EN
+10V
IN 2 THRU IN 8
GND OUT
IN 1
1K
VA
A2
A1
A0
ENABLE
DRIVE
2V/DIV.
OUTPUT
4V/DIV.
100ns/DIV.
CH 1 OFF
CH 1 ON
Schematic Diagrams
FIGURE 4. ADDRESS INPUT BUFFER AND LEVEL SHIFTER
N
N
N
V-
N
P
V+
N
P
N
P
PP
LEVEL SHIFTER
ADD
IN. 200Ω
V-
V+
D1
D2
R1N
N
N
N
PPPP
R5
R6
R7
R8
R2
R3R4
OVERVOLTAGE
PROTECTION
V+
R10
R9
Q1
Q4
D3
TTL REFERENCE CIRCUIT
LEVEL
SHIFTED
ADDRESS
TO
DECODE
P
LEVEL
SHIFTED
ADDRESS
TO
DECODE
HS-0548RH, HS-0549RH
4
FIGURE 5. ADDRESS DECODER FIGURE 6. MULTIPLEX SWITCH
Schematic Diagrams (C ont inu ed)
+V
ENABLE
PPPPP P
NNN
N
N
N
A0 OR A0
A1 OR A1
A2 OR A2
TO P-CHANNEL DEVICE OF THE SWITCH PAIR
TO N-CHANNEL DEVICE OF THE SWITCH PAIR V-
D6D7D4D5
V
OUT
IN R11
1K
FROM
DECODE
FROM
DECODE OVERVOLTAGE PROTECTION
V+
Q6
N
N
N
Q5
P
P
Burn-In/Life Test Circuits
HS-0548RH
DYNAMIC BURN-IN AND LIFE TEST CIRCUIT
V1= -15V maximum, -16V minimum
V2= +15V minimum, +16V maximum
R1=10kΩ ±5% 1/4W
C1=C
2 = 0.01µF minimum (per socket) or 0.1µF mini mum
(per row)
D1=D
2 = 1N4002 (or equivalent)
F0= 10 0kHz 50% duty cycle; VIL = 0. 8V Max; VIH = 4.0V Min.
F1=F
0/2
F2=F
1/2
F3=F
2/2
HS-0548RH
STATIC BURN-IN TEST CIRCUIT
V1= 5V minimum , 6V maximum
V2= -15V maximum, -1 6V minimum
V3= +15V minimum, +16V maximum
R1=10kΩ ±5% 1/4W
C1=C
2 = 0.01µF minimum ( per socket) or 0.1µF minimum
(per row)
D1=D
2 = 1N4002 (or equivalent)
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
F0
F3
V1
D1C1
R1
F1
F2
V2
D2C2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V2
D1C1
R1
V1
V3
D2C2
HS-0548RH, HS-0549RH
5
HS-0549RH
DYNAMIC BURN-IN AND LIFE TEST CIRCUIT
V2=+15.5V, ±.0.5V
V3=-15.5V, ±0.5V
R1=10kΩ, ±5%
C1=0.01µF minimum (pe r socket )
D1= 1N4002 or equivalent (pe r board)
F0= 100kHz, ±10%; F1 = F0/2; F2 = F1/2,
50% duty cycle, V IL = 0.8V Max; VIH = 4.0V Min
HS-0549RH
STATIC BURN-IN TEST CIRCUIT
V1= +5.5V, ±0.5V
V2=+15.5V, ±0.5V
V3=-15.5V, ±0.5V
R1=10kΩ, ±10%
C1=0.01µF minimum (per socket )
D1= 1N4002 or equivalent (pe r board)
Burn-In/Life Test Circuits (Continued)
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
F0
F2
V2
V3
D1C1
R1R1
D1C1
F1
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V2
V3
D1C1
R1R1
D1C1
V1
Irradiatio n Circuits
HS-0549RH
R1 = R2 = 10kΩ ±5%
HS-0548RH
R1 = 10kΩ ±5%
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
+5V
-15V
+1V
R1R2
+1V
+15V 14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
+5V
-15V
+1V
R1
+1V
+15V
HS-0548RH, HS-0549RH
6
All Intersil semiconductor products are manufactured, assem bled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its s ubsidiaries for its use; nor for any infringements of patents or other rights of third parties w hich may result
from its use. No licens e is granted by implication or ot herwise under any patent or patent rights of Inte rsil or its s ubsidiaries.
For info rm ati on regar di ng In te rsi l Corpo rat i on an d it s pro du ct s, s ee we b site http://www.intersil.com
Die Char acteris tics
DIE DIMENSI ONS:
83 mils x 108 mil s x 19 mils
INTERFACE MATERI ALS:
Glassivation:
Type: Nitride
Thickness: 7kÅ ±0.7kÅ
Top Met all ization:
Type: Al
Thickness: 16kÅ ±2kÅ
Substrate:
CMOS, DI
ASSEMBLY RELATED INFORMATI ON:
Substrate Potential:
Floating
ADDITIONAL INFORMATI ON:
Wor st Case Current Density:
1.4 x 105 A/c m2
Transistor Count:
253
Metallization Mask Layout
HS-0548RH HS-0549RH
NOTE: Pad Numbers Correspond to DIP Pin Numbers Only
IN 6 IN 7 IN 8 OUT IN 4 IN 3
IN 5
+V
GND
IN 2
IN 1
-V
A2 A1 A0 EN
IN3B IN4B OUT B OUT A IN4 A IN3 A
IN2A
IN1A
V-
IN2B
IN1B
+V
GND A1 A0 EN
HS-0548RH, HS-0549RH
