Product Folder Order Now Technical Documents Support & Community Tools & Software SN65HVD82 SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 SN65HVD82 Robust RS-485 Transceiver 1 Features 3 Description * This device has robust drivers and receivers for demanding industrial applications. The bus pins are robust to ESD events, with high levels of protection to Human-Body Model, Air-Gap Discharge, and Contact Discharge specifications. 1 * * * * * Bus I/O Protection - 16-kV HBM Protection - 12-kV IEC61000-4-2 Contact Discharge - +4-kV IEC61000-4-4 Fast Transient Burst Industrial Temperature Range -40C to 85C Large Receiver Hysteresis (60 mV Typical) for Noise Rejection Low-Power Consumption - <1-A Standby Current - <1-mA Quiescent Current Signaling Rate Optimized for 250 kbps Create a Custom Design Using the SN65HVD82 With the WEBENCH(R) Power Designer Device Information(1) PART NUMBER 2 Applications * * * * The device combines a differential driver and a differential receiver, which operate from a single 5-V power supply. The driver differential outputs and the receiver differential inputs are connected internally to form a bus port suitable for half-duplex (two-wire bus) communication. The device features a wide commonmode voltage range making the device suitable for multi-point applications over long cable runs. The device is characterized from -40C to 85C. SN65HVD82 Electrical Meters Building Automation Industrial Networks Security Electronics PACKAGE SOIC (8) BODY SIZE (NOM) 4.90 mm x 3.91 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Logic Diagram (Positive Logic) R RE DE D 1 2 3 6 A 7 B 4 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN65HVD82 SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 3 3 4 4 5 6 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 7 Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagram ....................................... 10 8.3 Feature Description................................................. 10 8.4 Device Functional Modes........................................ 11 9 Application and Implementation ........................ 13 9.1 Application Information............................................ 13 9.2 Typical Application ................................................. 19 10 Power Supply Recommendations ..................... 21 11 Layout................................................................... 21 11.1 Layout Guidelines ................................................. 21 11.2 Layout Example .................................................... 22 12 Device and Documentation Support ................. 23 12.1 12.2 12.3 12.4 12.5 Device Support...................................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 23 23 13 Mechanical, Packaging, and Orderable Information ........................................................... 24 4 Revision History Changes from Revision A (July 2015) to Revision B Page * Added WEBENCH links to data sheet ................................................................................................................................... 1 * Changed pin 6 From: B To: A and pin 7 From: A To: B in Figure 19 .................................................................................. 15 Changes from Original (October 2012) to Revision A * 2 Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 SN65HVD82 www.ti.com SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 5 Pin Configuration and Functions D Package 16-Pin SOIC (Top View) R 1 8 VCC RE 2 7 B DE 3 6 A D 4 5 GND Pin Functions PIN NAME NO. TYPE DESCRIPTION A 6 Bus input/output Driver output or receiver input (complementary to B) B 7 Bus input/output Driver output or receiver input (complementary to A) D 4 Digital input Driver data input DE 3 Digital input Driver enable, active high GND 5 Reference potential R 1 RE 2 Digital input VCC 8 Supply Local device ground Digital output Receive data output Receiver enable, active low 4.5-V to 5.5-V supply 6 Specifications 6.1 Absolute Maximum Ratings (1) VCC TJ MIN MAX UNIT Supply voltage -0.5 7 V Voltage range at A or B Inputs -18 18 V V Input voltage range at any logic pin -0.3 5.7 Voltage input range, transient pulse, A and B, through 100 -100 100 V Receiver output current -24 24 mA 170 C Junction temperature Continuous total power dissipation TSTG (1) See Thermal Information Storage temperature -65 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 4000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 1500 Machine model (MM), JEDEC Standard 22 400 IEC 61000-4-2 ESD (Contact Discharge) Bus terminals and GND 12000 IEC 60749-26 ESD (Human Body Model) Bus terminals and GND 16000 IEC 61000-4-4 EMC (Fast Transient Burst Immunity) Bus terminals and GND 4000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 3 SN65HVD82 SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 www.ti.com 6.3 Recommended Operating Conditions MIN NOM MAX VCC Supply voltage 4.5 5 5.5 V VI Input voltage at any bus terminal (separately or common mode) (1) -7 12 V VIH High-level input voltage (D, DE and RE inputs) 2 VCC V VIL Low-level input voltage (D, DE and RE inputs) 0 0.8 V VID Differential input voltage (A and B inputs) -12 12 V Output current, Driver -60 60 mA 8 mA IO Output current, Receiver -8 RL Differential load resistance 54 CL Differential load capacitance 1/tUI Signaling rate TA Operating free-air temperature (see Application and Implementation section for thermal information) TJ Junction Temperature (1) UNIT 60 50 pF 250 kbps -40 85 C -40 150 C The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. 6.4 Thermal Information SN65HVD82 THERMAL METRIC (1) D (SOIC) UNIT 8 PINS RJA Junction-to-ambient thermal resistance 116.1 C/W RJC(top) Junction-to-case (top) thermal resistance 60.8 C/W RJB Junction-to-board thermal resistance 57.1 C/W JT Junction-to-top characterization parameter 13.9 C/W JB Junction-to-board characterization parameter 56.5 C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 SN65HVD82 www.ti.com SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 6.5 Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER |VOD| Driver differential output voltage magnitude TEST CONDITIONS MIN TYP MAX UNIT See Figure 5, RL = 60 , 375 on each output to -7 V to 12 V 1.5 RL = 54 (RS-485) 1.5 2 V 2 2.5 V RL = 100 (RS-422) See Figure 6 V |VOD| Change in magnitude of driver differential output voltage RL = 54 , CL = 50 pF See Figure 6 -0.2 0 0.2 V VOC(SS) Steady-state common-mode output voltage Center of two 27- load resistors See Figure 6 1 VCC/2 3 V VOC Change in differential driver output common-mode voltage -0.2 0 0.2 V VOC(PP) Peak-to-peak driver common-mode output voltage COD Differential output capacitance VIT+ Positive-going receiver differential input voltage threshold VIT- Negative-going receiver differential input voltage threshold VHYS Receiver differential input voltage threshold hysteresis (VIT+ - VIT-) VOH Receiver high-level output voltage IOH = -8 mA VOL Receiver low-level output voltage IOL = 8 mA II Driver input, driver enable, and receiver enable input current IOZ Receiver output high-impedance current VO = 0 V or VCC, RE at VCC IOS Driver short-circuit output current | IOS | with VA or VB from -7 V to +12 V II Bus input current (disabled driver) VCC = 4.5 to 5.5 V or VCC = 0 V, DE at 0 V ICC mV 8 pF (1) -70 -200 -150 40 60 4 VCC-0.3 See 0.2 -2 -10 VI = 12 V 75 VI = -7 V -100 -20 mV (1) mV See mV V 0.4 V 2 A 10 A 150 mA 125 -40 Driver and Receiver enabled DE = VCC, RE=GND, No load 900 Driver enabled, receiver disabled DE = VCC, RE = VCC, No load 650 Driver disabled, receiver enabled DE = GND, RE = GND, No load 650 Driver and receiver disabled DE = GND, D=GND, RE = VCC, No load Supply current (quiescent) Supply current (dynamic) (1) 850 A A 0.4 2 See Typical Characteristics Under any specific conditions, VIT+ is assured to be at least VHYS higher than VIT-. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 5 SN65HVD82 SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 www.ti.com 6.6 Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 400 700 1200 ns 90 700 1000 ns 25 200 ns DRIVER tr, tf Driver differential output rise/fall time tPHL, tPLH Driver propagation delay tSK(P) Driver pulse skew, |tPHL - tPLH| tPHZ, tPLZ Driver disable time tPZH, tPZL RL = 54 , CL = 50 pF, See Figure 7 Receiver enabled Driver enable time See Figure 8 and Figure 9 Receiver disabled 50 500 ns 500 1000 ns 3 9 s 18 30 ns 85 195 ns RECEIVER tr, tf Receiver output rise/fall time tPHL, tPLH Receiver propagation delay time tSK(P) Receiver pulse skew, |tPHL - tPLH| tPLZ, tPHZ Receiver disable time tPZL(1), tPZH(1) tPZL(2), tPZH(2) CL = 15 pF, See Figure 10 Receiver enable time 1 15 ns 50 500 ns Driver enabled, See Figure 11 20 130 ns Driver disabled, See Figure 12 2 8 s 6.7 Typical Characteristics 5 715 VOL Driver Rise and Fall Time (ns) Driver Output Voltage (V) 4.5 4 3.5 3 2.5 2 1.5 VOH 1 705 695 685 675 0.5 0 665 0 10 20 30 40 50 60 70 Driver Output Current (mA) 80 -40 -20 0 20 40 60 80 100 Temperature (C) C003 Figure 1. Driver Output Voltage vs Driver Output Current 120 C002 Figure 2. Driver Rise and Fall Time vs Temperature 6 25 VIT+(VIC=12V) 5 Receiver Output [R] (V) Supply Current (mA) 20 15 10 5 4 3 VIT-(VIC=12V) VIT-(VIC=-7V) Series6 VIT-(VIC=0V) 2 1 0 0 50 100 150 200 250 Signaling Rate (kbps) 300 0 -250 -230 -210 -190 -170 -150 Differential Input Voltage [VID] (mV) C001 Figure 3. Supply Current vs Signaling Rate 6 VIT+(VIC=-7V) VIT+(VIC=0V) -130 -110 C004 Figure 4. Receiver Output vs Differential Input Voltage Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 SN65HVD82 www.ti.com SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 7 Parameter Measurement Information Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec, output impedance 50 . 375 W 1% VCC DE 0 V or 3 V D A VOD 60 W 1% B + _ -7 V < V(test) < 12 V 375 W 1% S0301-01 Figure 5. Measurement of Driver Differential Output Voltage With Common-Mode Load A 0 V or 3 V A VA B VB RL/2 D VOD VOC(PP) B RL/2 CL DVOC(SS) VOC VOC S0302-01 Figure 6. Measurement of Driver Differential and Common-Mode Output With RS-485 Load 50% 50% A : | : B | Copyright (c) 2016, Texas Instruments Incorporated Figure 7. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays 3V D DE Input Generator VI 50 W A 3V S1 B CL = 50 pF 20% CL Includes Fixture and Instrumentation Capacitance VO VI RL = 110 W 1% 50% 50% VO 0V 0.5 V tPZH VOH 90% 50% tPHZ 0V S0304-01 D at 3V to test non-inverting output, D at 0V to test inverting output. Figure 8. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down Load Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 7 SN65HVD82 SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 www.ti.com Parameter Measurement Information (continued) 3V A 3V VI VO 50% 50% 0V B DE Input Generator S1 D 3V RL = 110 W 1% tPZL tPLZ CL = 50 pF 20% VI 50 W 3V CL Includes Fixture and Instrumentation Capacitance VO 50% 10% VOL S0305-01 D at 0V to test non-inverting output, D at 3V to test inverting output. Figure 9. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load 3V A Input Generator R VI 50 W 1.5 V VI VO 50% 0V B 0V 50% tPLH CL = 15 pF 20% RE tPHL 90% 90% VO 50% 10% CL Includes Fixture and Instrumentation Capacitance 50% 10% tr VOH VOL tf S0306-01 Figure 10. Measurement of Receiver Output Rise and Fall Times and Propagation Delays 3V VCC DE A 0 V or 3 V D RE Input Generator VI 1 kW 1% R VO B S1 CL = 15 pF 20% CL Includes Fixture and Instrumentation Capacitance 50 W 3V VI 50% 50% 0V tPZH(1) tPHZ VOH 90% VO 50% D at 3 V S1 to GND 0V tPZL(1) tPLZ VCC VO 50% D at 0 V S1 to VCC 10% VOL S0307-01 Figure 11. Measurement of Receiver Enable/Disable Times With Driver Enabled 8 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 SN65HVD82 www.ti.com SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 Parameter Measurement Information (continued) VCC A 0 V or 1.5 V R VO S1 B 1.5 V or 0 V RE Input Generator VI 1 kW 1% CL = 15 pF 20% CL Includes Fixture and Instrumentation Capacitance 50 W 3V VI 50% 0V tPZH(2) VOH VO A at 1.5 V B at 0 V S1 to GND 50% GND tPZL(2) VCC VO 50% VOL A at 0 V B at 1.5 V S1 to VCC S0308-01 Figure 12. Measurement of Receiver Enable Times With Driver Disabled Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 9 SN65HVD82 SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 www.ti.com 8 Detailed Description 8.1 Overview The SN65HVD82 device is a half-duplex RS-485 transceiver suitable for data transmission at rates up to 250 kbps over controlled-impedance transmission media (such as twisted-pair cabling). The device features a high level of internal transient protection, making it able to withstand up ESD strikes up to 12 kV (per IEC 61000-4-2) and EFT transients up to 4 kV (per IEC 61000-4-4) without incurring damage. Up to 256 units of SN65HVD82 may share a common RS-485 bus due to the device's low bus input currents. The device also features a low standby current consumption of 400 nA (typical). 8.2 Functional Block Diagram R RE DE D 1 2 3 6 A 7 B 4 Figure 13. Logic Diagram (Positive Logic) 8.3 Feature Description 8.3.1 Receiver Failsafe The differential receiver is failsafe to invalid bus states caused by: * open bus conditions such as a disconnected connector * shorted bus conditions such as cable damage shorting the twisted-pair together, or * idle bus conditions that occur when no driver on the bus is actively driving In any of these cases, the differential receiver will output a failsafe logic High state so that the output of the receiver is not indeterminate. Receiver failsafe is accomplished by offsetting the receiver thresholds so that the "input indeterminate" range does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than 200 mV, and must output a Low when the VID is more negative than -200 mV. The receiver parameters which determine the failsafe performance are VIT+ and VIT- and VHYS. As seen in the Electrical Characteristics table, differential signals more negative than -200 mV will always cause a Low receiver output. Similarly, differential signals more positive than 200 mV will always cause a High receiver output. When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output will be High. Only when the differential input is more negative than VIT- will the receiver output transition to a Low state. So the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value VHYS (the separation between VIT+ and VIT- ) as well as the value of VIT+. Signals which transition from positive to negative (or from negative to positive) will transition only once, ensuring no spurious bits. 8.3.2 Low-Power Standby Mode When both the driver and receiver are disabled (DE transitions to a low state and RE transitions to a high state) the device enters standby mode. If the enable inputs are in this state for a brief time (e.g. less than 100 ns), the device does not enter standby mode. This prevents inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this state a sufficient duration (e.g. for 300 ns or more), the device is assured to be in standby mode. In this low-power standby mode, most internal circuitry is powered down, and the steady-state supply current is typically less than 400 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active. 10 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 SN65HVD82 www.ti.com SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 8.4 Device Functional Modes Table 1. Driver Function Table INPUT ENABLE D DE A OUTPUTS H H H L Actively drive bus High L H L H Actively drive bus Low X L Z Z Driver disabled X OPEN Z Z Driver disabled by default OPEN H H L Actively drive bus High by default B Table 2. Receiver Function Table DIFFERENTIAL INPUT ENABLE OUTPUT VID = VA - VB RE R VIT+ < VID L H Receive valid bus High VIT- < VID < VIT+ L ? Indeterminate bus state VID < VIT- L L Receive valid bus Low X H Z Receiver disabled X OPEN Z Receiver disabled by default Open-circuit bus L H Fail-safe high output Short-circuit bus L H Fail-safe high output Idle (terminated) bus L H Fail-safe high output Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 11 SN65HVD82 SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 www.ti.com D and RE Inputs DE Input VCC VCC 100 kW 1 kW 1 kW Input Input 100 kW 9V 9V A Input B Input VCC VCC 16 V 16 V R3 R1 R1 R3 Input Input 16 V R2 16 V A and B Outputs R2 R Output VCC VCC 16 V 5W Output Output 9V 16 V Figure 14. Equivalent Input and Output Schematic Diagrams 12 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 SN65HVD82 www.ti.com SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Device Configuration The SN65HVD82 is a half-duplex, 250-kbps, RS-485 transceiver operating from a single 5-V supply. The driver and receiver enable pins allow for the configuration of different operating modes. R R R R R R RE A RE A RE A DE B DE B DE B D D D a) Independent driver and receiver enable signals D D b) Combined enable signals for use as directional control pin D c) Receiver always on Copyright (c) 2016, Texas Instruments Incorporated Figure 15. SN65HVD82 Transceiver Configurations Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be turned on and off individually. While this configuration requires two control lines, it allows for selective listening into the bus traffic, whether the driver is transmitting data or not. Combining the enable signals simplifies the interface to the controller by forming a single, direction-control signal. Thus, when the direction-control line is high, the transceiver is configured as a driver, while for a low the device operates as a receiver. Tying the receiver-enable to ground and controlling only the driver-enable input, also uses one control line only. In this configuration a node not only receives the data from the bus, but also the data it sends and thus can verify that the correct data have been transmitted. 9.1.2 Bus - Design An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer cable length. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 13 SN65HVD82 SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 www.ti.com Application Information (continued) R R RE B DE D R A R A RT RT D A B R A R RE DE D DE D B R D RE B D D R RE DE D Copyright (c) 2016, Texas Instruments Incorporated Figure 16. Typical RS-485 Network with SN65HVD82 Transceivers Common cables used are unshielded twisted pair (UTP), such as low-cost CAT-5 cable with Z0 = 100 , and proper RS-485 cable with Z0 = 120 . Line measurements have shown that making RT by up to 10% larger than Z0 improves signal quality. Typical cable sizes are AWG 22 and AWG 24. The theoretical maximum bus length is assumed with 4000 ft or 1200 m, and represents the length of an AWG 24 cable whose cable resistance approaches the value of the termination resistance, thus reducing the bus signal by half or 6 dB. The theoretical maximum number of bus nodes is determined by the ratio of the RS-485 specified maximum of 32 unit loads (UL) and the actual unit load of the applied transceiver. For example, the SN65HVD82 is a 1/8 UL transceiver. Dividing 32 UL by 1/8 UL yields 256 transceivers that can be connected to one bus. 9.1.3 Cable-Length Versus Data Rate There is an inverse relationship between data rate and cable length. That is, the higher the data rate the shorter the cable and conversely the lower the data rate the longer the cable. While most RS-485 systems utilize data rates between 10 kbps and 100 kbps, applications such as e-metering often operate at rates of up to 250 kbps even at distances of 4000 feet and above. This is possible by allowing for small signal jitter of up to 5 or 10%. 10000 CABLE LENGTH - ft 5,10,20 % Jitter 1000 Conservative Characteristics 100 10 100 1k 10k 100k 1M 10M 100M DATA RATE - bps Figure 17. Cable Length vs Data Rate Characteristic 14 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 SN65HVD82 www.ti.com SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 Application Information (continued) 9.1.4 Stub - Length When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as the stub, should be as short as possible. The reason for this is that a stub presents a non-terminated piece of bus line which can introduce reflections if too long. As a rule of thumb the electrical length or round-trip delay of a stub should be less than one tenth of the driver's rise time, thus leading to a maximum physical stub length of: LStub 0.1 x tr x v x c, with tr as the driver's 10/90 rise time, c as the speed of light (3 x 108 m/s or 9.8 x 108 ft/s), and v as the signal velocity of the cable (v = 78%) or trace (v = 45%) as a factor of c. Thus, for the SN65HVD82 with a minimum rise time of 400 ns the maximum cable stub length yields LStub 0.1 x 400 x 10-9 x 3 108 x 0.78 = 9.4 m or 30.6 ft. LS A B R D R RE DE D Figure 18. Stub Length 9.1.5 3-V to 5-V Interface Interfacing the SN65HVD82 to a 3-V controller is easy. Because the 5-V logic inputs of the transceiver accept 3V input signals they can be directly connected to the controller I/O. The 5-V receiver output, R, however must be level-shifted via a Schottky diode and a 10-kV resistor to connect to the controller input. When R is high, the diode is reverse biased and the controller supply potential lies at the controller input. When R is low, the diode is forward biased and conducts. In this case only the diode forward voltage of 0.2 V lies at the controller input. 3.3 V 10 k 5V BAS70 MCU RxD 1 RCV 2 RE DRV 3 DE TxD 4 D R VCC 8 B 7 A 6 GND 5 HVD82 0.1 F Copyright (c) 2017, Texas Instruments Incorporated Figure 19. 3 V - 5 V Interface 9.1.6 Noise Immunity The input sensitivity of a standard RS-485 transceiver is 200 mV. When the differential input voltage, VID, is greater than +200 mV, the receiver output turns high, for VID 200 mV the receiver outputs low. Bus voltages in between these levels can cause the receiver output to go high, or low, or even toggle between logic states. Small bus voltages however occur every time during the bus access hand-off from one driver to the next as the lowimpedance termination resistors reduce the bus voltage to zero. To prevent receiver output toggling during bus idling, and thus increasing noise immunity, external bias resistors must be applied to create a bus voltage that is greater than the input sensitivity plus any expected differential noise. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 15 SN65HVD82 SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 www.ti.com Application Information (continued) R VHYS-min 60mV -80 -20 VID - mV 80 0 Vnoise-max = 160mVpp Figure 20. SN65HVD82 Noise Immunity The SN65HVD82 transceiver circumvents idle-bus and differential noise issues by providing a positive input threshold of -20 mV and a typical hysteresis of 60 mV. In the case of an idle-bus condition therefore, a differential noise voltage of up to 160 mVPP can be present without causing the receiver output to change states from high to low. This increased noise immunity eliminates the need for idle-bus failsafe bias resistors and allows for long haul data transmissions in noisy environment. 9.1.7 Transient Protection The bus terminals of the SN65HVD82 transceiver family possess on-chip ESD protection against 15 kV human body model (HBM) and 12 kV IEC61000-4-2 contact discharge. As stated in the IEC 61000-4-2 standard, contact discharge is the preferred test method; although IEC air-gap testing is less repeatable than contact testing, air discharge protection levels are inferred from the contact discharge test results. The IEC-ESD test is far more severe than the HBM-ESD test. The 50% higher charge capacitance, CS, and 78% lower discharge resistance, RD of the IEC-model produce significantly higher discharge currents than the HBM-model. RD 50M (1M) High-Voltage Pulse Generator 330 (1.5k) CS 150pF (100pF) Device Under Test Current - A RC 40 35 30 25 20 15 10 5 0 10kV IEC 10kV HBM 0 50 100 150 200 250 300 Time - ns Copyright (c) 2016, Texas Instruments Incorporated Figure 21. HBM and IEC-ESD Models and Currents in Comparison EFTs are usually caused by relay contact bounce or the interruption of inductive loads, while surge transients often results from lightning strikes (direct strike or induced voltages and currents due to an indirect strike), or the switching of power systems including load changes and short circuits switching. These transients are often encountered in industrial environments, such as factory automation and power-grid systems. 16 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 SN65HVD82 www.ti.com SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 Application Information (continued) 22 20 18 16 14 12 10 8 6 4 2 0 Pulse Power - MW Pulse Power - kW Figure 22 compares the pulse-power of the EFT and surge transients with the power caused by an IEC-ESD transient. As can be seen the tiny blue blip in the bottom left corner of the left diagram represents the power of a 10-kV ESD transient, which already dwarfs against the significantly higher EFT power spike and certainly against the 500-V surge transient. This type of transient power is well representative for factory environments in industrial and process automation. The right diagram compares the enormous power of a 6-kV surge transient, which more likely occurs in e-metering applications of power generating and power grid systems, with the aforementioned 500-V surge transient. Note that the unit of the pulse-power changes from kW to MW, thus making the power of the 500-V surge transient almost dropping off the scale. 0.5kV Surge 4kV EFT 10kV ESD 0 5 10 15 20 25 30 35 40 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 6kV Surge 0.5kV Surge 0 5 10 15 20 25 30 35 40 Time - s Time - s Figure 22. Power Comparison of ESD, EFT, and Surge Transients In the case of surge transients, their long pulse duration and slowly decreasing pulse power signifies high energy content. The electrical energy of a transient that is dumped onto the transceiver's internal protections cells is converted into thermal energy, or heat that literally fries the protection cells, thus destroying the transceiver. Figure 23 showcases the large differences in transient energies for single ESD, EFT, and surge transients as well as for an EFT pulse train, commonly applied during compliance testing. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 17 SN65HVD82 SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 www.ti.com Application Information (continued) 1000 100 Surge Pulse Energy - Joule 10 1 EFT Pulse Train 0.1 0.01 EFT 10-3 10-4 ESD 10-5 10-6 0.5 1 2 4 6 8 10 15 Peak Pulse Voltage - kV Figure 23. Comparison of Transient Energies Figure 24 suggests two circuit designs providing protection against surge transients. Table 3 presents the associated bill of material. Table 3. Bill of Materials DEVICE FUNCTION ORDER NUMBER MANUFACTURER XCVR 3.3V, 250kbps RS-485 Transceiver SN65HVD82D TI R1,R2 10, Pulse-Proof Thick-Film Resistor CRCW0603010RJNEAHP Vishay TVS Bidirectional 400W Transient Suppressor CDSOT23-SM712 Bourns TBU1,TBU2 Bidirectional. 200mA Transient Blocking Unit TBU-CA-065-200-WH Bourns MOV1,MOV2 200V, Metal-Oxide Varistor MOV-10D201K Bourns Vcc Vcc Vcc 10k 1 R 2 RE DIR 3 DE TxD 4 D RxD MCU Vcc 8 B 7 A 6 GND 5 XCVR 0.1 F Vcc 10k R1 1 R 2 RE DIR 3 DE TxD 4 D RxD TVS MCU 8 B 7 A 6 GND 5 XCVR R2 10k Vcc 0.1 F R1 TBU1 MOV1 TVS MOV2 R2 10k TBU2 Copyright (c) 2016, Texas Instruments Incorporated Figure 24. Transient Protection Against ESD, EFT, and Surge Transients Both circuits are designed for 10-kV ESD and 4-kV EFT transient protection. The left however provides surge protection of 500-V transients only, while the right protection circuits can withstand 5-kV surge transients. 18 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 SN65HVD82 www.ti.com SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 9.2 Typical Application 0.1F 2 Vcc D2 3 1:2.2 MBR0520L SN6501 GND D1 10F N IN OUT 5 TPS76350 10F 0.1F 3 1 4,5 L1 1 EN GND 2 5VISO 10F MBR0520L ISO-BARRIER 3.3V 0.1F PSU 0.1F PE 0.1F 4.7k PE 2 DVcc 5 6 XOUT XIN UCA0RXD P3.0 MSP430 F2132 DVss P3.1 UCA0TXD 16 11 12 15 4 1 16 Vcc1 Vcc2 7 10 EN1 ISO7241 EN2 6 11 OUTD IND 3 14 INA OUTA 4 13 INB OUTB 5 12 INC OUTC GND1 GND2 2,8 0.1F 4.7k 1 R 8 Vcc 7 B RE SN65 3 DE HVD82 6 A 4 D GND2 2 5 R1 R2 TVS 9,15 R HV Short thick Earth wire or Chassis Protective Earth Ground, Equipment Safety Ground Floating RS-485 Common C HV PE island R1,R2, TVS: see Table 1 RHV = 1M, 2kV high-voltage resistor, TT electronics, HVC 2010 1M0 G T3 CHV = 4.7nF, 2kV high-voltage capacitor, NOVACAP, 1812 B 472 K 202 N T Figure 25. Isolated Bus Node With Transient Protection 9.2.1 Design Requirements The following list outlines sample design requirements for the typical application example found in Figure 25 * RS-485-compliant bus interface (needs differential signal amplitude of at least 1.5 V under fully-loaded conditions - essentially, maximum number of nodes connected and with dual 120- termination). * Galvanic isolation of both signal and power supply lines. * Able to withstand ESD transients up to 10 kV (per IEC 61000-4-2) and EFTs up to 4 kV (per IEC 61000-4-4). * Full control of data flow on bus in order to prevent contention (for half-duplex communication). 9.2.2 Detailed Design Procedure 9.2.2.1 Custom Design With WEBENCH(R) Tools Click here to create a custom design using the SN65HVD82 device with the WEBENCH(R) Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: * Run electrical simulations to see important waveforms and circuit performance * Run thermal simulations to understand board thermal performance Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 19 SN65HVD82 SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 www.ti.com Typical Application (continued) * * Export customized schematic and layout into popular CAD formats Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 9.2.2.2 Isolated Bus Node Design Many RS-485 networks use isolated bus nodes to prevent the creation of unintended ground loops and their disruptive impact on signal integrity. An isolated bus node typically includes a micro controller that connects to the bus transceiver via a multi-channel, digital isolator (Figure 25). Power isolation is accomplished using the push-pull transformer driver SN6501 and a low-cost LDO, TPS76350 Signal isolation utilizes the quadruple digital isolator ISO7241. Notice that both enable inputs, EN1 and EN2, are pulled-up via 4.7-k resistors to limit their input currents during transient events. While the transient protection is similar to the one in Figure 24 (left circuit), an additional high-voltage capacitor is used to divert transient energy from the floating RS-485 common further towards Protective Earth (PE) ground. This is necessary as noise transients on the bus are usually referred to Earth potential. RVH refers to a high-voltage resistor, and in some applications even a varistor. This resistance is applied to prevent charging of the floating ground to dangerous potentials during normal operation. Occasionally varistors are used instead of resistors in order to rapidly discharge CHV, if it is expected that fast transients might charge CHV to high-potentials. Note that the PE island represents a copper island on the PCB for the provision of a short, thick Earth wire connecting this island to PE ground at the entrance of the power supply unit (PSU). In equipment designs using a chassis, the PE connection is usually provided through the chassis itself. Typically the PE conductor is tied to the chassis at one end while the high-voltage components, CHV and RHV, are connecting to the chassis at the other end. 9.2.3 Application Curve Figure 26. SN65GVD82 D Input (Top), Differential Output (Middle), and R Output (Bottom), 250 kbps Operation, PRBS Data Pattern 20 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 SN65HVD82 www.ti.com SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 10 Power Supply Recommendations To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and inductance of the PCB power planes. 11 Layout 11.1 Layout Guidelines 11.1.1 Design and Layout Considerations For Transient Protection On-chip IEC-ESD protection is good for laboratory and portable equipment but never sufficient for EFT and surge transients occurring in industrial environments. Therefore robust and reliable bus node design requires the use of external transient protection devices. Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, highfrequency layout techniques must be applied during PCB design. In order for your PCB design to be successful start with the design of the protection circuit in mind. 1. Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your board. 2. Use Vcc and ground planes to provide low-inductance. Note that high-frequency currents follow the path of least inductance and not the path of least impedance. 3. Design the protection components into the direction of the signal path. Do not force the transients currents to divert from the signal path to reach the protection device. 4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the Vcc-pins of transceiver, UART, controller ICs on the board. 5. Use at least two vias for Vcc and ground connections of bypass capacitors and protection devices to minimize effective via-inductance. 6. Use 1-k to 10-k pullup or pulldown resistors for enable lines to limit noise currents in theses lines during transient events. 7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping current into the transceiver and prevent it from latching up. 8. While pure TVS protection is sufficient for surge transients up to 1kV, higher transients require metal-oxide varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient blocking units (TBUs) that limit transient current to some 200 mA. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 21 SN65HVD82 SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 www.ti.com 11.2 Layout Example 5 Via to ground C R 6 Via to VCC 4 R 1 MCU R 7 5 R 6 JMP R TVS R SN65HVD82 5 Figure 27. SN65HVD82 Layout Example 22 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 SN65HVD82 www.ti.com SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.1.2 Custom Design With WEBENCH(R) Tools Click here to create a custom design using the SN65HVD82 device with the WEBENCH(R) Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: * Run electrical simulations to see important waveforms and circuit performance * Run thermal simulations to understand board thermal performance * Export customized schematic and layout into popular CAD formats * Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 23 SN65HVD82 SLLSED6B - OCTOBER 2012 - REVISED NOVEMBER 2017 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 24 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: SN65HVD82 PACKAGE OPTION ADDENDUM www.ti.com 23-Oct-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) SN65HVD82D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HVD82 SN65HVD82DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HVD82 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 23-Oct-2017 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65HVD82DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.5 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65HVD82DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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