PI74AVC+16836 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 2.5V 20-Bit Universal Bus Driver with 3-State Outputs Features Description * PI74AVC+16836 is designed for low-voltage operation, VCC = 1.65V to 3.6V Pericom Semiconductor's 20-bit PI74AVC+16836 universal bus driver is designed for 1.65V to 3.6V VCC operation. Data flow from A to Y is controlled by the Output Enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is LOW. When LE is HIGH, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is HIGH, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is HIGH, the outputs are in the highimpedance state, but all the inputs are enabled and data is capable of being stored in the register. * True 24mA Balanced Drive @ 3.3V * IOFF supports partial power-down operation * 3.6V I/O Tolerant inputs and outputs * Meets PC133 SDRAM Registered DIMM Specifications * All outputs contain a patented DDC (Dynamic Drive Control) circuit that reduces noise without degrading propagation delay To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. * Industrial operation: -40C to +85C * Packaging (Pb-free & Green available): - 56-pin 240-mil wide plastic TSSOP (A) Block Diagram OE CLK LE A1 1 56 29 55 1D C1 2 Y1 V CLK TO 19 OTHER CHANNELS 1 08-0291 PS8511E 10/17/08 PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 Truth Table(1) Pin Description Pin Name Inputs De s cription OE Output Enable Input (Active LOW) OE LE CLK A Outputs Y LE Latch Enable (Active LOW) H X X X Z CLK Clock Input L L X L L A Data Input L L X H H Y Data Output L H L L GND Ground L H H H Vcc Power L H L or H X Yo(2) Notes: 1 H = High Signal Level L = Low Signal Level Z = High Impedance = Transition LOW-to-HIGH X = Irrelevant 2. Output level before the indicated steady-state input conditions were established. Pin Configuration OE Y1 1 2 56 55 CLK A1 Y2 GND Y3 3 4 5 54 53 52 A2 GND A3 Y4 VCC 51 50 49 A4 VCC Y5 6 7 8 A5 Y6 Y7 9 10 48 47 A6 A7 GND Y8 Y9 11 12 13 46 45 44 GND A8 A9 Y10 Y11 Y12 14 15 16 43 42 41 A10 A11 A12 Y13 GND 17 18 40 39 A13 GND Y14 Y15 Y16 19 20 21 38 37 36 A14 A15 A16 VCC 22 23 24 35 VCC Y17 Y18 34 33 A17 A18 GND Y19 25 26 32 31 GND A19 Y20 NC 27 28 30 29 A20 LE 2 08-0291 PS8511E 10/17/08 PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC ............................................ -0.5V to +4.6V Input voltage range, VI .................................................. -0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ................... -0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ....................................... -0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ................................................... -50mA Output clamp current, IOK (VO <0) .............................................. -50mA Continuous output current, IO ................................................... 50mA Continuous current through each VCC or GND ........................ 100mA Package thermal impedance, JA(3): ........................................... 64C/W Storage Temperature range, Tstg .................................... -65C to 150C Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. Output positive-voltage rating may be exceeded up to 4.6V maximum if the output current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51. Recommended Operating Conditions(1) VCC VIH Supply Voltage High- level Input Voltage M in. M ax. Operating 1.65 3. 6 Data retention only 1.2 VCC = 1.2V VCC VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VIL Low- level Input Voltage 0.65 x VCC 1.7 2 VCC = 1.2V Gnd Input Voltage VO Output Voltage IOH High- level output current IOL Low- level output current tv Input transition rise or fall rate TA V 0.35 x VCC VCC = 1.65V to 1.95V VI Units VCC = 2.3V to 2.7V 0.7 VCC = 3V to 3.6V 0.8 0 3. 6 Active State 0 VCC 3- State 0 3.6 VCC = 1.65V to 1.95V -6 VCC = 2.3V to 2.7V -12 VCC = 3V to 3.6V -24 mA VCC = 1.65V to 1.95V 6 VCC = 2.3V to 2.7V 12 VCC = 3V to 3.6V 24 VCC = 1.65V to 3.6V 5 ns/V 85 C Operating free- air temperature -40 Notes: 1. All unused inputs must be held at VCC or GND to ensure proper device operation. 3 08-0291 PS8511E 10/17/08 PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 DC Electrical Characteristics (Over the Operating Range, TA = -40C +85C) Parame te rs VO H VO L II IO F F IO Z IC C CI Control Inputs Te s t Conditions (1) IO H = -100A IO H = -6mA VIH = 1.07V VIH = 1.7V IO H = -12mA VIH = 2V IO H = -24mA IO L = 100A IO L = 6mA VIH = 0.57V IO L = 12mA VIH = 0.7V IO L = 24mA VIH = 0.8V VI = VC C or GND VI or VO = 3.6V VI = VC C or GND VO = VC C or GND IO = 0 VI = VC C or GND Data Inputs CO Outputs VO = VC C or GND VCC 1.65V to 3.6V 1.65V 2 . 3V 3V 1.65V to 3.6V 1.65V 2.3V 3V 3 . 6V 0 3.6V 3.6 V 2 . 5V 3.3V 2.5V 3.3V 2.5V 3.3V M in. VC C -0.2V 1.2 1.75 2. 0 M a x. Units V 0 .2 0.45 0.55 0 .8 2. 5 10 10 40 4 4 6 6 8 8 A pF Notes: 1. Typical values are measured at TA = 25C. 4 08-0291 PS8511E 10/17/08 PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 Timing Requirements (Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4) VCC = 1.2V VCC = 1.5V 0.1V VCC = 1.8V 0.15V VCC = 2.5V 0.2V VCC = 3.3V 0.3V Typical M in. M ax. M in. M in. M in. M a x. M a x. fclock Clock Frequency tw Pulse Duration LE Low 3.3 3.3 3. 3 CLK High or Low 3.3 3.3 3. 3 tsu Setup Time th Hold Time 15 0 Data before CLK Data before LE Data after LE 1.6 1.4 1. 0 1.0 CLK High 1.7 1. 6 1.2 1.2 1.0 CLK Low 1.2 1. 0 1. 4 1.2 1.0 1.0 1. 0 1.0 0 .8 0. 6 1.0 1. 0 1.0 0 .8 0. 6 CLK High or Low Units 15 0 MHz 15 0 2.2 Data after CLK M ax. ns Switching Characteristics (Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4) Parame te rs From (Input) To (Output) VCC = 1.2V Typical VCC = 1.5V 0.1V M in. M a x. fmax tpd VCC = 1.8V 0.15V M in. M ax. VCC = 2.5V 0.2V M in. 15 0 M a x. 150 VCC = 3.3V 0.3V M in. M ax. 150 MHz A 5.4 4.0 1.0 4.5 0.8 3 .0 0.7 2.4 LE 6.8 4.6 1.0 4.5 0.8 3 .3 0.7 2.5 7.8 5.0 1.0 4.5 0.8 3 .3 0.7 2.5 CLK Y Units ten OE 6.2 5. 0 1. 5 4.5 1.0 4 .5 1.0 4.0 tdis OE 5.5 4.5 1. 5 4.5 1.0 4 .5 1.0 4.0 ns Operating Characteristics, TA= 25C Te s t Conditions Parame te rs Cpd Power Dissipation Capacitance Outputs Enabled Outputs Disabled CL = 0pF, f = 10 MHz 5 08-0291 VCC = 1.8V 0.1V VCC = 2.5V 0.2V VCC = 3.3V 0.3V Typical Typical Typical 45 48 52 23 25 28 Units pF PS8511E 10/17/08 PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 PARAMETER MEASUREMENT INFORMATION VCC = 1.2V and 1.5V 0.1V Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input tW VCC/2 VCC 0V tsu VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) Input VCC/2 VCC VCC/2 tPLH Output VCC/2 VCC/2 VCC/2 tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V tPHL VCC VOH VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Voltage Waveforms Propagation Delay Times VCC/2 0V tPLZ VCC VCC/2 VOL +0.1V VOL tPHZ VCC/2 VOH -0.1V VOH 0V Voltage Waveforms Enable and Disable Times Figure 1. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. * All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. * The outputs are measured one at a time with one transition per measurement. * tPLZ and tPHZ are the same as tdis * tPZL and tPZH are the same as ten * tPLH and tPHL are the same as tpd 6 08-0291 PS8511E 10/17/08 PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 PARAMETER MEASUREMENT INFORMATION VCC = 1.8V 0.15V 1 k 30 1 k Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) Input VCC/2 VCC VCC/2 tPLH Output VCC/2 VCC/2 VCC/2 tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V tPHL VCC VOH VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Voltage Waveforms Propagation Delay Times VCC/2 0V tPLZ VCC VCC/2 VOL +0.1V 0.15V VOL tPHZ VCC/2 VOH -0.1V 0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 2. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. * All input impulses are supplied by generators having these characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. * The outputs are measured one at a time with one transition per measurement. * tPLZ and tPHZ are the same as tdis * tPZL and tPZH are the same as ten * tPLH and tPHL are the same as tpd 7 08-0291 PS8511E 10/17/08 PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 PARAMETER MEASUREMENT INFORMATION VCC = 2.5V 0.2V 500 30 500 Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input tW VCC/2 VCC 0V tsu VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) Input VCC/2 VCC VCC/2 tPLH Output VCC/2 VCC/2 VCC/2 tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V tPHL VCC VOH VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Voltage Waveforms Propagation Delay Times VCC/2 0V tPLZ VCC VCC/2 VOL +0.15V VOL tPHZ VCC/2 VOH -0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 3. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. * All input impulses are supplied by generators having these characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. * The outputs are measured one at a time with one transition per measurement. * tPLZ and tPHZ are the same as tdis * tPZL and tPZH are the same as ten * tPLH and tPHL are the same as tpd 8 08-0291 PS8511E 10/17/08 PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 PARAMETER MEASUREMENT INFORMATION VCC = 3.3V 0.3V S1 500 2 From Output Under Test CL = 30 15pF 2xVCC Open GND 500 2 (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input tW VCC/2 VCC 0V tsu VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) Input Output VCC/2 VCC/2 VCC/2 tPLH tPHL VCC /2 VCC VCC/2 tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V VOH VCC/2 VCC Output Waveform 2 S1 at GND (see Note B) VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPLZ VCC VCC/2 VOL +0.1V 0.3V VOL tPHZ VCC/2 VOH -0.1V 0.3V VOH 0V Voltage Waveforms Enable and Disable Times Figure 4. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. * All input impulses are supplied by generators having these characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. * The outputs are measured one at a time with one transition per measurement. * tPLZ and tPHZ are the same as tdis * tPZL and tPZH are the same as ten * tPLH and tPHL are the same as tpd 9 08-0291 PS8511E 10/17/08 PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 Packaging Mechanical: 56-pin TSSOP (A) Ordering Information Ordering Code PI74AVC+16836AE Package Code Package Type A Pb-free & Green, 56-pin, 240-mil wide plastic TSSOP Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ * E = Pb-free & Green * Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 10 08-0291 PS8511E 10/17/08