PI74AVC+16836AE - Pericom - Datasheet.Directory

1PS8511E 10/17/08

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1

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PI74AVC+16836

2.5V 20-Bit Universal Bus

Driver with 3-State Outputs

Block Diagram

Features

•PI74AVC+16836 is designed for low-voltage operation,

VCC = 1.65V to 3.6V

•True ±24mA Balanced Drive @ 3.3V

•IOFF supports partial power-down operation

•3.6V I/O Tolerant inputs and outputs

•Meets PC133 SDRAM Registered DIMM Specifications

•All outputs contain a patented DDC

(Dynamic Drive Control) circuit that reduces noise without

degrading propagation delay

•Industrial operation: –40°C to +85°C

•Packaging (Pb-free & Green available):

– 56-pin 240-mil wide plastic TSSOP (A)

Description

Pericom Semiconductor’s 20-bit PI74AVC+16836 universal bus

driver is designed for 1.65V to 3.6V VCC operation.

Data flow from A to Y is controlled by the Output Enable (OE) input.

The device operates in the transparent mode when the latch-enable

(LE) input is LOW. When LE is HIGH, the A data is latched if the

clock (CLK) input is held at a high or low logic level. If LE is HIGH,

the A data is stored in the latch/flip-flop on the low-to-high

transition of CLK. When OE is HIGH, the outputs are in the high-

impedance state, but all the inputs are enabled and data is capable

of being stored in the register.

To ensure the high-impedance state during power up or power

down, OE should be tied to VCC through a pullup resistor; the

minimum value of the resistor is determined by the current-sinking

capability of the driver.

OE

CLK

LE

A1

1

56

29

55

1D

CLK

C1 Y1

2

V

TO 19 OTHER CHANNELS

08-0291

PI74AVC+16836

2.5V 20-Bit Universal Bus

Driver with 3-State Outputs

2PS8511E 10/17/08

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Truth Table(1)

Pin Configuration

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

25

26

27

28

32

31

30

29

CLK

A1

A2

GND

A3

A4

V

CC

A5

A6

A7

GND

A8

A9

A10

A11

A12

A13

GND

A14

A15

A16

V

CC

A17

A18

GND

A19

A20

LE

OE

Y1

Y2

GND

Y3

Y4

V

CC

Y5

Y6

Y7

GND

Y8

Y9

Y10

Y11

Y12

Y13

GND

Y14

Y15

Y16

V

CC

Y17

Y18

GND

Y19

Y20

NC

Pin Description

Notes:

1 H =High Signal Level

L =Low Signal Level

Z =High Impedance

↑=Transition LOW-to-HIGH

X =Irrelevant

2. Output level before the indicated steady-state input

conditions were established.

stupnI stuptuO Y

EOELKLCA

HXXXZ

LLXLL

LLXHH

LH↑LL

LH↑HH

LH HroLXoY

)2(

emaNniPnoitpircseD

EO)WOLevitcA(tupnIelbanEtuptuO

EL)WOLevitcA(elbanEhctaL

KLCtupnIkcolC

AtupnIataD

YtuptuOataD

DNGdnuorG

ccVrewoP

08-0291

PI74AVC+16836

2.5V 20-Bit Universal Bus

Driver with 3-State Outputs

3PS8511E 10/17/08

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Recommended Operating Conditions(1)

Notes:

1. All unused inputs must be held at VCC or GND to ensure proper device operation.

.niM.xaMstinU

V

CC

egatloVylppuS gnitarepO 56.16.3

V

ylnonoitneterataD 2.1

V

HI

egatloVtupnIlevel-hgiHV

CC

V2.1=V

CC

V

CC

V59.1otV56.1=x56.0V

CC

V

CC

V7.2otV3.2=7.1

V

CC

V6.3otV3=2

V

LI

egatloVtupnIlevel-woLV

CC

V2.1=dnG

V

CC

V59.1otV56.1= x53.0V

CC

V

CC

V7.2otV3.2=7.0

V

CC

V6.3otV3=8.0

V

I

egatloVtupnI 06.3

V

O

egatloVtuptuO etatSevitcA 0V

CC

etatS-306.3

I

HO

tnerructuptuolevel-hgiH V

CC

V59.1otV56.1= 6–

Am

V

CC

V7.2otV3.2= 21–

V

CC

V6.3otV3=42–

I

LO

tnerructuptuolevel-woL V

CC

V59.1otV56.1= 6

V

CC

V7.2otV3.2= 21

V

CC

V6.3otV3=42

ΔtΔetarllafroesirnoitisnarttupnIv V

CC

V6.3otV56.1=5V/sn

T

A

erutarepmetria-eerfgnitarepO 04–58C°

Maximum Ratings

(Above which useful life may be impaired. For user guidelines, not tested.)

Supply voltage range, VCC ............................................ –0.5V to +4.6V

Input voltage range, VI.................................................. –0.5V to +4.6V

Voltage range applied to any output in the

high-impedance or power-off state, VO(1) ................... –0.5V to +4.6V

Voltage range applied to any output in the

high or low state, VO(1,2) .......................................–0.5V to VCC +0.5V

Input clamp current, IIK (VI <0) ................................................... –50mA

Output clamp current, IOK (VO <0) .............................................. –50mA

Continuous output current, IO................................................... ±50mA

Continuous current through each VCC or GND........................ ±100mA

Package thermal impedance, θJA(3): ........................................... 64°C/W

Storage Temperature range, Tstg .................................... –65°C to 150°C

Notes:

Stresses greater than those listed under MAXIMUM

RATINGS may cause permanent damage to the device.

This is a stress rating only and functional operation of the

device at these or any other conditions above those

indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

1. Input & output negative-voltage ratings may be exceeded

if the input and output curent rating are observed.

2. Output positive-voltage rating may be exceeded up to 4.6V

maximum if the output current rating is observed.

3. The package thermal impedance is calculated in accor-

dance with JESD 51.

08-0291

PI74AVC+16836

2.5V 20-Bit Universal Bus

Driver with 3-State Outputs

4PS8511E 10/17/08

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sretemaraPsnoitidnoCtseT

)1(

V

CC

.niM.xaMstinU

V

HO

I

HO

001–= μAV6.3otV56.1 V

CC

V2.0–

V

I

HO

6–=m VA

HI

V70.1=V56.12.1

I

HO

21–=m VA

HI

V7.1=V3.257.1

I

HO

42–=m VA

HI

V2=V30.2

V

LO

I

LO

001= μAV6.3otV56.12.0

I

LO

6=m VA

HI

V75.0=V56.154.0

I

LO

21=m VA

HI

V7.0= V3.255.0

I

LO

42=m VA

HI

V8.0=V38.0

I

V

I

V=

CC

DNGroV6.35.2±

μA

I

FFO

V

I

Vro

O

V6.3=001±

I

ZO

V

I

V=

CC

DNGro V6.301±

I

CC

V

O

V=

CC

IDNGro

O

0=V6.304

C

I

stupnIlortnoCV

I

V=

CC

DNGroV5.24

Fp

V3.34

stupnIataDV5.26

V3.36

C

O

stuptuOV

O

V=

CC

DNGroV5.28

V3.38

Notes:

1. Typical values are measured at TA = 25°C.

DC Electrical Characteristics (Over the Operating Range, TA = –40°C +85°C)

08-0291

PI74AVC+16836

2.5V 20-Bit Universal Bus

Driver with 3-State Outputs

5PS8511E 10/17/08

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sretemaraP morF )tupnI( oT )tuptuO(

V

CC

V2.1= V

CC

V5.1= V1.0± V

CC

V8.1= V51.0± V

CC

V5.2= V2.0± V

CC

V3.3= V3.0±

stinUlacipyT.niM.xaM.niM.xaM.niM.xaM.niM.xaM

f

xam

051051051zHM

t

dp

A

Y

4.50.40.15.48.00.37.04.2

sn

EL8.66.40.15.48.03.37.05.2

KLC8.70.50.15.48.03.37.05.2

t

ne

EO2.60.55.15.40.15.40.10.4

t

sid

EO5.55.45.15.40.15.40.10.4

Timing Requirements

(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)

Switching Characteristics

(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)

Operating Characteristics, TA= 25°C

sretemaraP

tseT snoitidnoC

V

CC

V8.1= V1.0± V

CC

V5.2= V2.0± V

CC

V3.3= V3.0±

stinU

lacipyTlacipyTlacipyT

C

dp

ecnaticapaCnoitapissiDrewoP delbanEstuptuO C

L

,Fp0= zHM01=f 548425Fp

delbasiDstuptuO325282

V

CC

V2.1= V

CC

V5.1= V1.0± V

CC

V8.1= V51.0± V

CC

V5.2= V2.0± V

CC

V3.3= V3.0±

stinUlacipyT.niM.xaM.niM.xaM.niM.xaM.niM.xaM

f

kcolc

ycneuqerFkcolC051051051zHM

t

w

esluP noitaruD woLEL3.33.33.3

sn

woLrohgiHKLC3.33.33.3

t

us

puteS

emiT KLCerofebataD ↑2.26.14.10.10.1

ELerofebataD ↑hgiHKLC7.16.12.12.10.1

woLKLC2.10.14.12.10.1

t

h

dloH

emiT KLCretfaataD ↑0.10.10.18.06.0

ELretfaataD ↑hgiHKLC woLro 0.10.10.18.06.0

08-0291

PI74AVC+16836

2.5V 20-Bit Universal Bus

Driver with 3-State Outputs

6PS8511E 10/17/08

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PARAMETER MEASUREMENT INFORMATION

VCC = 1.2V and 1.5V ±0.1V

Load Circuit

Voltage Waveforms

Propagation Delay Times Voltage Waveforms

Enable and Disable Times

Voltage Waveforms

Pulse Duration

tseT1S

t

dp

t

ZLP

t/

LZP

t

ZHP

t/

HZP

nepO Vx2

CC

DNG

Notes:

A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

• All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.

• The outputs are measured one at a time with one transition per measurement.

• tPLZ and tPHZ are the same as t dis

• tPZL and tPZH are the same as ten

• tPLH and tPHL are the same as tpd

Figure 1. Load Circuit and Voltage Waveforms

tPZL

Output

Control

(Low Level

Enabling) 0V

VCC/2

tPLZ

tPHZ

VOL

VCC

0V

tPZH

+0.1V

–0.1V

Output

Waveform 1

S1 at 2 x VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOH VOH

VOL

VCC

Input

tPLH tPHL

0V

Output

VOH

VOL

VCC/2 VCC/2

VCC/2

VCC

/2

Input

t

W

VCC/2

VCC

VCC/2

0V

Data

Input

t

su

t

h

VCC/2 VCC

VCC/2

0V

VCC

0V

Timing

Input VCC/2

Voltage Waveforms

Setup and Hold Times

08-0291

PI74AVC+16836

2.5V 20-Bit Universal Bus

Driver with 3-State Outputs

7PS8511E 10/17/08

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PARAMETER MEASUREMENT INFORMATION

VCC = 1.8V ±0.15V

Load Circuit

Voltage Waveforms

Propagation Delay Times Voltage Waveforms

Enable and Disable Times

Voltage Waveforms

Pulse Duration

tseT1S

t

dp

t

ZLP

t/

LZP

t

ZHP

t/

HZP

nepO Vx2

CC

DNG

Notes:

A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

• All input impulses are supplied by generators having these characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.

• The outputs are measured one at a time with one transition per measurement.

• tPLZ and tPHZ are the same as tdis

• tPZL and tPZH are the same as ten

• tPLH and tPHL are the same as tpd

Figure 2. Load Circuit and Voltage Waveforms

tPZL

Output

Control

(Low Level

Enabling) 0V

VCC/2

tPLZ

tPHZ

VOL

VCC

0V

tPZH

+0.1V

–0.1V

Output

Waveform 1

S1 at 2 x VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOH VOH

VOL

VCC

Input

tPLH tPHL

0V

Output

VOH

VOL

VCC/2 VCC/2

VCC/2

VCC

/2

Input

t

W

V

CC

/2 V

CC

V

CC

/2

0V

Data

Input

t

su

t

h

VCC/2 VCC

VCC/2

0V

VCC

0V

Timing

Input VCC/2

Voltage Waveforms

Setup and Hold Times

1 kΩ

0.15V

30

08-0291

PI74AVC+16836

2.5V 20-Bit Universal Bus

Driver with 3-State Outputs

8PS8511E 10/17/08

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PARAMETER MEASUREMENT INFORMATION

VCC = 2.5V ±0.2V

Load Circuit

Voltage Waveforms

Propagation Delay Times Voltage Waveforms

Enable and Disable Times

Voltage Waveforms

Pulse Duration

tseT1S

t

dp

t

ZLP

t/

LZP

t

ZHP

t/

HZP

nepO Vx2

CC

DNG

Notes:

A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

• All input impulses are supplied by generators having these characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.

• The outputs are measured one at a time with one transition per measurement.

• tPLZ and t PHZ are the same as tdis

• tPZL and tPZH are the same as ten

• tPLH and tPHL are the same as tpd

Figure 3. Load Circuit and Voltage Waveforms

tPZL

Output

Control

(Low Level

Enabling) 0V

VCC/2

tPLZ

tPHZ

VOL

VCC

0V

tPZH

+0.15V

–0.15V

Output

Waveform 1

S1 at 2 x VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOH VOH

VOL

VCC

Input

tPLH tPHL

0V

Output

VOH

VOL

VCC/2 VCC/2

VCC/2

VCC

/2

Input

t

W

VCC/2

VCC

VCC/2

0V

Data

Input

t

su

t

h

V

CC

/2

V

CC

V

CC

/2

0V

V

CC

0V

Timing

Input V

CC

/2

Voltage Waveforms

Setup and Hold Times

500Ω

30

08-0291

PI74AVC+16836

2.5V 20-Bit Universal Bus

Driver with 3-State Outputs

9PS8511E 10/17/08

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PARAMETER MEASUREMENT INFORMATION

VCC = 3.3V ±0.3V

Load Circuit

Voltage Waveforms

Propagation Delay Times Voltage Waveforms

Enable and Disable Times

Voltage Waveforms

Pulse Duration

tseT1S

t

dp

t

ZLP

t/

LZP

t

ZHP

t/

HZP

nepO Vx2

CC

DNG

Notes:

A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

• All input impulses are supplied by generators having these characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.

• The outputs are measured one at a time with one transition per measurement.

• tPLZ and tPHZ are the same as tdis

• tPZL and tPZH are the same as ten

• tPLH and tPHL are the same as tpd

Figure 4. Load Circuit and Voltage Waveforms

2Ω

2xVCC

Open

GND

S1

From Output

Under Test

CL = 15pF

(See Note A)

tPZL

Output

Control

(Low Level

Enabling) 0V

VCC/2

tPLZ

tPHZ

VOL

VCC

0V

tPZH

+0.1V

–0.1V

Output

Waveform 1

S1 at 2 x VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOH VOH

VOL

VCC

Input

t

PLH

t

PHL

0V

Output

V

OH

V

OL

V

CC

/2 V

CC

/2

V

CC

/2

V

CC

VCC/2

Input

t

W

VCC/2

VCC

VCC/2

0V

Data

Input

t

su

t

h

V

CC

/2

V

CC

V

CC

/2

0V

V

CC

0V

Timing

Input V

CC

/2

Voltage Waveforms

Setup and Hold Times

500Ω

0.3V

30

08-0291

PI74AVC+16836

2.5V 20-Bit Universal Bus

Driver with 3-State Outputs

10 PS8511E 10/17/08

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Packaging Mechanical: 56-pin TSSOP (A)

Notes:

• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/

• E = Pb-free & Green

• Adding an X suffix = Tape/Reel

Ordering Information

Ordering Code Package Code Package Type

PI74AVC+16836AE A Pb-free & Green, 56-pin, 240-mil wide plastic TSSOP

Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com

08-0291