Features
• Single 2.7V − 3.6V Supply
• Serial Peripheral Interface (SPI) Compa tible
Supports SPI Modes 0 and 3
Supports Atmel RapidS Operation
Supports Dual-Input Program and Dual-Output Read
• Very Hig h Operating Frequencies
100MHz for RapidS
75MHz for SPI
Clock-to-Output (tV) of 5ns Maximum
• Flexib le, Optimized Erase Architecture for Code + Data Storage Ap p lications
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Er ase
• Individ u al Sector Protection with Global Protect/Unprotect Feature
128 Sectors of 64-Kbytes Each
• Hardware Controlled Locking o f Protected Sectors via Pin
• Sector Loc kdown
Make Any Co m b ination of 64-Kbyte Sectors Per ma n ent ly Read-Only
• 128-Byte Programmable OTP Security Register
• Flexib le Programming
Byte/Page Program (1- to 256-Bytes)
• Fast Program and Erase Times
1.0ms Typical Page Program (256-Bytes) Time
50ms Typical 4-Kbyte Block Erase Time
250ms Ty pical 32-Kbyte Block Erase Time
400ms Ty pical 64-Kbyte Block Erase Time
• Program and Er ase Suspend/Resu m e
• Automatic Checking and Reporting of Erase/ Program Failure s
• Software Controlled Reset
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation
5mA Active Read Current (Typical at 20MHz)
5µA Deep Power-Down Current (Typical)
• Endurance: 100,000 Program/Erase Cycles
• Data Retention: 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
16-Lead SOIC (300-mil wide)
8-Contact Very Thin DFN (6 x 8mm)
64-Mbit, 2.7V
Minimum Serial
Peripheral Interface
Serial Flash Memory
Atmel AT25DF641
3680F–DFLASH–4/10
WP
2 Atmel AT25DF641
3680F–DFLASH–4/10
Description
The Atmel® AT25DF641 is a serial interface Flash memory device designed for use in a wide variety of high-
volume consumer based applications in which program code is shadowed from Flash memory into embedded or
external R AM for execution. The flex ible erase archite cture of the AT25DF64 1, with its erase gran ularity as smal l
as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM
devices.
The physical sectoring and the erase block sizes of the AT25DF641 have been optimized to meet the needs of
today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the
memory space can be used much more efficiently. Because certain code modules and data storage segments
must resi de by th ems e lves in t he ir own pr otec te d s ectors, the wasted and un us e d m emory s p ac e t hat oc cur s with
large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory
space effici enc y allows add iti ona l code r out ines a nd da ta s torage s eg ments to b e adde d whi le s ti ll mai nta ini ng the
same overall device density.
The AT25DF641 also offers a sophisticated method for protecting individual sectors against erroneous or
malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a
system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the me mory
array s ecur ely pr otec ted . T his is us efu l i n ap pl icati ons wher e pro gr am c od e is pa tched or up dated on a s ubro ut ine
or module basis or in applications where data storage segments need to be modified without running the risk of
errant modifications to the program code segments. In addition to individual sector protection capabilities, the
AT25DF641 incorporates Global Protect and Global Unprotect features that allow the entire memory array to be
either protected or unprotected all at once. This reduces overhead during the manufacturing process since
sectors do not have to be unprotected one-by-one prior to initial programming.
To take code and data protection to the next level, the AT25DF641 incorporates a sector lockdown mechanism
that allows any combinat io n of i nd ividu al 64-K by te sectors to be loc ked d ow n and bec ome perm ane nt ly r ea d-only.
This addresses the need of certain secure applications that require portions of the Flash memory array to be
permanently protected against malicious attempts at altering program code, data modules, security information, or
encryption/decryption algorithms, keys, and routines. The device also contains a specialized OTP (One-Time
Programma ble) Security R egister t hat can be used for purpos es suc h as uniq ue devic e seria lizatio n, sys tem-level
Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in 3-volt systems, the AT25DF641 supports read, program, and erase operations
with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.
Atmel AT25DF641
3
3680F–DFLASH–4/10
1. Pin Descr iptions and Pi nout s
Table 1-1. Pin Descriptions
Symbol Name and Function Asserted
State Type
CHIP SELECT: Asserting the pin selects the device. When the pin is
deasserted, the device will be deselected and normally be placed in standby
mode (not Deep Power-Down mode), and the SO pin will be in a high-impedance
state. When the device is deselected, data will not be accepted on the SI pin.
A high-to-low transition on the pin is required to start an operation, and a low-
to-hi gh tr ansition is required to end an operation. When ending an internally self-
timed operation such as a program or erase cycle, the device will not enter the
standby mode until the completion of the operation.
Low Input
SCK
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to
control the flow of data to and from the device. Command, address, and input
data present on the SI pin is always latched in on the rising edge of SCK, while
output data on the SO pin is always clocked out on the falling edge of SCK.
− Input
SI (SIO)
SERIAL INPUT (SE RIAL INPUT/OUTPUT): The SI pin is used to shift data into
the device. The SI pin is used for all data input including command and address
sequences. Data on the SI pin is always latched in on the rising edge of SCK.
With the Dual-Output Read Array command, the SI pin becomes an output pin
(SIO) to allow two bits of data (on the SO and SIO pins) to be clocked out on
every falling edge of SCK. To maintain consistency with SPI nomenclature, the
SIO pin will be referenced as SI throughout the document with exception to
sections dealing with the Dual-Output Read Array command in which it will be
referenced as SIO.
Data present on the SI pin will be ignored whenever the device is deselected
( is deasserted).
− Input/Output
SO (SOI)
SERIAL OUTPUT (SERI AL OUTPUT/INPUT): The SO pin is used to shift data
out from the device. Data on the SO pin is always clocked out on the falling edge
of SCK.
With the Dual-Input Byte/Page Program command, the SO pin becomes an input
pin (SOI) to allow two bits of data (on the SOI and SI pins) to be clocked in on
every rising edge of SCK. To maintain consistency with SPI nomenclature, the
SOI pin will be referenced as SO throughout the document with exception to
sections dealing with the Dual-Input Byte/Page Program command in which it will
be referenced as SOI.
The SO pin will be in a high-impedance state whenever the device is deselected
( is deasserted).
− Output/Input
WRITE PROTECT: The pin controls the hardware locking feature of the
device. Please refer to “Protection Commands and Features” on page 21 for more
details on protection features and the WP pin.
The pin is internally pulled-high and may be left floating if hardware
controlled protection will not be used. However, it is recommended that the
pin also be externally connected to VCC whene ver pos si ble.
Low Input
CS
CS
CS
CS
CS
CS
WP
WP
WP
WP
4 Atmel AT25DF641
3680F–DFLASH–4/10
Table 1-1. Pin Descriptions (Continued)
Symbol Name and Function Asserted
State Type
HOLD: The pin is used to temporarily pau se seri al comm uni cati on wit hout
deselecting or resetting the device. While the pin is asserted, transitions on the
SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-
impedance stat e.
The pin must be asserted, and the SCK pin must be in the low state in order for a
Hold condition to start. A Hold condition pauses serial communication only and does not
have an effect on internally self-timed operations such as a program or erase cycle.
Please refer to “Hold” on page 45 for additional details on the Hold operation.
The pin is internal ly pul led-high and may be left floating if the Hold function will not
be used. However, it is recommended that the pin also be externally connected to
VCC whenever possible.
Low Input
VCC
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the
device.
Operations at invalid VCC voltages may produce spurious results and should not be
attempted.
− Power
GND GROUND: The ground reference for the power supply. GND should be connected to the
system ground. − Power
Figure 1-1. 8-VDFN (Top View) Figure 1-2. 16-SOIC (Top View)
1
2
3
4
8
7
6
5
CS
SO (SOI)
WP
GND
V
CC
HOLD
SCK
SI (SIO)
CS
HOLD
HOLD
HOLD
HOLD
HOLD
Atmel AT25DF641
5
3680F–DFLASH–4/10
2. Block Diagram
Figure 2-1. Block Diagram
CS
SCK
SO (SOI)
SI (SIO)
WP
HOLD
INTERFACE
CONTROL
AND
LOGIC
CONTROL AND
PROTECTION LOGIC
I/O BUFFERS
AND LATCHES
SRAM
DATA BUFFER
FLASH
MEMORY
ARRAY
Y-GATING
Y-DECODER
X-DECODER
ADDRESS LATCH
6 Atmel AT25DF641
3680F–DFLASH–4/10
3. Memory Array
To provide the greatest flexibility, the memory array of the Atmel® AT25DF641 can be erased in four levels of
granularity inclu ding a fu ll chip er ase. In a dditi on, the a rray has been d ivided i nto phys ical sec tors of u nifor m siz e,
of which each sector can be individually protected from program and erase operations. The size of the physical
sectors is opt imized f or bot h code and d ata stor age appl ications , allow ing bot h c ode and dat a segmen ts to reside
in their ow n isolated regions. The Memory Arch itecture Diagra m illustrates the break down of eac h erase lev el as
well as the breakdown of each physical sector.
Figure 3-1. Memory Architecture Diagram
Internal Sectoring for 64KB 32KB 4KB 1-256 Byte
Protection, Lockdown, Block Erase Block Erase Block Erase Page Program
and Suspend Functions (D8h Command) (52h Command) (20h Command) (02h Command)
4KB 7FFFFFh–7FF000h 256 Bytes 7FFFFFh– 7FFF00h
4KB 7FEFFFh–7FE000h 256 Bytes 7FFEFFh–7FFE00h
4KB 7FDFFFh –7FD000h 256 Bytes 7FFDFFh –7FFD00h
4KB 7FCFFFh–7FC000h 256 Bytes 7FFCFFh–7FFC00h
4KB 7FBFFFh– 7FB000h 256 Bytes 7FFBFFh–7FFB00h
4KB 7FAFFFh –7FA000h 256 Bytes 7FFAFFh–7FFA00h
4KB 7F9FFFh –7F9000h 256 Bytes 7FF9FFh –7FF900h
4KB 7F8FFFh –7F8000h 256 Bytes 7FF8FFh –7FF800h
4KB 7F7FFFh –7F7000h 256 Bytes 7FF7FFh –7FF700h
4KB 7F6FFFh –7F6000h 256 Bytes 7FF6FFh –7FF600h
4KB 7F5FFFh –7F5000h 256 Bytes 7FF5FFh –7FF500h
4KB 7F4FFFh –7F4000h 256 Bytes 7FF4FFh –7FF400h
4KB 7F3FFFh –7F3000h 256 Bytes 7FF3FFh –7FF300h
4KB 7F2FFFh –7F2000h 256 Bytes 7FF2FFh –7FF200h
4KB 7F1FFFh –7F1000h 256 Bytes 7FF1FFh –7FF100h
4KB 7F0FFFh –7F0000h256 Bytes 7FF0FFh – 7FF000h
4KB 7EFFFFh–7EF000h 256 Bytes 7FEFFFh–7FEF00h
4KB 7EEFFFh– 7EE000h 256 Bytes 7FEEFFh–7FEE00h
4KB 7EDFFFh–7ED000h 256 Bytes 7FEDFFh–7FED00h
4KB 7ECFFFh–7EC000h 256 Bytes 7FECFFh–7FEC00h
4KB 7EBFFFh– 7EB000h 256 Bytes 7FEBFFh–7FEB00h
4KB 7EAFFFh– 7EA000h 256 Bytes 7FEAFFh–7FEA00h
4KB 7E9FFFh–7E9000h 256 Bytes 7FE9FFh–7FE900h
4KB 7E8FFFh–7E8000h 256 Bytes 7FE8FFh–7FE800h
4KB 7E7FFFh–7E7000h
4KB 7E6FFFh–7E6000h
4KB 7E5FFFh–7E5000h
4KB 7E4FFFh–7E4000h 256 Bytes 0017FFh –001700h
4KB 7E3FFFh–7E3000h 256 Bytes 0016FFh –001600h
4KB 7E2FFFh–7E2000h 256 Bytes 0015FFh –001500h
4KB 7E1FFFh–7E1000h 256 Bytes 0014FFh –001400h
4KB 7E0FFFh–7E0000h 256 Bytes 0013FFh –001300h
256 Bytes 0012FFh –001200h
256 Bytes 0011FFh –001100h
256 Bytes 0010FFh –001000h
4KB 00FFFFh –00F000h 256 Bytes 000FFFh –000F00h
4KB 00EFFFh–00E000h 256 Bytes 000EFFh –000E00h
4KB 00DFFFh –00D000h 256 Bytes 000DFFh – 000D00h
4KB 00CFFFh –00C000h 256 Bytes 000CFFh –000C00h
4KB 00BFFFh – 00B000h 256 Bytes 000BFFh –000B00h
4KB 00AFFFh –00A000h 256 Bytes 000AFFh –000A00h
4KB 009FFFh –009000h 256 Bytes 0009FFh –000900h
4KB 008FFFh –008000h 256 Bytes 0008FFh –000800h
4KB 007FFFh –007000h 256 Bytes 0007FFh –000700h
4KB 006FFFh –006000h 256 Bytes 0006FFh –000600h
4KB 005FFFh –005000h 256 Bytes 0005FFh –000500h
4KB 004FFFh –004000h 256 Bytes 0004FFh –000400h
4KB 003FFFh –003000h 256 Bytes 0003FFh –000300h
4KB 002FFFh –002000h 256 Bytes 0002FFh –000200h
4KB 001FFFh –001000h 256 Bytes 0001FFh –000100h
4KB 000FFFh –000000h 256 Bytes 0000FFh –000000h
64KB
•••
64KB
32KB
32KB
•••
Range
•••
•••
Range
Page Program Detail
Page AddressBlock Address
64KB
64KB
(Sector 127)
Block Erase Detail
32KB
32KB
64KB
(Sector 0)
32KB
32KB
•••
64KB
(Sector 126)
Atmel AT25DF641
7
3680F–DFLASH–4/10
4. Device Operation
The Atmel® AT25DF641 is controlled by a set of instructions that are sent from a host controller, commonly
referred to as the SPI Master. The SPI Master communicates with the AT25DF641 via the SPI bus which is
comprised of four signal lines: Chip Select ( ), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The AT25DF 641 features a dual-input program mode in which the SO pin become an input. Similarly, the device
also features a dual-output read mode in which the SI pin becomes an output. In the Dual-Input Byte/Page
Program command description, the SO pin will be referred to as the SOI (Serial Output/Input) pin, and in the Dual-
Output Read Array command, the SI pin will be referenced as the SIO (Serial Input/Output) pin.
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in
respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus.
The AT25DF641 supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI
Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby
mode and not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of
SCK and always output on the falling edge of SCK.
Figure 4-1. SPI Mode 0 and 3
SO
SI
SCK
CS
MS B LS B
MS B LS B
5. Commands and Addressi ng
A valid instruction or operation must always be started by first asserting the pin. After the pin has been
asserted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode,
instruction dependent information such as address and data bytes would then be clocked out by the host
controller. All opcode, address, and data bytes are transferred with the most-significant bit (MSB) first. An
operation is ended by deasserting the pin.
Opcodes not supported by the AT25DF641 will be ignored by the device and no operation will be started. The
device will continue to igno re any data presented on the SI pin u ntil the start of the next operation ( pin being
deasserted and then reasserted). In addition, if the pin is deasserted before complete opcode and address
information is sent to the device, then no operat ion will be performed and the device will simply return to the idle
state and wait for the next operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-
A0. Since the upper address limit of the AT25DF641 memory array is 7FFFFFh, address bit A23 is always
ignored by the device.
CS
CS
CS
CS
CS
CS
8 Atmel AT25DF641
3680F–DFLASH–4/10
Table 5-1. Command Listing
Command Opcode Clock
Frequency Address
Bytes Dummy
Bytes Data
Bytes
Read Commands
Read Array
1Bh 0001 1011 Up to 75MHz 3 2 1+
0Bh 0000 1011 Up to 75MHz 3 1 1+
03h 0000 0011 Up to 45MHz 3 0 1+
Dual-Output Read Array 3Bh 0011 1011 Up to 55MHz 3 1 1+
Program and Erase Commands
Block Erase (4-KBytes) 20h 0010 0000 Up to 75MHz 3 0 0
Block Erase (32-KBytes) 52h 0101 0010 Up to 75MHz 3 0 0
Block Erase (64-KBytes) D8h 1101 1000 Up to 75MHz 3 0 0
Chip Erase 60h 0110 0000 Up to 75 MHz 0 0 0
C7h 1100 0111 Up to 75MHz 0 0 0
Byte/Page Program (1 to 256 Bytes) 02h 0000 001 0 Up to 75MHz 3 0 1+
Dual-Input Byte/Page Program (1 to 256 Bytes) A2h 1010 0010 Up to 75MHz 3 0 1+
Program/Erase Suspend B0h 1011 0000 Up to 75MHz 0 0 0
Program/Erase Resume D0h 1101 0000 Up to 75MHz 0 0 0
Protection Commands
Write Enable 06h 0000 0110 Up to 75MHz 0 0 0
Write Disable 04h 0000 0100 Up to 75MHz 0 0 0
Protect Sector 36h 0011 0110 Up to 75MHz 3 0 0
Unprotect Sector 39h 0011 1001 Up to 75MHz 3 0 0
Global Protect/Unprotect Use Write Status Register Byte 1 Command
Read Sector Protection Registers 3Ch 0011 1100 Up to 75MHz 3 0 1+
Security Commands
Sector Lockd own 33h 0011 0011 Up to 75MHz 3 0 1
Freeze Sector Lockdown State 34h 0011 010 0 Up to 75MHz 3 0 1
Read Sector Lockdown Registers 35h 0011 0101 Up to 75MHz 3 0 1+
Program OTP Security Register 9Bh 1001 1011 Up to 75MHz 3 0 1+
Read OTP Security Register 77h 0111 011 1 Up to 75MHz 3 2 1+
Status Register Commands
Read Status Register 05h 0000 0101 Up to 75MHz 0 0 1+
Write Status Register Byte 1 01h 0000 0001 Up to 75MHz 0 0 1
Write Status Register Byte 2 31h 0011 0001 Up to 75MHz 0 0 1
Miscellaneous Commands
Reset F0h 1111 0000 Up to 75MHz 0 0 1
Read Manufacturer and Device ID 9Fh 1001 1111 Up to 75MHz 0 0 1 to 4
Deep Power-Down B9h 1011 1001 Up to 75MHz 0 0 0
Resume from Deep Power-Down ABh 1010 1011 Up to 75MHz 0 0 0
Atmel AT25DF641
9
3680F–DFLASH–4/10
6. Read Commands
6.1. Read Array
The Read Array command can be used to sequentially read a continuous stream of data from the device by
simply pr oviding the c lock signa l once the in itial starting a ddress has b een specified . The devic e incorporat es an
internal address counter that automatically increments on every clock cycle.
Three opc odes (1 Bh , 0 Bh, and 03h) ca n be use d f or t he Re ad Ar ray c om man d. The us e of eac h opc od e d e pends
on the maximu m clock frequenc y that will be used to r ead data from the devic e. The 0Bh opcode can b e used at
any clock frequency up to the maximum specified by fCLK, and the 03h opcode can be used for lower frequency
read operations up to the maximum specified by fRDLF. The 1Bh opcode allows the highest read performance
possible and can be used at any clock frequency up to the maximum specified by fMAX; however, use of the 1Bh
opcode at clock frequencies above fCLK should be reserved to systems employing the RapidS protocol.
To perform t he Read Array operat ion, the pin must f irst be ass erted and the a ppr opriate opc ode (1 Bh, 0Bh , or
03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be
clocked in to spec ify the starting address location of the first byte to read within the memory array. Following the
three addres s by tes , a dd itional dummy bytes may need t o b e c l oc ked int o the d ev ice d epending on wh ic h opc ode
is used for the Rea d Array operation . If the 1Bh opcode is used, then two dummy bytes must be clock ed into the
device after the three address bytes. If the 0Bh opcode is used, then a single dummy byte must be clocked in
after the address bytes.
After the three address bytes (and t he dummy bytes or byte if using opco des 1Bh or 0Bh) have been c locked in,
additiona l clock cy cles will result in data be ing output on the SO pin. The d ata is always output with t he MSB of a
byte first. When the last byte (7FFFFFh) of the memory array has been read, the device will continue reading
back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of
the array to the beginning of the array.
Deassert ing the pin will ter minate the re ad operat ion and put t he SO pin i nto a high-i mpedance s tate. The
pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 6-1. Read Array - 1Bh Opcode
SO
SI
SCK
MS B MS B
2 310
0 0 011011
6 754 10 1198 12 39 42 43414037 3833 36353431 3229 30 44 47 484645 50 5149 52 55 565453
OP CODE
AAAA AAAAA
MS B
XXXXXXXX
MS B MS B
DDDDDDDD
DD
ADDR E S S B ITS A23-A0 DON'T C AR E
MS B
XXXXXXXX
DON'T C AR E
DATA BYTE 1
HIGH-IMP E DANC E
CS
CS
CS
CS
10 Atmel AT25DF641
3680F–DFLASH–4/10
Figure 6-2. Read Array - 0Bh Opcode
SO
SI
SCK
CS
MS B MS B
2 310
00001011
6 7
54 10 1198 12 39 42 43414037 3833 36353431 3229 30 44 47 484645
OP C O DE
AAAA AAAAA
MS B
XXXXXXXX
MS B MS B
D D D D D D D D
DD
ADDR E S S BITS A23-A0 DON'T C AR E
DATA BYTE 1
HIG H-IMP E DANC E
Figure 6-3. Read Array - 03h Opcode
SO
SI
SCK
MS B MS B
2 310
00000011
6 754 10 1198 12 37 3833 36353431 3229 30 39 40
OP C ODE
AAAA AAAAA
MS B MS B
DDDDDDDD
DD
ADDR E S S B IT S A23-A0
DAT A B Y T E 1
HIG H -IMP E DANC E
CS
Atmel AT25DF641
11
3680F–DFLASH–4/10
6.2. Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to
sequentia lly read a conti nuous s tream of data from th e device by s imply provid ing the clock s ignal once the ini tial
starting ad dress has been specified. Unlike the standard Read Array command, however, the Dual-Output Read
Array command allows two bits of data to be clocked out of the device on every clock cycle rather than just one.
The Dual-Out pu t Read Arr a y c ommand can b e us ed at any c lock fr equency up to t he max i mum s p ecifi ed by fRDDO.
To perfor m the Dual-O utpu t Rea d Arr ay oper ation, the pin m ust f irst be asser ted and the opco de of 3Bh must
be clocked into the device. After the opcode has bee n clocked in, the three address bytes must be clocked in to
specify th e star ting addres s locat ion o f the f irst by te to r ead with in the memory ar ray. Fol lowin g the t hree add ress
bytes, a single dummy byte must also be clocked into the device.
After the thr ee addr ess by t es and the d um my byte h av e been c locked in, add itional c lock cyc les will res ult i n data
being output o n both t he SO and SIO pins. T he data is always output with th e MSB of a byt e firs t, and the MS B is
always output on the SO pin. During the first clock cycle, bit seven of the first data byte will be output on the SO
pin wh ile bit six of the sam e data byte will be out put o n the SIO p in. Dur ing th e n ext clock cy cle, bits five and four
of the firs t data byt e will be outp ut on the SO and SIO pins, resp ectively . The se quence con tinues w ith each byte
of data being output after every four clock cycles. When the last byte (7FFFFFh) of the memory array has been
read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred
when wrapping around from the end of the array to the beginning of the array.
Deasserting the pin will terminate the read operation and put the SO and SIO pins into a high-impedance
state. The pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 6-4. Dual-Output Read Array
CS
SO
SI
SCK
MS B MS B
2 310
00111011
6 754 10 1198 12 39 42 43414037 3833 36353431 3229 30 44 47 484645
OP C O DE
AAAA AAAAA
MS B
XXXXXXXX
MS B MS B
ADDR E S S B ITS A23-A0 DO N'T C AR E
OUT P UT
DAT A B Y T E 1
OUT P UT
DAT A B Y T E 2
HIG H-IMP E DANC E
D
7
D
5
D
3
D
1
D
7
D
5
D
3
D
1
D
7
D
5
D
6
D
4
D
2
D
0
D
6
D
4
D
2
D
0
D
6
D
4
CS
CS
CS
12 Atmel AT25DF641
3680F–DFLASH–4/10
7. Progra m and Er ase Com m a nds
7.1. Byte/Page Program
The Byte/Page Program command allows anywhere from a single byte of data to 256-bytes of data to be
programmed into previously erased memory locations. An erased memory location is one that has all eight bits
set to the log ical “ 1” state ( a byte value of FFh) . B efore a Byte/ Page Progr am co mmand ca n b e start ed, the Write
Enable command must have been previously issued to the device (see “Write Enable” on page 21) to set the
Write Enable Latch (WEL) bit of the Status Register to a logical “1” state.
To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the
three address bytes denoting the first byte location of the memory array to begin programming at. After the
address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal
buffer.
If the star ting memory address deno ted by A2 3-A0 does not fa ll on an eve n 256-byte page boundary (A7-A 0 are
not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this
situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the
beginning of t he s a me p ag e. F or ex a mpl e, i f th e s tart ing ad dr es s denoted by A 23-A0 is 0 000FEh, an d thr e e by tes
of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and
0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page
(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In
addition, if more than 256-bytes of data are sent to the device, then only the last 256-bytes sent will be latched
into the internal buffer.
When the pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data
bytes sent to the device. If less than 256-bytes of data were sent to the device, then the remaining bytes within
the page w ill not be progra mmed a nd w ill r emain i n the er ase d state ( FFh). T he program ming of the data by tes is
internally self-timed and should take place in a time of tPP or tBP if only programming a single byte.
The three addr es s by tes an d at le as t on e c omp let e byt e of dat a must be cloc k ed int o th e devic e befor e the pin
is deasserted, and the pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
device w ill abort the opera tion and no data w ill be progr ammed into the mem ory array. In ad dition, if the ad dress
specified by A2 3-A0 po in ts to a me mor y l oc ati on wit hin a s ector t hat is in the protected s tat e (s ee “Pr otect Sec tor”
on page 22) or locked down (see “Sec tor Lockdow n” on page 28), t hen the By te/Pag e Progr am comm and w ill no t
be execu ted, an d the devic e wi ll return to the idle stat e once the pin has been d eass erted. T he W EL bit in the
Status Regis ter will be res et bac k to the logica l “0” st ate if the progra m cyc le aborts due to an incom plete add ress
being sent, an incomplete byte of data being sent, the pin being deasserted on uneven byte boundaries, or
because the memory location to be programmed is protected or locked down.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For
faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to
determine if the data bytes have finished programming. At some point before the progra m cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to
program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register
CS
CS
CS
CS
CS
Atmel AT25DF641
13
3680F–DFLASH–4/10
Figure 7-1. Byte Program
SO
SI
SCK
CS
MS B MS B
2 310
00000010
6 754 10 1198 12 3
937 3833 36353431 3229 30
OP C O DE
HIG H-IMP E DANC E
AAAA AAAAA
MS B
DDDDDDDD
AD DR E S S B IT S A23-A0 DAT A IN
Figure 7-2. Page Program
SO
SI
SCK
MS B MS B
2 310
00000010
6 754 98 3937 3833 36353431 3229 30
OP C ODE
HIG H-IMP E DAN C E
A A A A AA
MS B
DDDDDDDD
ADDR E S S BIT S A23-A0 DAT A IN B Y T E 1
MS B
DDDDDDDD
DAT A IN B Y T E n
CS
7.2. Dual-Input Byte/Page Program
The Dual-Inp ut By te/ Pa ge Progr a m c omma nd is s im ilar to the s tand ard By te /Pa g e Pr ogra m c omm and a nd c an be
used to program anywhere from a single byte of data up to 256-bytes of data into previously erased memory
locations. Unlike the standard Byte/Page Program command, however, the Dual-Input Byte/Page Program
command allows two bits of data to be clocked into the device on every clock cycle rather than just one.
Before the Dua l-Input Byte/Page Pr ogram command can be s tarted, the Write Enabl e command must have been
previously issued to the device (see “Write Enable” on page 21) to set the Write Enable Latch (WEL) bit of the
Status Register to a logical “1” state. To perform a Dual-Input Byte/Page Program command, an opcode of A2h
must be c lock ed into the de v ice f ollow ed by t he three a ddres s bytes den oti ng t he firs t by te location of t he m e mor y
array to begin programming at. After the address bytes have been clocked in, data can then be clocked into the
device two bits at a time on both the SOI and SI pins.
The data is alw ays input with th e MS B of a byt e firs t, and t he MS B is a lways input on the SOI pin. Duri ng the first
clock cycle, bit seven of the fir st data by te wo ul d b e inp ut o n the SO I pi n w hi le bit six of t he s ame d ata by te w oul d
be input on the SI pin. During the next clock cycle, bits five and four of the first data byte would be input on the
SOI and SI pins, respectively. The sequence would continue with each byte of data being input after every four
clock cycles. Like the standard Byte/Page Program command, all data clocked into the device is stored in an
internal buffer.
14 Atmel AT25DF641
3680F–DFLASH–4/10
If the star ting memory address deno ted by A2 3-A0 does not fa ll on an eve n 256-byte page boundary (A7-A 0 are
not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this
situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the
beginning of t he s a me p ag e. F or ex a mpl e, i f th e s tart ing ad dr es s denoted by A 23-A0 is 0 000FEh, an d thr e e by tes
of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and
0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page
(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In
addition, if more than 256-bytes of data are sent to the device, then only the last 256-bytes sent will be latched
into the internal buffer.
When the pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data
bytes sent to the device. If less than 256-bytes of data were sent to the device, then the remaining bytes within
the page w ill not be pr ogramme d and will rema in in th e erase d stat e (FF h). T he progr ammi ng of t he dat a b ytes is
internally self-timed and should take place in a time of tPP or tBP if only programming a single byte.
The three addr es s by tes an d at le as t on e c omp let e by t e of dat a mus t be c loc ked i nto th e dev ic e before t he pin
is deasserted, and the pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
device w ill abort the opera tion and no d ata will be progr ammed into the memory array . In addition, if t he address
specified by A2 3-A0 po in ts to a me mor y l oc ati on wit hin a s ector t hat is in the protected s tat e (s ee “Pr otect Sec tor”
on page 22) or loc ked dow n (s ee “Sect or Loc kdow n” on p age 28), then the Byte/ Page Pr ogram c omm and w ill no t
be execu ted, an d the devic e will return to the idle stat e once the pin has been d eass erted. T he W EL bit in the
Status Regis ter will be res et bac k to the logica l “0” st ate if the progra m cyc le aborts due to an incom plete add ress
being sent, an incomplete byte of data being sent, the pin being deasserted on uneven byte boundaries, or
because the memory location to be programmed is protected or locked down.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For
faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to
determine if the data bytes have finished programming. At some point before the program cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to
program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
Figure 7-3. Dual-Input Byte Program
SOI
SI
SCK
MS B MS B
2 310
10100010
6 754 10 1198 12 33 353431 3229 30
OP C ODE
AAAA AAAAA
ADDR E S S B IT S A23-A0
MS B
D7
D6
D5
D4
D3
D2
D1
D0
IN P UT
DAT A B Y T E
HIG H -IMP E DANC E
CS
CS
CS
CS
CS
CS
Atmel AT25DF641
15
3680F–DFLASH–4/10
Figure 7-4. Dual-Input Page Program
SOI
SI
SCK
MS B MS B
2 310
10100010
6 754 10 1198 12 3937 3833 36353431 3229 30
OP C ODE
AAAA AAAAA
MS B MS B
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
ADDR E S S B IT S A23-A0
IN P UT
DAT A B Y T E 1
MS B
D7
D6
D5
D4
D3
D2
D1
D0
IN P UT
DAT A B Y T E n
IN P UT
DAT A B Y T E 2
HIG H -IMP E DANC E
CS
7.3. Block Erase
A block of 4-, 32-, or 64-Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using
one of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an
opcode of 5 2h is used for a 32-Kbyte erase , and an opcode of D8h is used f or a 64-Kbyte erase . Before a Block
Erase command can be started, the Write Enable command must have been previously issued to the device to
set the WEL bit of the Status Register to a logical “1” state.
To perfor m a Block Erase, the pin m ust first be ass erted and t he appropr iate opcode ( 20h, 52h , or D8h) must
be clock ed into the device. After th e opcode h as been clock ed in, the t hree address bytes specify ing an ad dress
within the 4-, 32-, or 64-Kb yte block to be erased mus t be clocked in. Any addi tional data clocked in to the device
will be ignored. When the pin is deasserted, the device will erase the appropriate block. The erasing of the
block is internally self-timed and should take place in a time of tBLKE.
Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be
decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and
their values can be either a logical “1” or “0” . For a 32-Kbyte er ase, address bi ts A14-A0 wi ll be ignor ed, an d for a
64-Kbyte eras e , a ddr es s bits A15-A0 wi ll be ig nored by the devic e . D es pit e th e lo wer or der ad dr es s bits not bei ng
decoded by the device, the c omplete t hre e address byt es mus t s till be c lock ed i nto the dev ice b ef ore th e pin is
deasserted, and t he pi n must be deass erted on an ev en byte boundar y (mu ltiple s of eig ht bits ); other wise, the
device will abort the operation and no erase operation will be performed.
If the address specified by A23-A0 points to a memory location within a sector that is in the protected or locked
down state, t hen the Bloc k Erase comman d will not be ex ecuted, and the dev ice will return to the idle state once
the pin has been deasserted.
The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an
incomplete address being sent, the pin being deasserted on uneven byte boundaries, or because a memory
location within the region to be erased is protected or locked down.
While the dev ice is executing a s uccessful erase c ycle, the Status Re gister can be read a nd will indicate th at the
device is bus y. For fas ter thr ough put, i t is recomm end ed that the St at us R eg ister be p ol led rath er th an wai tin g th e
tBLKE time to determine if the device has finished erasing. At some point before the erase cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase
properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.
CS
CS
CS
CS
CS
CS
16 Atmel AT25DF641
3680F–DFLASH–4/10
Figure 7-5. Block Erase
SO
SI
SCK
CS
MS B MS B
2 310
CCCCCCCC
6 754 10 1198 12 3129 3027 2826
OP C ODE
AAAA AAAAA AAA
ADDR E S S B IT S A23-A0
HIG H -IMP E DANC E
7.4. Chip Erase
The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip
Erase command can be started, the Write Enable command must have been previously issued to the device to
set the WEL bit of the Status Register to a logical “1” state.
Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device
functiona lity when utilizing t he two opcodes, so they can be used intercha ngeably. T o perform a Chip Erase, one
of the two opco des (60 h or C 7h) mus t be c locked into t he dev ice. Si nce t he entir e mem ory ar ray is to be eras ed,
no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.
When the pin is deasserted, the device will erase the entire memory array. The erasing of the device is
internally self-timed and should take place in a time of tCHPE.
The complete opcode must be clocked into the device before the pin is deasserted, and the pin must be
deasserted o n an even byte boundar y (multiples of ei ght bits); otherwise , no erase will be perform ed. In addition,
if any s ector of the memory ar ray is in th e protec ted or loc ked down state, th en the Ch ip Erase c ommand w ill not
be execu ted, an d the devic e will return to the idle stat e once the pin has been d eass erted. T he W EL bit in the
Status Regis ter w ill be rese t back to the logica l “0” s tate if the pin is deass erted o n uneven byte bound aries or
if a sector is in the protected or locked down state.
While the dev ice is executing a s uccessful erase c ycle, the Status Re gister can be read a nd will indicate th at the
device is bus y. For fas ter thr ough put, i t is recomm end ed that the St at us R eg ister be p ol led rath er th an wai tin g th e
tCHPE time to determine if the device has finished erasing. At some point before the erase cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase
properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.
CS
CS
CS
CS
CS
Atmel AT25DF641
17
3680F–DFLASH–4/10
Figure 7-6. Chip Erase
SO
SI
SCK
CS
MS B
2 310
CCCCCCCC
6 754
OP C ODE
HIG H-IMP E DANC E
7.5. Program/Erase Suspend
In some code plus data sto rage applications, it is often necessary to process certain high-level system interrupts
that require relatively immediat e reading of code or data from the Flash memory. In such an insta nce, it may not
be poss ible for the s ystem to wait the microsec onds o r milliseconds require d for t he Flash m emory to c omplete a
program or erase cyc le. The Progra m/Erase Sus pend c ommand allow s a program or erase oper ation in pro gress
to a particular 64-Kbyte s ec t or of th e F l ash me mor y array to be s us p end ed s o t hat other d evic e o perations ca n be
performed. For example, by suspending an erase operation to a particular sector, the system can perform
functions such as a program or read operation within another 64-Kbyte sector in the device. Other device
operations, such as a Read Status Register, can also be performed while a program or erase operation is
suspended. Table 7-1 outlines the operations that are allowed and not allowed during a program or erase
suspend.
Since the ne ed t o s uspend a pr ogra m or er as e op er ati on is imm ed iate , th e Write Ena ble c omm and do es not need
to be issue d prior t o t he Pr ogr am/ Eras e S us pen d c om mand bei ng iss ue d. Ther ef or e, the Progr am /Eras e Su s pend
command operates independently of the state of the WEL bit in the Status Register.
To perform a Program/ Erase Susp end, the pin must fi rst be ass erted and the op code of B0h must be cloc ked
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode
will be ignored. When the pin is deasserted, the program or erase operation currently in progress will be
suspended within a time of tSUSP. The Program Suspend (PS) bit or the Erase Suspend (ES) bit in the Status
Register will then be set to the logical “1” state to indicate that the program or erase operation has been
suspended. In addition, the RDY/BSY bit in the Status Register will indicate that the device is ready for another
operation . Th e c o mpl ete o pc ode mus t be c l ock ed into the dev ice before t he pin i s deas s ert ed, an d t he pin
must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no suspend operation will be
performed.
Read opera tio ns are n ot a llowed to a 64-K by te s ector t hat h as had its pro gr am or eras e op erat ion s us pe nde d . If a
read is attempted t o a suspended sec tor, then the dev ice will output unde fined data. Ther efore, when perfor ming
a Read Array operation to an unsuspended sector and the device’s internal address counter increments and
crosses the sector boundary to a suspended sector, the device will then start outputting undefined data
continuously until the address counter increments and crosses a sector boundary to an unsuspended sector.
CS
CS
CS
CS
18 Atmel AT25DF641
3680F–DFLASH–4/10
A program operation is not allowed to a sector that has been erase suspended. If a program operation is
attempted to an erase suspended sector, then the program operation will abort and the WEL bit in the Status
Register will be r eset back to the logica l “0” s tate. L ike wise, a n erase operatio n is not allow ed to a sector tha t has
been program s uspend ed. If attempte d, the eras e operation wi ll abort and the WEL bit in t he Status Re gister will
be reset to a logical “0” state.
During an Erase Suspend, a program operation to a different 64-Kbyte sector can be started and subsequently
suspended. This results in a simultaneous Erase Suspend/Program Suspend condition and will be indicated by
the states of both the ES and PS bits in the Status Register being set to the logical “1” state.
If a Reset operation (see “Reset” on page 40) is performed while a sector is erase suspended, the suspend
operation will abort and the contents of the block in the suspended sector will be left in an undefined state.
However, i f a Reset is perf ormed while a sect or is program sus pended, the s uspend operat ion will abort but only
the contents of the page that was being programmed and subsequently suspended will be undefined. The
remaining pages in the 64-Kbyte sector will retain their previous contents.
If an attempt is made to perform an operation that is not allowed during a program or erase suspend, such as a
Protect Sector operation, then the device will simply ignore the opcode and no operation will be performed. The
state of the WEL bit in the Status Register, as well as the SPRL (Sector Protection Registers Locked) and SLE
(Sector Lockdown Enabled) bits, will not be affected.
Atmel AT25DF641
19
3680F–DFLASH–4/10
Table 7-1. Operations Allowed and Not Allowed During a Program or Erase Suspend
Command Operation During
Program Suspend Operation During
Erase Suspend
Read Commands
Read Array (All Opcodes) Allowed Allowed
Program and Erase Commands
Block Erase Not Allowed Not Allowed
Chip Erase Not Allowed Not Allowed
Byte/Page Program (All Opcodes) Not Allowed Allowed
Program/Erase Suspend Not Allowed Allowed
Program/Erase Resume Allowed Allowed
Protection Commands
Write Enable Not Allowed Allowed
Write Disable Not Allowed Allowed
Protect Sector Not Allowed Not Allowed
Unprotect Sector Not Allowed Not Allowed
Global Protect/Unprotect Not Allowed Not Allowed
Read Sector Protection Registers Allowed Allowed
Security Commands
Sector Lockd own Not Allowed Not Allowed
Freeze Sector Lockdown State Not Allowed Not Allowed
Read Sector Lockdown Registers Allowed Allowed
Program OTP Security Register Not Allowed Not Allowed
Read OTP Security Register Allowed Allowed
Status Register Commands
Read Status Register Allowed Allowed
Write Status Register (All Opcodes) Not Allowed Not Allowed
Miscellaneous Commands
Reset Allowed Allowed
Read Manufacturer and Device ID Allowed Allowed
Deep Power-Down Not Allowed Not Allowed
Resume from Deep Power-Down Not Allowed Not Allowed
20 Atmel AT25DF641
3680F–DFLASH–4/10
Figure 7-7. Program/Erase Suspend
SO
SI
SCK
CS
MS B
2 310
10110000
6 754
OP C ODE
HIG H -IMP E DANC E
7.6. Program/Erase Resume
The Program/Erase Resume command allows a suspended program or erase operation to be resumed and
continue pro gram ming a Fl ash pag e or erasi ng a Flas h memor y block where it left off. As with t he Pr ogram/E rase
Suspend co mmand, th e Write Enab le command does not nee d to be iss ued prior to the Program/ Erase Resume
command b eing issued. Th erefore, the Pr ogram/Erase Res ume command oper ates independe ntly of the sta te of
the WEL bit in the Status Register.
To perform a Pro gram/Eras e Resume, the pin must fir st be asserted and the op code of D0h must be c locked
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode
will be ignored. When the pin is deasserted, the program or erase operation currently suspended will be
resumed within a t ime of tRES. The P S bit or the ES bit in the Stat us Register will t hen be reset back to t he logical
“0” state to indicate that the program or erase operation is no longer suspende d. In addition, the RDY/BSY bit in
the Status Register will indicate that the device is busy performing a program or erase operation. The complete
opcode must be clocked into the device before the pin is deasserted, a nd the pin must be deasserted on
an even byte boundary (multiples of eight bits); otherwise, no resume operation will be performed.
During a simultaneous Erase Suspend/Program Suspend condition, issuing the Program/Erase Resume
command w il l res ult in t he progr am oper a tio n res um in g firs t. A fter th e progr a m o p er atio n has b een c o mp let e d, t he
Program/Erase Resume command must be issued again in order for the erase operation to be resumed.
While the device is busy resuming a program or erase operation, any attempts at issuing the Program/Erase
Suspend c omm and w il l be ignor ed . Ther efore, if a resu med pr o gram or er ase op er atio n nee ds to be subs eq u ently
suspended again, the system must either wait the entire tRES time before issuing the Program/Erase Suspend
command, or it must c h ec k the st atus o f the RDY/ B SY bit or t he appropr iate PS or ES b it in th e St atus Re gis t er to
determine if the previously suspended program or erase operation has resumed.
CS
CS
CS
CS
Atmel AT25DF641
21
3680F–DFLASH–4/10
Figure 7-8. Program/Erase Resume
SO
SI
SCK
CS
MS B
2 310
11010000
6 754
OP C ODE
HIG H -IMP E DANC E
8. Protec ti on Com mands a nd Fe at ures
8.1. Write Enable
The Write Ena ble comman d is used to set the Wr ite Enable Latc h (WEL) bit in the Status Regis ter to a logic al “1”
state. The WEL bit must be set before a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector
Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, or Write Status Register command
can be ex ecut e d. Th is makes the iss uanc e of th es e c o mma nds a t wo s te p proc ess, ther eby re duc in g th e c ha nc es
of a comm and bein g accid entally or erroneous ly exec uted. If the WEL bi t in the Status Reg ister is no t set p rior to
the issuance of one of these commands, then the command will not be executed.
To issue the Write Enable command, the pin must first be asserted and the opcode of 06h must be clocked
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode
will be ignore d. When the pin is deasser ted, the WEL bit in the Status Reg ister will be s et to a logical “1” . The
complete opcode must be clocked into the device before the pin is deasserted, and the pin must be
deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and
the state of the WEL bit will not change.
Figure 8-1. Write Enable
SO
SI
SCK
CS
MS B
2 310
00000110
6 754
OP C ODE
HIG H -IMP E DANC E
CS
CS
CS
CS
22 Atmel AT25DF641
3680F–DFLASH–4/10
8.2. Write Disable
The Write Dis a bl e comm an d is us ed to res et t he Write Ena ble Latc h (W EL) bit in t he St atus Reg ist er to t he l o gic al
"0" state. With the WEL bit reset, all Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector
Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, and Write Status Register
commands will not be executed. Other conditions can also cause the WEL bit to be reset; for more details, refer to
the WEL bit section of the Status Register description.
To issue the Write Disable command, the pin must first be asserted and the opcode of 04h must be clocked
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode
will be ignored. When the pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”.
The complete opcode must be clocked into the device before the pin is deasserted, and the pin must be
deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and
the state of the WEL bit will not change.
Figure 8-2. Write Disable
SO
SI
SCK
CS
MS B
2 310
00000100
6 754
OP C ODE
HIG H-IMP E DANC E
8.3. Protect Sector
Every physical 64-Kbyte sector of the device has a corresponding single-bit Sector Protection Register that is
used to control the software protection of a sector. Upon device power-up, each Sector Protection Register will
default to the logical “1” state indicating that all sectors are protected and cannot be programmed or erased.
Issuing the Protect Sector command to a particular sector address will set the corresponding Sector Protection
Register to the logical “1” state. The following table outlines the two states of the Sector Protection Registers.
Table 8-1. Sec tor Protec t ion Reg ist er Val ues
Value Sector Protection Status
0 Sector is unprote cted and ca n be progr am m ed and erase d
1 Sector is protecte d and cannot be programmed or erased
This is the default state
CS
CS
CS
CS
Atmel AT25DF641
23
3680F–DFLASH–4/10
Before the Pro tec t Sec t or comm and c an b e is sued, th e Write Ena bl e command mus t hav e be en prev i ous ly iss ued
to set the WEL bit in the Status Register to a logical “1”. To issue th e Protect Sector command, the pin must
first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes
designating any address within the sector to be protected. Any additional data clocked into the device will be
ignored. When the pin is deasserted, the Sector Protection Register corresponding to the physical sector
addressed by A23-A0 will be set to the logical “1” state, and the sector itself will then be protected from program
and erase operations. In addition, the WEL bit in the Status Register will be reset back to the logical “0” state.
The complete three address bytes must be clocked into the device before the pin is deasserted, and the
pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the
operation . Whe n t he dev ice abor ts the Protect Sec tor oper ati on, th e s tat e of t he S ec tor Pro tec ti on Reg is ter will be
unchanged, and the WEL bit in the Status Register will be reset to a logical “0”.
As a safeguard against accidental or erroneous protecting or unprotecting of sectors, the Sector Protection
Register s can themselves be locked from u pdates by using th e SPRL (Sector Prot ection Registers Locked) bit of
the Status Register (please refer to the Status Register Commands description for more details). If the Sector
Protect ion Regist ers are lock ed, then any attempts t o issue the Protect Sector comma nd will be ignored, and the
device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the
pin has been deasser te d.
Figure 8-3. Protect Sector
SO
SI
SCK
CS
MS B MS B
2 310
00110110
6 754 10 1198 12 3129 3027 2826
OP C ODE
AAAA AAAAA AAA
ADDR E S S B IT S A23-A0
HIG H -IMP E DANC E
8.4. Unprotect Sector
Issuing the Unprotect Sector command to a particular sector address will reset the corresponding Sector
Protection Register to the logical “0” state (see Table 8-1 for Sector Protection Register values). Every physical
sector of t he devic e has a corres ponding sing le-bit Se ctor Protect ion Regis ter that is used t o control the soft ware
protection of a sector.
Before the Unprotect Sector command can be issued, the Write Enable command must have been previously
issued to se t the WEL bit i n the Status Reg ister to a logica l “1”. To issue the Unprotect Sec tor command , the
pin must first be asserted and the opcode of 39h must be clocked into the device. After the opcode has been
clocked in, the three addre ss bytes designat ing any address within the sector to be unprotecte d must be clo cked
in. Any additional data clocked into the device after the address bytes will be ignored. When the pin is
deasserted, the Sector Protection Register corresponding to the sector addressed by A23-A0 will be reset to the
logical “0” state, and the sector itself will be unprotected. In addition, the WEL bit in the Status Register will be
reset back to the logical “0” state.
CS
CS
CS
CS
CS
CS
CS
24 Atmel AT25DF641
3680F–DFLASH–4/10
The complete three address bytes must be clocked into the device before the pin is deasserted, and the
pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the
operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register
will be reset to a logical “0”.
As a safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Protection Registers
can thems elves b e locked fr om updates by us ing the SPRL (Sec tor Protect ion R egister s Locked) bit of the Status
Register (please refer to the Status Register description for more details). If the Sector Protection Registers are
locked, then any attempts to issue the Unprotect Sector command will be ignored, and the device will reset the
WEL bit in the Status Register back to a logical “0” and return to the idle state once the pin has been
deasserted.
Figure 8-4. Unprotect Sect or
SO
SI
SCK
CS
MS B MS B
2 310
00111001
6 754 10 1198 12 3129 3027 2826
OP C ODE
AAAA AAAAA A A A
ADDR E S S B IT S A23-A0
HIG H -IMP E DANC E
8.5. Global Protect/Unprotect
The Global Protect and Global Unprotect feat ures can work in conjunc tion with the Prot ect Sector and Unprotect
Sector f unctions . For exam ple, a sy stem can glo bally protec t the entire m emory arr ay and then use the Unp rotect
Sector command to individually unprotect certain sectors and individually re-protect them later by using the
Protect Sector comm and . L ik ewis e, a sy s tem c an gl ob ally unpr o tec t t he ent ire memory ar ray an d t hen in div i d ually
protect certain sectors as needed.
Performing a Global Protect or Global Unprotect is accomplished by writing a certain combination of data to the
Status Re gister us ing the Write Status Regis ter Byte 1 com mand (see “Write Status Re gister Byte 1” on page 38
for command execution details). The Write Status Register command is also used to modify the SPRL (Sector
Protection Registers Locked) bit to control hardware and software locking.
To perform a Global Protect, the appropriate pin and SPRL conditions must be met, and the system must
write a logica l “1” to bits five, four, three, and two of th e first byte of the St atus Regis ter. Converse ly, to perfo rm a
Global Unprotect, the same and SPRL conditions must be met but the system must write a logical “0” to bits
five, four, three, and two of the first byte of the Status Register. Table 8-1 details the conditions necessary for a
Global Protec t or Glob al Un protec t to be perfor med.
Sectors that have been erase or program suspended must remain in the unprotected state. If a Global Protect
operation is attempted while a sector is erase or program suspended, the protection operation will abort, the
protection s tates of all sec tors in the Flash memor y array will not chan ge, and WEL bit in t he Status Regist er will
be reset back to a logical “0”.
WP
WP
CS
CS
CS
Atmel AT25DF641
25
3680F–DFLASH–4/10
Table 8-2. Val id S PRL and Glob al Pro tec t/U npro tec t Conditions
State
Current
SPRL
Value
New Write Status
Register Byte 1
Data
Protection Operation
New
SPRL
Value
Bit
7 6 5 4 3 2 1 0
0 0
0 x 0 0 0 0 x x
0 x 0 0 0 1 x x
↕
0 x 1 1 1 0 x x
0 x 1 1 1 1 x x
1 x 0 0 0 0 x x
1 x 0 0 0 1 x x
↕
1 x 1 1 1 0 x x
1 x 1 1 1 1 x x
Global Unprotect – all Sector Protect i on Registers reset t o 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
Global Unprotect – all Sector Protect i on Registers reset t o 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Regis t ers set to 1
0
0
0
0
0
1
1
1
1
1
0 1 x x x x x x x x
No change to the current protection level. All sect ors currently prot ected will remai n protected
and all sectors currently unprotected will remain unprotected.
The Sector Protecti on Registers are hard-loc k ed and cannot be changed when the pin is
LOW and the current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur.
In addition, the SPRL bit cannot be changed (the pin m ust be HIGH in order to change
SPRL back to a 0).
1 0
0 x 0 0 0 0 x x
0 x 0 0 0 1 x x
↕
0 x 1 1 1 0 x x
0 x 1 1 1 1 x x
1 x 0 0 0 0 x x
1 x 0 0 0 1 x x
↕
1 x 1 1 1 0 x x
1 x 1 1 1 1 x x
Global Unprotect – all Sector Protect i on Registers reset t o 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
Global Unprotect – all Sector Protect i on Registers reset t o 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Regis t ers set to 1
0
0
0
0
0
1
1
1
1
1
1 1
0 x 0 0 0 0 x x
0 x 0 0 0 1 x x
↕
0 x 1 1 1 0 x x
0 x 1 1 1 1 x x
1 x 0 0 0 0 x x
1 x 0 0 0 1 x x
↕
1 x 1 1 1 0 x x
1 x 1 1 1 1 x x
No change to the current protection level. All sect ors currently
protected will remain prot ect ed, and all sectors currently
unprotected will rem ain unprotected.
The Sector Protecti on Registers are soft -lock ed and cannot be
changed when the current state of SPRL is 1. Therefore, a Global
Protect/ Unprot ect will not occur. However, the SPRL bit can be
changed back to a 0 from a 1 since the pin is HIGH. To
perform a Global Protect/ Unprot ect, the Write Status Register
command must be issued again after the SPRL bit has been
changed from a 1 to a 0.
0
0
0
0
0
1
1
1
1
1
Essentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector Protection Registers are not
locked), th en writing a 00h t o the firs t by te of t he Stat u s Regis ter will p erfor m a G loba l Unprotect without c ha ngi ng
the state of the SPRL bit. Similarly, writing a 7Fh to the first byte of the Status Register will perform a Global
Protect an d keep the S PRL bit in t he logica l “0” s tate. T he SPRL b it can, of cours e, be c hanged t o a logica l “1” by
writing an FFh if software-locking or hardware-locking is desired along with the Global Protect.
WP
WP
WP
WP
26 Atmel AT25DF641
3680F–DFLASH–4/10
If the desire is to only change the SPRL bit without performing a Global Protect or Global Unprotect, then the
system can simply write a 0Fh to the first byte of the Status Register to change the SPRL bit from a logical “1” to a
logical “0” pr ov ided the pin is deasser ted. Like wise, t he s ys tem can writ e an F0h to chan ge the S PRL bit fro m
a logical “0” to a logical “1” without affecting the current sector protection status (no changes will be made t o the
Sector Protec t ion Reg ister s ).
When writ ing to the firs t byte of the Stat us Regist er, bits five, four, three, and two will not ac tually be m odified but
will be decoded by the device for the purposes of the Global Protect and Global Unprotect functions. Only bit
seven, the SPRL bit, will actually be modified. Therefore, when reading the first byte of the Status Register, bits
five, four, three, and two wi ll not refl ect the valu es wr itten to the m but will instead i ndicate t he status of th e pin
and the sector protection status. Please refer to “Status Register Commands” on page 34 and Table 10-1 on page
34 for details on the Status Register format and what values can be read for bits five, four, three, and two.
8.6. Read Sector Protection Registers
The Sector Protection Registers can be read to determine the current software protection status of each sector.
Reading the Sector Protection Registers, however, will not determine the status of the pin.
To read the Sec tor Protect ion Reg ister for a partic ular sector , the pin must firs t be as serted an d the opc ode of
3Ch must be clocked in. Once the opcode has been clocked in, three address bytes designating any address
within the sector must be clocked in. After the last address byte has been clocked in, the device will begin
outputting dat a on the SO pin duri ng every subseque nt clock c yc le. The data be i ng o utpu t w ill b e a r epe ati n g by te
of either FFh or 00h to denote the value of the appropriate Sector Protection Register.
At clock frequencies above fCLK, the first byte of data output will not be valid. Therefore, if operating at clock
frequencies above fCLK, at least two bytes of data must be clocked out from the device in order to determine the
correct status of the appropriate Sector Protection Register.
Table 8-3. R ead Sector Prot ec tio n Regis ter - Output Data
Output Data Sector Protection Register Value
00h Sector Protection Register value is 0 (sector is unprotected)
FFh Sector Protection Register value is 1 (sector is protected)
Deassert ing the pin will ter minate the re ad operat ion and put t he SO pin i nto a hi gh-impeda nce state. T he
pin can be deasserted at any time and does not require that a full byte of data be read.
In addition to read ing the individua l Sector Protectio n Registers, the Soft ware Protection St atus (SWP) bits in th e
Status Register can be read to determine if all, some, or none of the sectors are software protected (refer to
“Read Status Register” on page 34 for more details).
CS
CS
CS
WP
WP
WP
Atmel AT25DF641
27
3680F–DFLASH–4/10
Figure 8-5. Read Sector Protec tion Register
SO
SI
SCK
CS
MS B MS B
2 310
00111100
6 754 10 1198 12 37 3833 3
6353431 3229 30 39 40
OP C ODE
AAAA AAAAA
MS B MS B
DDDDDDDDDD
ADDR E S S B IT S A23-A0
DAT A B Y T E
HIG H -IMP E DANC E
8.7. Protected States and the Write Protect ( ) Pin
The pin is not linked to the memory array itself and has no direct effect on the protection status or lockdown
status of the memory array. Instead, the pin, in conjunction with the SPRL (Sector Protection Registers
Locked) bi t i n th e St atus R egis ter, is used to c o ntr ol t he har dw are loc k ing m ec ha nis m o f th e device. For h ar dware
locking to be active, two conditions must be met-the pin must be asserted and the SPRL bit must be in the
logical “1” state.
When hardware locking is active, the Sector Protection Registers are locked and the SPRL bit itself is also locked.
Therefore, s ectors that are pr otected w ill be loc ked in the pr otecte d state, a nd sector s that are unpr otec ted wi ll be
locked in the unprotected state. These states cannot be changed as long as hardware locking is active, so the
Protect Sector, Unprotect Sector, and Write Status Register commands will be ignored. In order to modify the
protection s tatus of a s ec to r, t he pin must first be de a ss er ted, and the SPR L bit i n the Sta tus Reg ister mus t be
reset back to the logical “0” s tate using the Write Status Register comma nd. When r esetting the SPRL b it back to
a logical “0”, it is not possible to perform a Global Protect or Global Unprotect at the same time since the Sector
Protection Registers remain soft-locked until after the Write Status Register command has been executed.
If the pin is permanently connected to GND, then once the SPRL bit is set to a logical “1”, the only way to
reset the bit back to the logical “0” state is to power-cycle the device. This allows a system to power-up with all
sectors software protected but not hardware locked. Therefore, sectors can be unprotected and protected as
needed and then hardware locked at a later time by simply setting the SPRL bit in the Status Register.
When the pin is deasserted, or if the pin is permanently connected to VCC, the SPRL bit in the Status
Register can still be set to a logical “1” to lock the Sector Protection Registers. This provides a software locking
ability to prevent er r on eous Pr ot ec t S ect or or Un pr otect Sec tor c om man ds fr o m b ein g proc es sed . Whe n cha ngi ng
the SPRL bit to a logical “1” from a logical “0”, it is also possible to perform a Global Protect or Global Unprotect at
the same time by writing the appropriate values into bits five, four, three, and two of the first byte of the Status
Register.
Table 8-1 and Table 8-2 detail the various protection and locking states of the device.
Table 8-4. Sec tor Protec t ion Reg ist er Stat es
Sector Protection Register
n(1) Sector
n(1)
X
(Don't Care) 0 Unprotected
1 Protected
Note: 1. “n” represents a sector number.
WP
WP
WP
WP
WP
WP
WP
WP
WP
28 Atmel AT25DF641
3680F–DFLASH–4/10
Table 8-5. Hardware and Software Locking
SPRL Locking SPRL Change Allowed Sector Protection Registers
0 0 Can be modified from 0 to 1 Unlocked and modifiable using the Protect and Unprotect
Sector commands. Global Protect and Unprotect can also be
performed.
0 1 Hardware
Locked Locked Locked in current state. Protect and Unprotect Sector
commands will be ignored. Global Protect and Unprotect
cannot be performed.
1
0
Can be modified from 0 to 1
Unlocked and modifiable using the Protect and Unprotect
Sector commands. Global Protect and Unprotect can also be
performed.
1 1 Software
Locked Can be modified from 1 to 0 Locked in current state. Protect and Unprotect Sector
commands will be ignored. Global Protect and Unprotect
cannot be performed.
9. Security Commands
9.1. Sector Lockdown
Certain applications require that portions of the Flash memory array be permanently protected against malicious
attempts at altering program code, data modules, security information, or encryption/decryption algorithms, keys,
and routines. To address these applications, the device incorporates a sector lockdown mechanism that allows
any com bination of in dividual 64-K byte sectors to be perman ently locke d so that they become read only. On ce a
sector is locked dow n, it ca n nev er be eras ed or programmed aga in, a nd it c an n ev er be unloc ked fr o m the l oc ked
down state.
Each 64-Kbyte physical sector has a corresponding single-bit Sector Lockdown Register that is used to control
the lockdown status of that sector. These registers are nonvolatile and will retain their state even after a device
power-cycle or reset operation. The following table outlines the two states of the Sector Lockdown Registers.
Table 9-1. Sec tor Lock down R eg ister Values
Value Sector Lockdown Status
0 Sector is not locked down and can be programmed and erased. This is the default state.
1 Sector is permanently locked down and can never be programmed or erased again.
Issuing th e Sector Lock down c ommand to a p articul ar sector address will set the corr esponding Sec tor Loc kdown
Register to the logica l “1” state. Eac h Sector Lock down Regis ter can only be set once; ther efore, once s et to the
logical “1” state, a Sector Lockdown Register cannot be reset back to the logical “0” state.
WP
Atmel AT25DF641
29
3680F–DFLASH–4/10
Before the Sector Lockdown command can be issued, the Write Enable command must have been previously
issued to set the WEL bit in the Status Register to a logical “1”. In addition, the Sector Lockdow n Enabled (SLE)
bit in the Status Register must have also been previously set to the logical “1” state by using the Write Status
Register Byte 2 command (see “Write Status Register Byte 2” on page 39). To issue the Sector Lockdown
command, the pin must first be asserted and the opcode of 33h must be clocked into the device followed by
three address bytes designating any address within the 64-Kbyte sector to be locked down. After the three
address by tes have been cl ock ed in, a c o nfirmation by t e of D0h mus t a ls o be cl oc k ed in imm edi ate ly fol low in g th e
three address bytes. Any additional data clocked into the device after the first byte of data will be ignored. When
the pin is deass erted, t he Sec tor Lock down R egister cor respondi ng to the s ector address ed by A 23-A0 w ill be
set to the logical “1” state, and the sector itself will then be permanently locked down from program and erase
operations within a ti me o f tLOCK. In a dd ition, t he WE L bit in the S tat us Regis ter w ill b e res et b ac k to th e lo gic al “ 0”
state.
The complete t hree ad dress bytes and the c orrec t confirmat ion by te value of D 0h must be c locked i nto the de vice
before the pin is deassert ed, and t he pin mus t be dea sser ted on an eve n byte boundar y (mu ltiples of e igh t
bits); otherwise, the device will abort the operation. When the device aborts the Sector Lockdown operation, the
state of the corresponding Sector Lockdown Register as well as the SLE bit in the Status Register will be
unchanged; however, the WEL bit in the Status Register will be reset to a logical “0”.
As a safeguard against accidental or erroneous locking down of sect ors, the Sector Lockdown co mmand can be
enabled and disabled as needed by using the SLE bit in the Status Register. In addition, the current sector
lockdown state can be frozen so that no further modifications to the Sector Lockdown Registers can be made
(see “Freeze Sector Lockdown State”). If the Sector Lockdown command is disabled or if the sector lockdown
state is frozen, then any attempts to issue the Sector Lockdown command will be ignored, and the device will
reset the WEL b it in the Sta tus Reg is ter bac k to a log ical “0” and r etur n to t h e idle s tate o nc e t he p in has b ee n
deasserted.
Figure 9-1. Sector Lockdown
SO
SI
SCK
CS
MS B MS B
2 310
00110011
6 754 98 3937 3833 36353431 3229 30
OP C ODE
HIG H -IMP E DANC E
A A A A AA
MS B
11010000
ADDR E S S B IT S A23-A0 C O NF IR MAT IO N B Y T E IN
CS
CS
CS
CS
CS
30 Atmel AT25DF641
3680F–DFLASH–4/10
9.2. Freeze Sector Lockdown State
The current sector lockdown state can be permanently frozen so that no further modifications to the Sector
Lockdown Registers can be made; therefore, the Sector Lockdown command will be permanently disabled, and
no additiona l sec tor s can be loc ked down aside fro m those alre ady lock ed do wn. Any atte mpt s to is s ue th e S ector
Lockdown command after the sector lockdown state h as been frozen w i ll be ignored.
Before the Fr eeze Sector Loc kdown State comma nd can be iss ued, the Write En able command mus t have been
previously issued to set the WEL bit in the Status Register to a logical “1”. In addition, the Sector Lockdown
Enabled (S LE) bit in th e Status Re gister must hav e also been pr eviously set to the log ical “1” state. T o issue the
Freeze Sector Lockdown State command, the pin must first be asserted and the opcode of 34h must be
clocked into the device followed by three command specific address bytes of 55AA40h. After the three address
bytes have been clocked in, a confirmation byte of D0h must be clocked in immediately following the three
address bytes. Any additional data clocked into the device will be ignored. When the pin is deasserted, the
current sector lockdown state will be permanently frozen within a time of tLOCK. In addition, the WEL bit in the
Status Reg ister w ill be res et bac k to th e logica l “0” s tate, an d the SLE b it will be per manent ly reset to a logic al “0”
to indicate that the Sector Lockdown command is permanently disabled.
The complete and correct three address bytes and the confirmation byte must be clocked into the device before
the pin is deasserted, and the pin must be deasserted on an even byte bound ary (multiples of eight bits);
otherwise, the device will abort the operation. When the device aborts the Freeze Sector Lockdown State
operation, the W EL bit in th e Status Regis ter will be res et to a log ical “0”; h oweve r, the s tate of th e SLE b it wil l be
unchanged.
Figure 9-2. Freeze Sector Lockdown State
SO
SI
SCK
CS
MS B MS B
2 310
00110100
6 754 98 3937 3833 36353431 3229 30
OP C ODE
HIG H -IMP E DANC E
0 1 0 0 00
MS B
11010000
ADDR E S S B IT S A23-A0 C O NF IR MAT IO N B Y T E IN
CS
CS
CS
CS
Atmel AT25DF641
31
3680F–DFLASH–4/10
9.3. Read Sector Lockdown Registers
The Sector Lock down Regis ters can be read to deter mine the current lock down status of each phy sical 64-Kbyte
sector. To read the Sector Lockdown Reg ister for a particular 64-Kbyte sector, the pin must first be asserted
and the opcode of 35h must be clocked in. Once the opcode has been clocked in, three address bytes
designating any address within the 64-Kbyte sector must be clocked in. After the address bytes have been
clocked in, data wi ll be out put on the SO pin dur ing e very subsequent c lock cyc le. The data bein g output w ill b e a
repeating byte of either FFh or 00h to denote the value of the appropriate Sector Lockdown Register.
At clock frequencies above fCLK, the first byte of data output will not be valid. Therefore, if operating at clock
frequencies above fCLK, at least two bytes of data must be clocked out from the device in order to determine the
correct status of the appropriate Sector Lockdown Register.
Table 9-3. R ead Sector Loc kdown Register – Output Data
Output Data Sector Lockdown Register Value
00h Sector Lockdown Register value is 0 (sector is not locked down)
FFh Sector Lockdown Register value is 1 (sector is permanently locked down)
Deassert ing the pin will ter minate the re ad operat ion and put t he SO pin i nto a high-i mpedance s tate. The
pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 9-3. Read Sector Lockdow n Re gister
SO
SI
SCK
CS
MS B MS B
2 310
00110101
6 754 10 1198 12 39 42 43414037 3833 36353431 3229 30 44 47 484645
OPCODE
AAAA AAAAA
MS B
XXXXXXXX
MS B MS B
DDDDDDDD
D
D
ADDR E S S B ITS A23-A0 DON'T CAR E
DATA BYTE
HIGH-IMPE DANC E
9.4. Program OTP Security Register
The device contains a specialized OTP (One-Time Programmable) Security Register that can be used for
purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key
storage, etc. The OTP Security Register is independent of the main Flash memory array and is comprised of a
total of 128-by tes of m emor y divided int o two p ortions . The first 64-by tes (by te loc atio ns 0 throu gh 63) o f the OT P
Security Register are allocated as a one-time user-programmable space. Once these 64-bytes have been
programmed, they cannot be erased or reprogrammed. The remaining 64-bytes of the OTP Security Register
(byte loc ati ons 6 4 t hr oug h 127) ar e fac t ory pr ogra mm ed by At mel a nd will co nta i n a un iqu e v a lue for eac h d ev ic e.
The factory programmed data is fixed and cannot be changed.
CS
CS
CS
32 Atmel AT25DF641
3680F–DFLASH–4/10
Table 9-4. OTP Security Register
Security Register
Byte Number
0 1 . . . 62 63 64 65 . . . 126 127
One-Time User Programmable Factory Programmed by Atmel
The user-programmable portion of the OTP Security Register does not need to be erased before it is
programmed. In addition, the Program OTP Security Register command operates on the entire 64-byte user-
programmable portion of the OTP Security Register at one time. Once the user-programmable space has been
programmed with any n umber of by tes, the user-progr ammable s pace cannot be progr ammed aga in; therefo re, it
is not possible to only program the first two bytes of the register and then program the remaining 62-bytes at a
later time.
Before the Progra m OTP S ecurity R egister command can be is sued, the Writ e Enab le comman d must h ave been
previously is s ued to s e t th e W EL bit in the S tatus R eg i s ter t o a logic a l “1” . T o pr o gr am t he OTP Sec urity R e gis ter ,
the pin must first be asserted and an opcode of 9Bh must be clocked into the device followed by the three
address bytes denoting the first byte location of the OTP Security Register to begin programming at. Since the
size of the user-programm able portion of the OTP Security Register is 64-bytes, the upper order address bits do
not need to be decoded by the device. Therefore, address bits A23-A6 will be ignored by the device and their
values can be either a logical “1” or “0”. After the address bytes have been clocked in, data can then be clocked
into the device and will be stored in the internal buffer.
If the starting memory address denoted by A23-A0 does not start at the beginning of the OTP Security Register
memory space (A5-A0 ar e not al l 0), then s pecial c ircumstanc es regar ding wh ich O TP Security Regis ter loc ations
to be pr ogrammed will app ly. In t his situa tion, any data th at is sent to the device that goes beyond the end of the
64-byte user-programmable space will wrap around back to the beginning of the OTP Security Register. For
example, if the starting address denoted by A23-A0 is 00003Eh, and three bytes of data are sent to the device,
then the first two bytes of data will be programmed at OTP Security Register addresses 00003Eh and 00003Fh
while the last byte of data will be programmed at address 000000h. The remaining bytes in the OTP Security
Register (addresses 000001h through 00003Dh) will not be programmed and will remain in the erased state
(FFh). In addition, if more than 64-bytes of data are sent to the device, then only the last 64-bytes sent will be
latched into the internal buffer.
When the pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate OTP Security Register locations based on the starting address specified by A23-A0 and the number
of data bytes sent to the device. If less than 64-bytes of data were sent to the device, then the remaining bytes
within the OTP Security Register will not be programmed and will remain in the erased state (FFh). The
programmi ng of the dat a bytes is interna lly self-tim ed and sho uld take pl ace in a time of tOTPP. It is not possi ble to
suspend the programming of the OTP Security Register.
The three addr es s by tes an d at le as t on e c omp let e byt e of dat a must be cloc k ed int o th e devic e befor e the pin
is deasserted, and the pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
device will abort the operation and the user-programmable portion of the OTP Security Register will not be
programmed. The WEL bit in the Status Register will be reset back to the logical “0” state if the OTP Security
Register program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent,
the pin being deasserted on uneven byte boundaries , or because the user -programmable portion of the O TP
Security Register was previously programmed.
While the devic e is pr o gr a mming t he OT P Secur ity Register, th e Sta tus Register c an be read and will indic a te that
the devic e is b us y . For f as ter thr ou ghp ut , it is r ec o mm ende d t hat the St at us R eg i ster be po lle d rat her t han waiting
the tOTPP time to determine if the data bytes have finished programming. At some point before the OTP Security
Register programming completes, the WEL bit in the Status Register will be reset back to the logical “0” state.
CS
CS
CS
CS
CS
Atmel AT25DF641
33
3680F–DFLASH–4/10
If the device is pow ered-down during the OTP Security Register program cycle, then t he contents of the 64-byte
user programmable portion of the OTP Security Register cannot be guaranteed and cannot be programmed
again.
The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the
contents of the buffer will be altered from its previous state when this command is issued.
Figure 9-4. Program OTP Security Register
SO
SI
SCK
CS
MS B MS B
2 310
10011011
6 754 98 3937 3833 36353431 3229 30
OP C ODE
HIG H -IMP E DANC E
A A A A AA
MS B
DDDDDDDD
ADDR E S S B IT S A23-A0 DAT A IN B Y T E 1
MS B
DDDDDDDD
DAT A IN B Y T E n
9.5. Read OTP Security Register
The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the
maximum cloc k frequenc y specifi ed by fMAX. To r ead the OT P Security Reg ister, the pin must firs t be assert ed
and the opcod e of 77h must be clock ed into the devic e. After the opcode h as been clocked i n, the three addr ess
bytes must be clocked in to specify the starting address location of the first byte to read within the OTP Security
Register. Following the three address bytes, two dummy bytes must be clocked into the device before data can
be output.
After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in
OTP Security Register data being output on the SO pin. When the last byte (00007Fh) of the OTP Security
Register has been read, the device will continue reading back at the beginning of the register (000000h). No
delays will be incurred when wrapping around from the end of the register to the beginning of the register.
Deassert ing the pin will ter minate the re ad oper ation and put the SO pin int o a high-im pedance s tate. T he
pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 9-5. Read OTP Security Register
SO
SI
SCK
CS
M S B M S B
2 310
01110111
6 754 10 1198 12 33 36353431 3229 30
O P C O D E
A A A A A A AA A X X X
M S B M S B
DDDDDDDDDD
AD DR E S S B IT S A23-A0
M S B
X X X X X X
D O N'T C A R E
DA T A B Y T E 1
HIG H -IMP E DANC E
CS
CS
CS
34 Atmel AT25DF641
3680F–DFLASH–4/10
10. Status Register Commands
10.1. Read Status Register
The two-byte Status Register can be read to determine the device’s ready/busy status, as well as the status of
many other functions suc h as Har dware Locking a nd Software Pr o tec ti on. Th e St atus Register c an b e read at any
time, including during an internally self-timed program or erase operation.
To read the Status Register, the pin must first be asserted and the opcode of 05h must be clocked into the
device. Aft er the opcod e has been cloc ked in, the dev ice will be gin outputt ing Status Register data o n the SO pin
during every subsequent clock cycle. After the second byte of the Status Register has been clocked out, the
sequence will repeat itself starting again with the first byte of the Status Register as long as the pin remains
asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated, so each
repeating sequence will output new data. The RDY/BSY status is available for both bytes of the Status Register
and is updated for each byte.
At clock frequencies above fCLK, the first two bytes of data output from the Status Register will not be valid.
Therefore, if operating at clock frequencies above fCLK, at least four bytes of data must be clocked out from the
device in order to read the correct values of both bytes of the Status Register.
Deasserting the pin will terminate the Read Status Register operation and put the SO pin into a
high-im pedance state. T he pin can b e deasserted at any time and does not req uire that a fu ll byte of data be
read.
Table 10-1. Status Register Format – Byte 1
Bit(1) Name Type(2) Description
7 SPRL Sector Protec tion Regi sters
Locked R/W
0
Sector Prot ecti on Regist ers are unlocked (def ault)
1
Sector Prot ecti on Regist ers are locked
6 RES Res erved for future use R 0 Reserved f or future use
5 EPE Erase/Pr ogram Error R
0
Erase or progr am operation w as successful
1
Erase or progr am error detect ed
4 WPP
Write Prot ect ( ) Pin Status R 0 is asserted
1
is deasserted
3:2 SWP Software Protection St atus R
00 All sectors are software unprotected ( all Sect or
Protection R egisters are 0)
01 Some sectors are software protected
Read individual Sect or Prot ection Regi ster s to
determine whic h sectors are protec ted
10
Reserved for futur e use
11 All sectors are software prot ected (all Sect or Protec tion
Registers are 1 – default)
1 WEL Write Enable Latch S tatus R 0 Device is not write enabled (default)
1 Device is w rite enabled
0 RDY/BSY Ready/Busy St atus R 0 Device is ready
1 Device is busy with an internal operation
Notes: 1. Only bit 7 of Status Register Byte 1 will be modified when using the Write Status Register
Byte 1 command
2. R/W = Readable and writeable
R = Readable only
WP
WP
WP
CS
CS
CS
CS
Atmel AT25DF641
35
3680F–DFLASH–4/10
Table 10-2. Status Register Format – Byte 2
Bit(1) Name Type(2) Description
7 RES Reserved for future use R 0 Reserved for future use.
6 RES Reserved for future use R 0 Reserved for future use.
5 RES Reserved for future use R 0 Reserved for future use.
4 RSTE Reset Enabled R/W 0 Reset command is disabled (default).
1 Reset command is enabled.
3 SLE Sector Lockd own Enabled R/W 0 Sector Lockd own and Fre eze Sector Loc kd ow n
State commands are dis abl ed ( defau lt) .
1 Sector Lockdown and Freeze Sector Loc kd own
State commands are enabled.
2 PS Program Suspend Status R 0 No sectors are program suspended (default).
1 A sector is program suspended.
1 ES Erase Suspend Status R 0 No sectors are erase suspended (default).
1 A sector is erase suspended.
0 RDY/BSY
Ready/Busy Status R 0 Device is ready.
1 Device is busy with an inter nal opera tion .
Notes: 1. Only bits 4 and 3 of Status Register Byte 2 will be modified when using the Write Status Register
Byte 2 command
2. R/W = Readable and writeable
R = Readable only
10.1.1. SPRL Bit
The SPRL bit is used t o co ntrol whet her th e Sec tor Protecti on Regis ters can be mod ified or not. When th e SPR L
bit is in the logical “1” state, all Sector Protection Registers are locked and cannot be modified with the Protect
Sector and Unprotect Sector commands (the devic e will ign ore these comm ands) . In addition, the Global Pr otect
and Global Unprotect features cannot be performed. Any sectors that are presently protected will remain
protected, and any sectors that are presently unprotected will remain unprotected.
When the SPRL bit is in the logical “0” state, all Sector Protection Registers are unlocked and can be modified
(the Protect Sector and Unprotect Sector commands, as well as the Global Protect and Global Unprotect features,
will be processed as normal). The SPRL bit defaults to the logical “0” state after device power-up. The Reset
command has no effect on the SPR L bit.
The SPRL b it can be mod ifi ed free ly whenev er the pin is deas serted. H owev er, if the pin is ass erted, th en
the SPRL bit may only be changed from a logical “0” (Sector Protection Registers are unlocked) to a logical “1”
(Sector Prot ec tio n Reg is ters are loc k ed). In or der to reset the S PRL bit bac k to a l ogic a l “0” using t he Wr ite S tatus
Register Byte 1 command, the pin will have to first be deasserted.
The SPRL bi t is t he only bit of S tatus R eg is ter By t e 1 t hat c an be us er modifie d vi a the Wr i te Stat us Reg ist er By te
1 command.
WP
WP
WP
36 Atmel AT25DF641
3680F–DFLASH–4/10
10.1.2. EPE Bit
The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one
byte dur ing the erase or program oper ation did no t erase or pro gram properly, t hen the EP E bit will be s et to the
logical “1” state. The EPE bit will not be set if an erase or program operation aborts for any reason such as an
attempt to erase or program a protected region or a locked down sector, an attempt to erase or program a
suspende d sector , or if the WEL b it is not set pr ior to an er ase or progra m oper ati on. The E PE b it wil l be upd ated
after every erase and program operation.
10.1.3. WPP Bit
The WPP bit can be read to determine if the pin has been asserted or not.
10.1.4. SWP Bit s
The SWP bits provide feedback on the software protection status for the device. There are three possible
combinations of the SWP bits that indicate whether none, some, or all of the sectors have been protected using
the Protec t Sector comma nd or the G lobal Protect f eature. If t he SWP bits indicate that s ome of the s ectors have
been protected, then the individual Sector Protection Registers can be read with the Read Sector Protection
Registers command to determine which sectors are in fact protected.
10.1.5. WEL Bit
The WEL bit in dicates the current s tatus of the inter nal Write E nable Latc h. When the W EL bit is in the logic al “0”
state, the device will not accept any Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector
Lockdown, Fr eeze S ector Loc kdown State , Program O TP Security Register, or Write St atus Regis ter comma nds.
The WEL bit defaults to the logical “0” state after a device power-up or reset operation. In addition, the WEL bit
will be reset to the logical “0” state automatically under the following conditions:
• Write Disable operation completes successfully
• Write Status Register operation completes successfully or aborts
• Protect Sector operation completes successfully or aborts
• Unprotect Sector operation completes successfully or aborts
• Sector Lockdown operation completes successfully or aborts
• Freeze Sector Lockdown State operation completes successfully or aborts
• Program OTP Security Register operation completes successfully or aborts
• Byte/Page Program operation completes successfully or aborts
• Block Erase operation completes successfully or aborts
• Chip Erase operation completes successfully or aborts
• Hold condition aborts
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts due to an
incomple te or unr ecogniz e d opcode bei ng c lock ed int o the device bef or e the pin is deas s erted. In order for the
WEL bit to be reset when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase,
Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security
Register , or Write Status Register command must have been clocked into the device.
CS
WP
Atmel AT25DF641
37
3680F–DFLASH–4/10
10.1.6. RSTE Bit
The RSTE bit is us ed to en able or disable the Reset c ommand. W hen the RST E bit is in the log ical “0” s tate (the
default state after power-up), the Reset command is disabled and any attempts to reset the device using the
Reset command will be ignored. When the RSTE bit is in the logical “1” state, the Reset command is enabled.
The RSTE bit will retain its state as long as power is applied to the device. Once set to the logical “1” state, the
RSTE bit will remain in that state until it is modified using the Write Status Reg ister Byte 2 comma nd or until the
device has been power cycled. The Reset command itself will not change the state of the RSTE bit.
10.1.7. SLE Bit
The SLE bit is used to enable and disable the Sector Lockdown and Freeze Sec tor Lockdown State commands.
When the SLE bit is in the logical “0” state (the default state after power-up), the Sector Lockdown and Freeze
Sector Lock down comman ds are disabled. If the Sector Lockdown a nd Freeze Sector Lockdown com mands are
disabled, then any attempts to issue the commands will be ignored. This provides a safeguard for these
commands against accidental or erroneous execution. When the SLE bit is in the logical “1” state, the Sector
Lockdown and Freeze Sector Lockdown State commands are enabled.
Unlike th e WEL bit, the SLE bit does n ot automatic ally reset after certain device operations. T herefore, o nce set,
the SLE bit w ill remain in the lo gical “1” state unt il it is modified using the Write Status Register Byte 2 command
or until the device has been power cycled. The Reset command has no effect on the SLE bit.
If the Fr eeze Sec t or Lock d own State c o mma nd has b een iss ued, then the SL E b it w il l b e p erma nently res et in t he
logical “0” state to indicate that the Sector Lockdown command has been disabled.
10.1.8. PS Bi t
The PS bit indicates whether or not a sector is in the Program Suspend state.
10.1.9. ES Bi t
The ES bit indicates whether or not a sector is in the Erase Suspend state.
10.1.10. RDY/BSY Bi t
The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in
progress . To po ll the RD Y / BSY b it to detect th e c omp l etio n of a pro gr am or eras e c yc le, new Stat us Reg is ter data
must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” to a
logical “0”.
Figure 10-1. Read Status Register
SO
SI
SCK
CS
MS B
2 310
00000101
6 754 10 1198 12 21 2217 20191815 1613 14 23 24 28 29272625 30
OP CODE
MS B MS B
DDDDDD DD
D
D
MS B
DDDDDD
D
DDD D
DDD
S TATUS R E G IS TE R
BYTE 1
S TATUS R E G IS TE R
BYTE 1
S TATUS R E G IS TE R
BYTE 2
HIG H -IMP E DANC E
38 Atmel AT25DF641
3680F–DFLASH–4/10
10.2. Write Status Register Byte 1
The Write Status Register Byte 1 command is used to modify the SPRL bit of the Status Register and/or to
perform a G lob al Protec t or Globa l Un pr otect o perat ion . Bef or e the Writ e St atus R egis ter Byte 1 c om ma nd c a n be
issued, t he Write Enab le comma nd mus t have been pr evious ly is sued to s et the WEL b it in the Status Regi ster to
a logical “1”.
To issue the Write Status Register Byte 1 command, the pin must first be asserted and the opcode of 01h
must be clock ed into t he de v ice foll owe d by one by te o f data. T h e one byte of data c ons ists of the SP RL b it v alue,
a don’t care bit, four data bits to denote whether a Global Protect or Unprotect should be performed, and two
additional don’t care bits (see Table 10-1). Any additional data bytes that are sent to the device will be ignored.
When the pin is deasserted, the SPRL bit in the Status Register will be modified, and the WEL bit in the Status
Register will be reset back to a logical “0”. The v alues of bits five, four, three, and two and the state of the SPRL
bit before the Write Stat us Regist er Byte 1 c om man d was ex ec uted (the prior s ta te of t he SP RL b it) wi ll det ermine
whether or not a Global Protec t or Global Unpr otect will be perf ormed. Please r efer to “ Global Protec t/Unpr otect”
on page 24 for more details.
The complete one byte of data must be clocked into the device before the pin is deasserted, and the pin
must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the
operation, the state of the SPRL bit will not change, no potential Global Protect or Unprotect will be performed,
and the WEL bit in the Status Register will be reset back to the logical “0” state.
If the pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made to reset the
SPRL bit to a logical “0” while the pin is asserted, then the Write Status Register Byte 1 command will be
ignored, and the WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the
SPRL bit to a logical “0”, the pin must be deasserted.
Table 10-3. Write Status Register Byte 1 Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi t 2 Bit 1 Bit 0
SPRL X Global Protect/Unprotect X X
Figure 10-2. Write Status Register Byte 1
SO
SI
SCK
CS
MS B
2 310
0000000
6 754
OP CODE
10 1198 14 151312
1
MS B
D X D D D D X X
S TATUS R E G IS TE R IN
BYTE 1
HIG H -IMP E DANC E
WP
WP
WP
CS
CS
CS
CS
Atmel AT25DF641
39
3680F–DFLASH–4/10
10.3. Write Status Register Byte 2
The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of the Status Register.
Using the Write Status Register Byte 2 command is th e only way to modify the RSTE and SLE bits in the Status
Register during normal device operation, and the SLE bit can only be modified if the sector lockdown state has
not been frozen. Before the Write Status Register Byte 2 command can be issued, the Write Enable command
must have been previously issued to set the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register Byte 2 command, the pin must first be asserted and the opcode of 31h
must be clocked into the device followed by one byte of data. The one byte of data consists of three don’t care
bits, the RSTE bit value, the SLE bit value, and three additional don’t care bits (see Table 10-1). Any additional
data bytes that are sent to the device will be ignored. When the pin is deasserted, the RSTE and SLE bits in
the Status R egis ter wi ll be mod ified, a nd the WEL bi t in the Status R egister will be r eset back to a lo gical “0” . The
SLE bit will only be modified if the Freeze Sector Lockdown State command has not been previously issued.
The complete one byte of data must be clocked into the device before the pin is deasserted, and the pin
must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the
operation , the s t ate of the R STE and SL E b its wil l n ot c hange, and the WE L b it i n the Stat us Reg ist er wi ll b e res et
back to the logical “0” state.
Table 10-4. Write Status Register Byte 2 Format
Bit 7 Bit 6 Bi t 5 Bit 4 Bit 3 Bi t 2 Bit 1 Bit 0
X X X RSTE SLE X X X
Figure 10-3. Write Status Register Byte 2
SO
SI
SCK
CS
MS B
2 310
0011000
6 754
OP CODE
10 1198 14 151312
1
MS B
X X X D D X X X
S TATUS R E G IS TE R IN
BYTE 2
HIG H -IMP E DANC E
CS
CS
CS
CS
40 Atmel AT25DF641
3680F–DFLASH–4/10
11. Other Com mands and Funct ions
11.1. Reset
In some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than
wait the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete
normally. T he Reset com mand all ows a progra m or eras e operation in progr ess to be ended abruptly an d returns
the devic e to an idle state. Since the need to reset t he device is imm ediate, th e Write E nable comm and does not
need to be issued prior to the Reset command being issued. Therefore, the Reset command operates
independently of the state of the WEL bit in the Status Register.
The Reset command can only be executed if the command has been enabled by setting the Reset Enabled
(RSTE) b it in the Status Regis ter to a log ical “1”. I f the Reset c ommand has not been e nabled (t he RST E bit is in
the logical “0” state), then any attempts at executing the Reset command will be ignored.
To perform a Reset, t he pin must first b e ass erted an d the o pcode of F 0h mus t be cloc ked into the d evice. No
address bytes nee d to be c locked in, but a co nfirmatio n byte of D 0h must be clock ed into the device im mediately
after the opc ode. A ny add itiona l data c locked i nto the d evice after the c onfirma tion byte wil l be ignor ed. Wh en the
pin is deass erted, the prog ram or eras e operation curr ently in progres s will be ter minated with in a time of tRST.
Since the progr a m or er as e operation may n ot complet e bef or e th e device is r eset, the co nten ts of th e pa ge being
programmed or the block being erased cannot be guaranteed to be valid.
The Reset command has no effect on the states of the Sector Protection Registers, the Sector Lockdown
Register s, or the SPRL, R STE, and SLE bits in the Status Re gister. The WEL, PS, and E S bits, however, will be
reset back to their default states. If a Reset operation is performed while a sector is erase suspended, the
suspend operati on wil l abor t, an d the co nte nts of t he b lock being erased in th e su spended s ector will be le ft i n an
undefined state. If a Reset is performed while a sector is program suspended, the suspend operation will abort,
and the contents of the page that was being programmed and subsequently suspended will be undefined. The
remaining pages in the 64-Kbyte sector will retain their previous contents.
The complete opc ode an d confirm ation by te must be clocked into th e devic e bef ore the pin is deasserte d, and
the pin must be deass erted on an even by te boundary (multiples of eight b its); otherwise, no Reset oper ation
will be performed.
Figure 11-1. Reset
SO
SI
SCK
CS
MS B
2 310
1111000
6 754
OP CODE CONF IR MATION BYTE IN
10 1198 14 151312
0
MS B
11010000
HIG H -IMP E DANC E
CS
CS
CS
CS
Atmel AT25DF641
41
3680F–DFLASH–4/10
11.2. Read Manufacturer and Device ID
Identification information can be read from the device to enable systems to electronically query and identify the
device w hi le it is in sy s tem . The identif icat ion met hod and t he c o mma nd opc od e c omply with the J ED EC s ta ndar d
for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The
type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor
specific Device ID, and the vendor specific Extended Device Information.
The Read Manufacturer and Device ID command is limited to a maximum clock frequency of fCLK. Since not all
Flash devices are capable of operating at very high clock frequencies, applications should be designed to read
the identif ication i nform atio n from th e devices a t a rea sonab ly low cl ock fr equency to ensure t hat all d evices to be
used in the applicatio n can be ident ified pr operly. Onc e the identi fication pr ocess is c omplete, the applicat ion can
then increase the clock frequency to accommodate specific Flash devices that are capable of operating at the
higher clock frequencies.
To read the identification information, the pin must first be asserted and the opcode of 9Fh must be clocked
into the device. After the opcode has been clocked in, the device will begin outputting the identification data on
the SO pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID
followed by two bytes of Device ID information. The fourth byte output will be the Extended Device Information
String Length, which will be 00h indicating that no Extended Device Information follows. After the Extended
Device Information String Length byte is output, the SO pin will go into a high-impedance state; therefore,
additional clock cycles will have no affect on the SO pin and no data will be output. As indicated in the JEDEC
standard, reading the Extended Device Information String Length and any subsequent data is optional.
Deasserting the pin will terminate the Manufacturer and Device ID read operation and put the SO pin into a
high-im pedance state. T he pin can b e deasserted at any time and does not req uire that a full byte of d ata be
read.
Table 11-1. Manufacturer and Device ID Information
Byte No. Data Type Value
1 Manufacturer ID 1Fh
2 Device ID (Part 1) 48h
3 Device ID (Part 2) 00h
4 Extended Device Information String Leng th 00h
Table 11-2. Manufacturer and Device ID Details
Data Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex
Value Details
Manufacturer ID JE DEC Assigned Code 1Fh JE DEC Code: 0001 1111 (1Fh for Atmel)
0 0 0 1 1 1 1 1
Device ID (Part 1) Family Code Density Code 48h Fami ly Code: 010 (A T25DF / 26DFxxx s eri es)
Density Code: 01000 (64-Mbit)
0 1 0 0 1 0 0 0
Device ID (Part 2) Sub Code Product Version Code 00h Sub Code: 000 (Standard series)
Product Version: 00000 (Ini tial version)
0 0 0 0 0 0 0 0
CS
CS
CS
42 Atmel AT25DF641
3680F–DFLASH–4/10
Figure 11-2. Read Manufacturer and Device ID
SO
SI
SCK
CS
60
9F h
87 38
OP C ODE
1F h 48h 00h 00h
MA NU F AC T UR E R ID DE VIC E ID
B Y T E 1
DE V IC E ID
B Y T E 2
E XTE NDE D
DE V IC E
IN F OR MAT IO N
S TR ING L E N G TH
HIG H -IMP E DANC E
14 1615 22 2423 30 3231
Note: Each transition shown for SI and SO represents one byte (8-bits).
Atmel AT25DF641
43
3680F–DFLASH–4/10
11.3. Deep Power-Down
During norma l oper ation, the dev ice wil l be place d in the s tandby mod e to cons ume less power as long as the
pin remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the
ability to place the device into an even lower power consumption state called the Deep Power-Dow n mod e.
When the device is in the Deep Power-D own mode, all comma nds including the Read Status Regis ter command
will be ignor ed with the exc eption of the Res ume from Deep Pow er-Down com mand. Since al l commands wil l be
ignored, the mode can be used as an extra protection mechanism against program and erase operations.
Entering the Deep Pow er-Down mode is accomplished by simply asserting the pin, clocking in the opcode of
B9h, and then deasserting the pin. Any additional data clocked into the device after the opcode will be
ignored. When the pin is deasserted, the device will enter the Deep Power-Down mode within the maximum
time of tEDPD.
The comple te opc ode m ust be c lock ed in b efore the pin is deas serted, and the pin must be d eass erted o n
an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the
standby mode once the pin is deasserted. In addition, the device will default to the standby mode after a
power-cycle.
The Deep Power-Dow n comma nd will be ignored if an i nternally self-time d operatio n such as a progr am or eras e
cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation
has been completed in order for the device to enter the Deep Power-Down mode.
Figure 11-3. Deep Power-Down
SO
SI
SCK
CS
MS B
2 310
10111001
6 754
OP C ODE
HIG H -IMP E DANC E
S tandby Mode C urrent
Active C urrent
Deep P ower-Down Mode C urrent
t
E D P D
I
CC
CS
CS
CS
CS
CS
CS
CS
44 Atmel AT25DF641
3680F–DFLASH–4/10
11.4. Resume from Deep Power-Down
In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-
Down command must be issued. The Resume from Deep Power-Down command is the only command that the
device will recognized while in the Deep Power-Down mode .
To resume from the Deep Power-Down mode, the pin must first be asserted and opcode of ABh must be
clocked i nto t he dev ice. An y addi tio na l dat a cl oc k ed in t o th e device af ter th e opco de w il l be ignor e d. Whe n th e
pin is deassert ed, t he dev ice wi ll exi t the D eep Power -Down mo de w ithin the m aximum t ime of tRDPD and return to
the standby mode . After th e dev ice has retur ne d to th e s tandby mo de, normal co mma nd op erati ons s uch as Read
Array can be resumed.
If the complete o pcode is not clock ed in before the pin is deas serted, or if the pin is not de asserted on an
even byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep
Power-Down mode.
Figure 11-4. Resume from Deep Power-Down
SO
SI
SCK
CS
I
CC
MS B
2 310
10101011
6 754
OP C ODE
HIG H -IMP E DANC E
Deep P ower-Down Mode C urrent
Active C urrent
S tandby Mode C urrent
t
R DP D
CS
CS
CS
CS
Atmel AT25DF641
45
3680F–DFLASH–4/10
11.5. Hold
The pin is used t o pause t he serial com municat ion with the device wit hout hav ing to sto p or reset t he clock
sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a
program or erase cycle. Therefore, if an erase cycle is in progress, asserting the pin will not pause the
operation, and the erase cycle will continue until it is finished.
The Hold mode c an o nly b e enter ed wh ile th e pin is as serted. Th e H old m ode is activate d sim ply by asser ting
the pin during the SCK low pulse. If the pin is asserted during the SCK high pulse, then the Hold
mode wo n’t be star ted unti l the be ginning of the next SCK l ow pulse . The dev ice wi ll remain in the H old mode as
long as the pin and pin are asserted.
While in t he Hol d m ode, th e SO p in w ill b e i n a hi gh-i mped anc e sta t e. I n ad di tio n, bot h th e S I p in a nd t he S CK p in
will be ignored. The pin, however, can still be asserted or deasserted while in the Hold mode.
To end the Hold mode and resume ser ial communication, the pin must be deasserted during the SCK low
pulse. If the pin is deas ser ted dur ing the SC K high p uls e, then the Ho ld mo de w on’t end un til the beginn ing
of the next SCK low pulse.
If the pin is de ass erted wh ile th e pin is still as serted, t hen a ny opera tion th at may have been s tarte d will
be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state.
Figure 11-5. Hold Mode
HOLD
SCK
CS
Hold HoldHold
WP
CS
CS
CS
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
46 Atmel AT25DF641
3680F–DFLASH–4/10
12. Atmel RapidS Implementation
To implement Atmel® RapidS and operate at c loc k fr equencies hig her than what c an be ac hieve d in a v iable SPI
implementation, a full clock cycle can be used to transmit data back and forth across the serial bus. The Atmel
AT25DF641 is des igne d t o alway s c loc k its da ta o ut on the falling edg e of t he SCK s ignal an d c lock dat a in on the
rising edge of SCK.
For full clock cycle operation to be achieved, when the AT25DF641 is clocking data out on the falling edge of
SCK, the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host
controller should c lock its d ata out on the ris ing edge of SCK in or der to g ive the AT25D F641 a f ull clock cycle t o
latch the incoming data in on the next rising edge of SCK.
Implementing RapidS allows a system to run at higher clock frequencies since a full clock cycle is used to
accommo date a dev ice’s cl ock-to-output time, input setup time , and ass ociated r ise/fall t imes. For example, if the
system clock frequency is 100MHz (10ns cycle time) with a 50% duty cycle, and the host controller h as an input
setup time of 2ns, then a standard SPI implementation would require that the slave device be capable of
outputting its data in less than 3ns to m eet the 2ns host contr oller setup t ime [(10ns x 50%) - 2ns] not accounting
for rise/f all times. In an SPI mode 0 or 3 implem entation, the SPI master is designed to clock in dat a on the next
immediate rising edge of SCK after the SPI slave has clocked its data out on the preceding falling edge. This
essentially makes SPI a half-clock cycle protocol and requires extremely fast clock-to-output times and input
setup times in order to run at high c l oc k fr equ enc ies. Wit h a Rapid S i mp lement a t ion of th i s exa mpl e, h ow ev er , the
full 10ns cycle time is availabl e which gives the slav e device up to 8ns, n ot accounti ng for rise/fall times , to clock
its data out . L ik ewise, wit h Rapi dS, the hos t c ontr ol ler has mor e t im e av a ilabl e to outp ut its d ata t o t h e slav e s ince
the slave device would be clocking that data in a full clock cycle later.
Figure 12-1. RapidS Operation
MOSI
MISO
SCK
Slave CS
t
V
12 3 4 5 6 7 8 1 2345678
ABC D E
FG
1
H
BYTE A
MSB LSB
BYTE B
MSB LSB
I
MOSI = Master Out, Slave In MISO = M aster In, Slave Out
The Master is the ASIC/MCU and the Slave is the memory device.
The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
A. Master clocks out first bit of BYTE A on the rising edge of SCK
B. Slave clocks in first bit of BYTE A on the next rising edge of SCK
C. Master clocks out s econd bit of BYTE A on the same rising edge of SCK
D. Last bit of BYTE A is clocked out from the Master
E. Last bit of BYTE A is clocked into the slave
F. Slave clocks out first bit of BYTE B
G. Master clo cks in firs t b it of BYT E B
H. Slave clocks out second bit of BYTE B
I. Master clocks in last bit of BYTE B
Atmel AT25DF641
47
3680F–DFLASH–4/10
13. Electrical Specifications
13.1. Absolute Maximum Ratings*
Temperature under Bias ......................... −55°C to +125°C
Storage Temperature ........................... −65°C to + 150°C
All Input Voltages (inc l udi ng NC Pins)
with Respect to Ground ............................... − 0.6 V +4.1V
All Output Voltages
with Respect to Ground .................... − 0.6 V to VCC +0.5V
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions beyond those indicated in
the operational sections of this specification are
not
implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
13.2. DC and AC Operating Range
Atmel AT25DF641
Operating Temperature (Case) Ind. -40°C to 85°C
VCC Power Supply 2.7V to 3.6V
13.3. DC Characteristics
Symbol Parameter Condition Min Typ Max Units
ISB Standby Current , , = VCC,
all inputs at CMOS levels 25 50 µA
IDPD Deep Power-down Current , , = VCC,
all inputs at CMOS levels 15 25 µA
ICC1 Active Current, Read Operation
f = 75MHz; IOUT = 0mA;
= VIL, VCC = Max 13 17
mA
f = 66MHz; IOUT = 0mA;
= VIL, VCC = Max 12 14
f = 50MHz; IOUT = 0mA;
= VIL, VCC = Max 11 13
f = 33MHz; IOUT = 0mA;
= VIL, VCC = Max 10 12
f = 20MHz; IOUT = 0mA;
= VIL, VCC = Max 9 11
ICC2 Active Current, Program Operation = VCC, VCC = Max 12 18 mA
ICC3 Active Current, Erase Operation = VCC, VCC = Max 12 18 mA
ILI Input Lea kag e Curre nt VIN = CMOS levels 1
µ
A
ILO Output Leakage Current VOUT = CMOS levels 1 µA
VIL Input Low Voltage 0.3 x VCC V
VIH Input High Voltage 0.7 x VCC V
V
OL
Output Low Voltage
I
OL
= 1. 6mA; V
CC
= Min
0.4
V
VOH Output High Voltage IOH = -100 µA; VCC = Min VCC - 0.2V
V
WP
WP
CS
CS
CS
CS
CS
CS
CS
CS
CS
HOLD
HOLD
48 Atmel AT25DF641
3680F–DFLASH–4/10
13.4. AC Characteristics - Maximum Clock Frequencies
Symbol
Parameter
Min
Max
Units
Atmel RapidS and SPI Operation
fMAX Maximum Clock Frequency for All Operations – Atmel RapidS Operation Only
(excluding 0Bh, 03h, 3Bh, and 9F opcodes) 100 MHz
fCLK Maximum Clock Frequency for All Operations
(excluding 03h and 3Bh opc odes) 75 MHz
fRDLF Maximum Clock Frequency for 03h Opcode (Read Array – Low Frequency) 45 MHz
fRDDO Maximum Clock Frequency for 3Bh Opcode (Dual-Output Read) 55 MHz
13.5. AC Characteristics – All Other Parame ters
Symbol
Parameter Min Max Units
tCLKH Clock High Time 4.3 ns
tCLKL Clock Low Time 4.3 ns
tCLKR(1) Clock Rise Time, Peak-to-Peak (Slew Rate) 0.1 V/ns
tCLKF(1) Clock Fall Time, Peak-to-Peak (Slew Rate) 0.1 V/ns
tCSH Chip Select High Time 50 ns
tCSLS Chip Select Low Setup Time (relative to Clock) 5 ns
t
CSLH
Chip Select Low Hold Time
(relative to Clock)
5
ns
tCSHS Chip Select High Setup Time (relative to Clock) 5 ns
tCSHH Chip Select High Hold Time (rel ative t o Clock) 5 ns
t
DS
Data In Setup Time
2
ns
tDH Data In Hold Time 1 ns
tDIS(1) Output Disable Time 5 ns
tV(2) Output Valid Tim e 5 ns
tOH Output Hold Time 2 ns
tHLS Low Setup Time (relative to Clock) 5 ns
tHLH Low Hold Time (r elative to Clock) 5 ns
tHHS High Setup Time (relative to Clock) 5 ns
tHHH
High Hold Time (re la t ive t o Clock) 5 ns
tHLQZ(1) Low to Output High-Z 5 ns
tHHQX(1) High to Output Low-Z 5 ns
tWPS(1)(3) Write Protect Setup Time 20 ns
tWPH(1)(3) Write Protect Hold Time 100 ns
tSECP(1) Sector Protect Time (from Chip Select High) 20 ns
tSECUP(1) Sector Unpr ot ect Tim e (from Chip Select High) 20 ns
tLOCK(1) Sector Lockd own and Fre eze Sector Loc kd ow n Stat e Time (from Chip Select High) 200 µs
t
EDPD
(1)
Chip Select High to Deep Power-Down
1
µs
tRDPD(1) Chip Select High to Standby Mode 30 µs
tRST Reset Time 30 µs
Notes: 1. Not 100% tested (value guaranteed by design and characterization)
2. 15pF load at frequencies above 70MHz, 30pF otherw ise
3. Only applicable as a constraint for the Write Status Register Byte 1 command when SPRL = 1
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
Atmel AT25DF641
49
3680F–DFLASH–4/10
13.6. Program and Erase Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tPP(1) Page Program Time (256 Bytes) 1.0 3.0 ms
tBP Byte Program Time 7 µs
tBLKE(1) Block Erase Time
4-Kbytes
50
200
ms 32-Kbytes 250 600
64-Kbytes 400 950
t
CHPE
(1)(2)
Chip Erase Time
64
112
sec
tSUSP Program/Erase Suspend Time 10 20 µs
tRES Program/Erase Resume Time 10 20 µs
tOTPP(1) OTP Sec urity Register Program Time 200 500 µs
t
WRSR
(2)
Write Status Register Time
200
ns
Notes: 1. Maximum values indicate worst-case performance after 100,000 erase/program cycles
2. Not 100% tested (value guaranteed by design and characterization)
13.7. Power-up Conditions
Symbol Parameter Min Max Units
tVCSL Minimum VCC to Chip Select Low Time 50 µs
tPUW Power-up Device Delay Before Program or Erase Allowed 10 ms
V
POR
Power-on Reset Voltage
1.5
2.5
V
13.8. Input Test Waveforms and Measurement Levels
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.1VCC
VCC/2
0.9VCC
tR, tF< 2 ns (10% to 90%)
13.9. Output Test Load
DEVICE
UNDER
TEST 15pF (frequencies above 70MHz)
or
30pF
50 Atmel AT25DF641
3680F–DFLASH–4/10
14. AC Wavefor m s
Figure 14-1. Serial Input Timing
SO
SI
SCK
CS
MS B
HIG H -IMP E DANC E
MS BLS B
t
C S L S
t
C L K H
t
C L K L
t
C S H S
t
C S H H
t
DS
t
DH
t
C S L H
t
C S H
Figure 14-2. Serial Output Timing
SO
SI
SCK
CS
t
V
t
C L K H
t
C L K L
t
DIS
t
V
t
OH
Figure 14-3. WP Timing for Write Status Register Byte 1 Command When SPRL = 1
SO
SI
SCK
WP
CS
000
HIG H -IMP E DANC E
MS BX
t
W P S
t
W P H
LS B O F
WR IT E S T AT US R E G IS T E R
DAT A B Y T E
MS B O F
WR IT E S T AT US R E G IS T E R
B Y T E 1 OP C O DE
MS B O F
NE X T O P C ODE
Atmel AT25DF641
51
3680F–DFLASH–4/10
Figure 14-4. HOLD Timing – Serial Input
SO
SI
HOLD
SCK
CS
t
HHH
t
HLS
t
HLH
t
HHS
HIG H -IMP E DANC E
Figure 14-5. HOLD Timing – Serial Output
SO
SI
HOLD
SCK
CS
t
HHH
t
HLS
t
HLQZ
t
HLH
t
HHS
t
HHQX
52 Atmel AT25DF641
3680F–DFLASH–4/10
15. Orderi ng Informati on
15.1. Ordering Code Detail
Atmel Designator
Product Family
Device Density
Interface
Shipping Carrier Option
Device Grade
Package Option
64 = 64-megabit
1 = Serial
B = Bulk (tubes)
Y = Bulk (trays)
T = Tape and reel
H = Green, NiPdAu lead finish,
Industrial Temperature range
-40°C to +85°C
S3 = 16-lead, 0.300” wide SOIC
MW= 8-contract, 6mm x 8mm VDFN
AT25DF641-S3H-B
15.2. Green Package Options (Pb/Halide-free/RoHS Compliant)
Ordering Code Package Lead
Finish Voltage Max. Freq.
(MHz) Operating Range
AT25DF641-S3H-B
AT25DF641-S3H-T 16S NiPdAu 2.7V to 3.6V 75 Industrial Temperature
(−40°C to 85°C)
AT25DF641-MWH-Y
AT25DF641-MWH-T 8MW1
Note: The shipping carrier option code is not marked on the devices
Package Type
16S
16-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)
8MW1
8-contact, 6 x 8mm, Very Thin Dual Flat No Lead Package (VDFN)
Atmel AT25DF641
53
3680F–DFLASH–4/10
16. Packaging Information
16S – SOIC
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV.TITLE
Notes: 1. This drawing is for general information only; refer to
JEDEC Drawing MS-013, Variation AA for additional
information.
2. Dimension D does not include mold Flash, protrusions
or gate burrs. Mold Flash, protrusion and gate burrs
shall not exceed 0.15 mm (0.006") per side.
3. Dimension E does not include inter-lead Flash or
protrusion. Inter-lead flash and protrusions shall not
exceed 0.25 mm (0.010") per side.
4. L is the length of the terminal for soldering to a
substrate.
16S A
11/02/05
16S, 16-lead, 0.300" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
End View
Top View
Side View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
2.35
0.10
0.31
0.40
0.20
A
A1
b
D
E
H
L
e
C
–
–
–
10.30 BSC
7.50 BSC
10.30 BSC
–
1.27 BSC
2.65
0.30
0.51
1.27
0.33
2
3
4
H
E
N
1
A1
b
e
A
D
E
L
C
54 Atmel AT25DF641
3680F–DFLASH–4/10
8MW1 – VDFN
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV.TITLE
8MW1 E
1/12/09
8MW1, 8-pad (6 x 8 x 1.0 mm Body), Thermally
Enhanced Plastic Very Thin Dual Flat No Lead
Package (VDFN)
Bottom View
Top View
Side View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
0.80
–
0.35
5.90
4.70
7.90
4.80
0.45
A
A1
b
C
D
D1
E
E1
e
L
K
–
–
0.40
0.203 REF
6.00
4.80
8.00
4.90
1.27
0.50
1.05 REF
1.00
0.05
0.48
6.10
4.90
8.10
5.00
0.55
Pin 1 ID
E
D
A1
A
C
Pin #1 ID
E1
D1
L
b
e
K
1Pin #1
Chamfer
(C 0.30)
Option A
Pin #1
Notch
(0.20 R)
Option B
2
3
4
8
7
6
5
Atmel AT25DF641
55
3680F–DFLASH–4/10
17. Revision Histor y
Doc. Rev.
Date
Comments
3680F 04/2010 Changed Deep Power Down Current
– Increased typical val ue from 5µA to 1 5µA
– Increased max value from 10µA to 25µA
Changed Active Current, Read Operation
– Removed ICC1 for 100MHz
– Decreased ICC1 frequency f rom 85MHz to 75MHz
– Increased typical ICC1 value from 10mA to 13mA
– Increased typical ICC1 value for 66MHz from 8mA to 12mA
– Increased typical ICC1 value for 50MHz from 7mA to 11mA and max value from 12mA to 13mA
– Increased typical ICC1 value for 33MHz from 6mA to 10mA and max value from 10mA to 12mA
– Increased typical ICC1 value for 20MHz from 5mA to 9mA and max value from 8mA to 11mA
Changed the Read Array frequencies
– 1Bh command: Decreased max value from 100MHz to 75MHz
– 0Bh command: Decreased max value from 85MHz to 75MHz
– 03h command: Decreased max value from 50MHz to 45MHz
– 3Bh command: Decreased max value from 85MHz to 55MHz
Removed “Preliminary” status from datasheet
Removed the Errata section
3680E
12/2008
Changed Standby Current value
– Increased maximum value from 35µA to 50µA
Changed Deep Power-Down Current values
– Increased typical val ue from 1µA to 5µA
– Increased maximum value from 5µA to 10µA
3680D 11/2008 Added Errat a (Secti on 18) regarding Eras e Suspend and AC Characteristi cs
Corrected clock frequency values in T abl e 5-1
3680C 06/2008 Replaced t he technic al illustration (16S2) with the correct one (16S) on page 53
3680B
02/2008
Minor text edits throughout document
Changed Standby Current values
– Increased typical val ue from 10µA to 2 5µA
– Increased maximum value from 20µA to 35µA
Changed minimum Clock High Time and minimum Clock Low Time from 3.7ns to 4.3ns
3680A
12/2007
Initi al document release
3680F–DFLASH–4/10
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