TTL Logic Diagrams (cont'd) Diag. 61 ECG74H71 14-Pin DIP See Fig. D6 KiB KIA OG vi CK K2B K2A full Gated J-K M/S Flip-Flop with Preset Diag. 62 ECG7472, ECG74H72 Gated J-K M/S Flip-Flop with Preset. and Clear 14-Pin DIP See Fig. D6 | Diag. 63 (See also Diag. 64) ECG7473, ECG74H73 14-Pin DIP See Fig. D6 13 14 10 GND 2K 20 26 131] 2 " a 8 Dual J-K M/S Flip-Flop with Clear Diag. 64 (See also Diag. 63) ECG74C73, ECG74LS73 14-Pin DIP See Fig. D6 10 GND 2k 2a 20 * 3 a " 8 s a a a Q . cus cua : $ ) eX [os . - 3 s 7 1CK 1 mK oa 2cK a CLA Dual J-K Negative Edge Triggered Flip-Flop with Clear Diag. 65 14-Pin DIP See Fig. D6 ECG7474, ECG74C74, ECG74H74, IECG74LS74A, ECG74S74 CLR Dual D Flip-Flop with Preset and Clear Diag. 66 16-Pin DIP See Fig. D8 ECG7475, ECG74LS75 ENASLE 12 GNI 4-Bit Bistable Latch with Complementary Outputs Diag. 67 (See also Diag. 68) ECG7476", ECG74H76 16-Pin DIP See Fig. D8 1K 1a 10. GNO 2K 2a 20 20 1 % 14h] taf 2 " 8 1 2 3 4 e 7 8 1CK TPR 1 Wo Vee: 26K 2PR 2 CLR ciR Dual J-K M/S Flip-Flop with Preset and Diag. 68 16-Pin DIP See Fig. D8 (See also Diag. 67) ECG74C76, ECG74LS76A Tek TPR 1 WF Voc 20K 2PR 2 cLR CLR Dual J-K. Negative Edge Triggered Flip-Flop Diag. 69 ECG74LS77 14-Pin DIP See Fig. D6 enaac O12) GND Veg PPR CLR 2) 2PR CK 2K " 431 4 12 n % a cope BD a ao T_T i iefisfisFsreh2 Dual J-K M/S Flip-Flop with Presets and a Common Clock and Clear Clear *Discontinued | with Preset and Clear 4-Bit Bistable Latch Diag. 70 14-Pin DIP See Fig. D6 | Diag. 71 14-Pin DIP See Fig. D6 | Diag. 72 14-Pin DIP See Fig. D6 (See also Diag. 71) (See also Diag. 70) ECG7480 ECG74H78 ECG74LS78 Vcc 82 BI AG AS AZ Al 1K 1a 14 GND 243 20 2a 134] 12 " " 8 a [>] PR PR | a 3 a ropck ET K a k CLR [| CLR e 1 | | 1 2 3 a 5 6 7 CK TPR W Vcc CLR 2PR 2K Dual J-K Negative Edge Triggered Flip-Flop with Presets and a Common Clock and Clear 1 vel ew be Gated Full Adder with Complementary Sum Outputs Package Outlines - See Page 1-357