DC1402A-A - Linear Technology - Datasheet.Directory

LTC3577/LTC3577-1

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TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Highly Integrated

6-Channel Portable PMIC

The LTC

3577 is a highly integrated power management

IC for single cell Li-Ion/Polymer battery applications. It

includes a PowerPath manager with automatic load priori-

tization, a battery charger, an ideal diode, input overvoltage

protection and numerous other internal protection features.

The LTC3577 is designed to accurately charge from current

limited supplies such as USB by automatically reducing

charge current such that the sum of the load current and

the charge current does not exceed the programmed input

current limit (100mA or 500mA modes). The LTC3577

reduces the battery voltage at elevated temperatures to

improve safety and reliability. Efﬁ cient high current charg-

ing from supplies up to 38V is available using the on-chip

Bat-Track controller. The LTC3577 also includes a push-

button input to control the three synchronous step-down

switching regulators and system reset. The onboard LED

backlight boost circuitry can drive up to 10 series LEDs

and includes versatile digital dimming via I2C input. The

I2C input also controls two 150mA LDOs as well as other

operating modes and status read back. The LTC3577 is

available in a low proﬁ le 4mm × 7mm × 0.75mm 44-pin

QFN package.

LED Driver Efﬁ ciency (10 LEDs)

n Full Featured Li-Ion/Polymer Charger/PowerPath™

Controller with Instant-On Operation

n Triple Adjustable High Efﬁ ciency Step-Down

Switching Regulators (800mA, 500mA, 500mA IOUT)

n 6µA Battery Drain Current in Hard Reset

n Bat-Track™ Control for External HV Buck DC/DCs

n I2C Adjustable SW Slew Rates for EMI Reduction

n High Temperature Battery Voltage Reduction

Improves Safety and Reliability

n Overvoltage Protection for USB (VBUS)/Wall Inputs

Provides Protection to 30V

n Integrated 40V Series LED Backlight Driver with 60dB

Brightness Control and Gradation via I2C

n 1.5A Maximum Charge Current with Thermal Limiting

n Battery Float Voltage: 4.2V (LTC3577)

4.1V (LTC3577-1)

n Pushbutton On/Off Control with System Reset

n Dual 150mA Current Limited LDOs

n Small 4mm × 7mm 44-Pin QFN Package

n PNDs, DMB/DVB-H; Digital/Satellite Radio;

Media Players

n Portable Industrial/Medical Products

n Universal Remotes, Photo Viewers

n Other USB-Based Handheld Products

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

PowerPath and Bat-Track are trademarks of Linear Technology Corporation. All other trademarks

are the property of their respective owners. Protected by U.S. Patents including 6522118,

6700364, 7511390, 5481178, 6580258. Other Patents Pending.

100mA/500mA

1000mA

HV SUPPLY

8V TO 38V

(TRANSIENTS TO 60V)

USB

CHARGE

CC/CV

CHARGER

LED BACKLIGHT WITH DIGITALLY

CONTROLLED DIMMING

DUAL LDO

REGULATORS

LTC3577/LTC3577-1

TRIPLE HIGH EFFICIENCY

STEP-DOWN SWITCHING

REGULATORS WITH

PUSHBUTTON CONTROL

HIGH VOLTAGE

BUCK DC/DC

SINGLE CELL

Li-Ion

UP TO 10 LED

BOOST

VOUT

0.8V to 3.6V/800mA

0.8V to 3.6V/150mA

0.8V to 3.6V/500mA

NTC

I2C PORT

3577 TA01a

OVERVOLTAGE

PROTECTION

OPTIONAL

LED CURRENT (A)

EFFICIENCY (%)

1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01

3577 TA01b

MAX PWM CONSTANT

CURRENT

LTC3577/LTC3577-1

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TABLE OF CONTENTS

Features ............................................................................................................................ 1

Applications ....................................................................................................................... 1

Typical Application ............................................................................................................... 1

Description......................................................................................................................... 1

Absolute Maximum Ratings ..................................................................................................... 3

Order Information ................................................................................................................. 3

Pin Conﬁ guration ................................................................................................................. 3

Electrical Characteristics ........................................................................................................ 4

Typical Performance Characteristics .........................................................................................10

Pin Functions .....................................................................................................................16

Block Diagram ....................................................................................................................19

PowerPath Operation ............................................................................................................................................ 20

Low Dropout Linear Regulator Operation ............................................................................................................. 30

Step-Down Switching Regulator Operation ........................................................................................................... 31

LED Backlight/Boost Operation ............................................................................................................................. 35

I2C Operation ........................................................................................................................................................ 38

Pushbutton Interface Operation ............................................................................................................................ 43

Layout and Thermal Considerations ..................................................................................................................... 48

Typical Applications .............................................................................................................50

Package Description ............................................................................................................52

Related Parts .....................................................................................................................53

Revision History .................................................................................................................54

LTC3577/LTC3577-1

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PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

VSW ............................................................ –0.3V to 45V

VBUS, VOUT

, VIN12, VIN3, VINLDO1, VINLDO2, WALL

t < 1ms and Duty Cycle < 1% ................... –0.3V to 7V

Steady State ............................................ –0.3V to 6V

CHRG, BAT, LED_FS, LED_OV, PWR_ON, WAKE,

PBSTAT, PG_DCDC, FB1, FB2, FB3, LDO1, LDO1_FB,

LDO2, LDO2_FB, DVCC, SCL, SDA ............... –0.3V to 6V

NTC, PROG, CLPROG, ON, ILIM0, ILIM1

(Note 4) ........................................... –0.3V to VCC + 0.3V

IVBUS, IVOUT

, IBAT, Continuous (Note 16) .....................2A

ISW3, Continuous (Note 16) ................................. 850mA

ISW2, ISW1, Continuous (Note 16) ........................ 600mA

ILDO1, ILDO2, Continuous (Note 16) ..................... 200mA

ICHRG, IACPR, IWAKE, IPBSTAT, IPG_DCDC ................... 75m A

IOVSENS ..................................................................10mA

ICLPROG, IPROG, ILED_FS, ILED_OV ..............................2mA

Junction Temperature ............................................110°C

Operating Temperature Range .................–40°C to 85°C

Storage Temperature Range .................. –65°C to 125°C

(Notes 1, 2, 3)

TOP VIEW

GND

UFF PACKAGE

44-LEAD (7mm s 4mm) PLASTIC QFN

ILIM0 1

ILIM1 2

LED_FS 3

WALL 4

SW3 5

VIN3 6

FB3 7

OVSENS 8

LED_OV 9

DVCC 10

SDA 11

SCL 12

OVGATE 13

PWR_ON 14

ON 15

37 IDGATE

36 PROG

35 NTC

34 NTCBIAS

33 SW1

32 VIN12

31 SW2

30 VINLD02

29 LDO2

28 LDO1

27 LDO1_FB

26 FB1

25 FB2

24 LDO2_FB

23 VINLDO1

PBSTAT 16

WAKE 17

SW 18

SW 19

SW 20

PG_DCDC 21

ILED 22

44 CHRG

43 CLPROG

42 VC

41 ACPR

40 VBUS

39 VOUT

38 BAT

TJMAX = 110°C, θJA = 45°C/W

EXPOSED PAD (PIN 45) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3577EUFF#PBF LTC3577EUFF#TRPBF 3577 44-Lead (4mm × 7mm) Plastic QFN –40°C to 85°C

LTC3577EUFF-1#PBF LTC3577EUFF-1#TRPBF 35771 44-Lead (4mm × 7mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

LTC3577/LTC3577-1

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ELECTRICAL CHARACTERISTICS

Power Manager. The l denotes the speciﬁ cations which apply over the

full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = WALL = 0V,

VINLDO1 = VINLDO2 = VIN12 = VIN3 = VOUT

, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Power Supply

BUS

Input Supply Voltage 4.35 5.5 V

BUS(LIM)

Total Input Current (Note 5) ILIM0 = 0V, ILIM1 = 0V (1x Mode)

ILIM0 = 5V, ILIM1 = 5V (5x Mode)

ILIM0 = 5V, ILIM1 = 0V (10x Mode)

450

900

475

950

100

500

1000

BUSQ

Input Quiescent Current, POFF State 1x, 5x, 10x Modes

ILIM0 = 0V, ILIM1 = 5V (Suspend Mode) 0.42

0.042 0.1 mA

CLPROG

Ratio of Measured VBUS Current to

CLPROG Program Current 1000 mA/mA

CLPROG

CLPROG Servo Voltage in Current

Limit 1x Mode

5x Mode

10x Mode

0.2

1.0

2.0

UVLO

BUS

Undervoltage Lockout Rising Threshold

Falling Threshold 3.5 3.8

3.7 3.9 V

DUVLO

BUS

to V

OUT

Differential Undervoltage

Lockout Rising Threshold

Falling Threshold 50

–50 100 mV

ON_ILIM

Input Current Limit Power FET On-

Resistance (Between V

BUS

and V

OUT

)200 mΩ

Battery Charger

FLOAT

BAT

Regulated Output Voltage LTC3577

LTC3577, 0 ≤ T

≤ 85°C

LTC3577-1

LTC3577-1, 0 ≤ T

≤ 85°C

4.179

4.165

4.079

4.065

4.200

4.100

4.221

4.235

4.121

4.135

ICHG

Constant-Current Mode Charge Current R

PROG

= 1k, Input Current Limit = 2A

PROG

= 2k, Input Current Limit = 1A

PROG

= 5k, Input Current Limit = 0.4A

950

465

180

1000

500

200

1050

535

220

IBATQ_HR

Battery Drain Current, Hard Reset V

BUS

= 0V, I

OUT

= 0µA 7 15 µA

IBATQ_OFF

Battery Drain Current, POFF State V

BAT

= 4.3V, Charger Time Out

BUS

= 0V 6

40 27

100 µA

µA

IBATQ_ON

Battery Drain Current, PON State

LDOs, and LED Backlight Disabled VBUS = 0V, IOUT = 0µA, No Load on

Supplies, Burst Mode Operation (Note 10) 90 160 µA

PROG,CHG

PROG Pin Servo Voltage V

BAT

> V

TRKL

1.000 V

PROG,TRKL

PROG Pin Servo Voltage in Trickle

Charge V

BAT

< V

TRKL

0.100 V

PROG

Ratio of I

BAT

to PROG Pin Current 1000 mA/mA

TRKL

Trickle Charge Current V

BAT

< V

TRKL

40 50 60 mA

TRKL

Trickle Charge Rising Threshold

Trickle Charge Falling Threshold V

BAT

Rising

BAT

Falling 2.5 2.85

2.75 3.0 V

ΔV

RECHRG

Recharge Battery Threshold Voltage Threshold Voltage Relative to V

FLOAT

–75 –100 –125 mV

TERM

Safety Timer Termination Period Timer Starts When V

BAT

= V

FLOAT

– 50mV 3.2 4 4.8 Hour

BADBAT

Bad Battery Termination Time V

BAT

< V

TRKL

0.4 0.5 0.6 Hour

C/10

End-of-Charge Indication Current Ratio (Note 6) 0.085 0.1 0.11 mA/mA

ON_CHG

Battery Charger Power FET On-

Resistance (Between VOUT and BAT) 200 mΩ

LIM

Junction Temperature in Constant

Temperature Mode 110 °C

LTC3577/LTC3577-1

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ELECTRICAL CHARACTERISTICS

Power Manager. The l denotes the speciﬁ cations which apply over the

full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = WALL = 0V,

VINLDO1 = VINLDO2 = VIN12 = VIN3 = VOUT

, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

NTC, Battery Discharge Protection

COLD

Cold Temperature Fault Threshold

Voltage Rising NTC Voltage

Hysteresis 75 76

1.3 77 %V

NTCBIAS

VHOT Hot Temperature Fault Threshold

Voltage Falling NTC Voltage

Hysteresis 34 35

1.3 36 %V

NTCBIAS

V2HOT NTC Discharge Threshold Voltage Falling NTC Voltage

Hysteresis 24.5 25.5

50 26.5 %V

NTCBIAS

INTC NTC Leakage Current VNTC = VBUS = 5V –50 50 nA

IBAT2HOT BAT Discharge Current VBAT = 4.1V, NTC < VTOO_HOT 180 mA

VBAT2HOT BAT Discharge Threshold IBAT < 0.1mA, NTC < VTOO_HOT 3.9 V

Ideal Diode

VFWD Forward Voltage Detection IOUT = 10mA 5 15 25 mV

RDROPOUT Diode On-Resistance, Dropout IOUT = 200mA 200 mΩ

IMAX Diode Current Limit (Note 7) 3.6 A

Overvoltage Protection

VOVCUTOFF Overvoltage Protection Threshold Rising Threshold, ROVSENS = 6.2k 6.10 6.35 6.70 V

VOVGATE OVGATE Output Voltage Input Below VOVCUTOFF

Input Above VOVCUTOFF

1.88 • VOVSENS 12

IOVSENSQ OVSENS Quiescent Current VOVSENS = 5V 40 µA

tRISE OVGATE Time to Reach Regulation COVGATE = 1nF 2.5 ms

Wall Adapter

VACPR ACPR Pin Output High Voltage

ACPR Pin Output Low Voltage IACPR = 0.1mA

IACPR = 1mA VOUT – 0.3 VOUT

0 0.3 V

VWAbsolute Wall Input Threshold Voltage VWALL Rising

VWALL Falling 3.1 4.3

3.2 4.45 V

ΔVWDifferential Wall Input Threshold

Voltage VWALL – VBAT Falling

VWALL – VBAT Rising 025

75 100 mV

IQWALL Wall Operating Quiescent Current IWALL + IVOUT

, IBAT = 0mA,

WALL = VOUT = 5V 440 µA

Logic (ILIM0, ILIM1 and CHRG)

VIL Input Low Voltage ILIM0, ILIM1 0.4 V

VIH Input High Voltage ILIM0, ILIM1 1.2 V

IPD Static Pull-Down Current ILIM0, ILIM1; VPIN = 1V 2 µA

VCHRG CHRG Pin Output Low Voltage ICHRG = 10mA 0.15 0.4 V

ICHRG CHRG Pin Input Current VBAT = 4.5V, VCHRG = 5V 0 1 µA

LTC3577/LTC3577-1

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ELECTRICAL CHARACTERISTICS

I2C Interface. The l denotes the speciﬁ cations which apply over the full

operating temperature range, otherwise speciﬁ cations are at TA = 25°C. DVCC = 3.3V, VOUT = 3.8V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DVCC Input Supply Voltage 1.6 5.5 V

IDVCC DVCC Supply Current SCL = 400kHz

SCL = SDA = 0kHz 1

0.4 µA

µA

VDVCC,UVLO DVCC UVLO 1.0 V

VIH Input HIGH Voltage 50 70 %DVCC

VIL Input LOW Voltage 30 50 %DVCC

IIH Input HIGH Leakage Current SDA = SCL = DVCC = 5.5V –1 1 µA

IIL Input LOW Leakage Current SDA = SCL = 0V, DVCC = 5.5V –1 1 µA

VOL SDA Output LOW Voltage ISDA = 3mA 0.4 V

Timing Characteristics (Note 8) (All Values are Referenced to VIH and VIL)

fSCL SCL Clock Frequency 400 kHz

tLOW LOW Period of the SCL Clock 1.3 µs

tHIGH HIGH Period of the SCL Clock 0.6 µs

tBUF Bus Free Time Between Stop and Start Condition 1.3 µs

tHD,STA Hold Time After (Repeated) Start Condition 0.6 µs

tSU,STA Setup Time for a Repeated Start Condition 0.6 µs

tSU,STO Stop Condition Setup Time 0.6 µs

tHD,DATO Output Data Hold Time 0 900 ns

tHD,DATI Input Data Hold Time 0 ns

tSU,DAT Data Setup Time 100 ns

tSP Input Spike Suppression Pulse Width 50 ns

Step-Down Switching Regulators. The l denotes the speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. VOUT = VIN12 = VIN3 = 3.8V, all regulators enabled unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Step-Down Switching Regulators (Buck1, Buck2 and Buck3)

VIN12, VIN3 Input Supply Voltage (Note 9) l2.7 5.5 V

VOUT UVLO VOUT Falling

VOUT Rising VIN12 and VIN3 Connected to VOUT Through

Low Impedance. Switching Regulators are

Disabled Below VOUT UVLO

2.5 2.7

2.8 2.9

fOSC Oscillator Frequency 1.91 2.25 2.59 MHz

800mA Step-Down Switching Regulator 3 (Buck3 – Pushbutton Enabled, Third in Sequence)

IVIN3Q Pulse-Skipping Mode Input Current (Note 10) 100 µA

Burst Mode Operation Input Current (Note 10) 17 µA

Shutdown Input Current 0.01 µA

ILIM3 Peak PMOS Current Limit (Note 7) 1000 1400 1700 mA

VFB3 Feedback Voltage Pulse-Skipping Mode

Burst Mode Operation

0.78

0.78 0.8

0.8 0.82

0.824 V

IFB3 FB3 Input Current (Note 10) –0.05 0.05 µA

D3 Max Duty Cycle FB3 = 0V 100 %

RP3 RDS(ON) of PMOS 0.3 Ω

RN3 RDS(ON) of NMOS 0.4 Ω

LTC3577/LTC3577-1

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ELECTRICAL CHARACTERISTICS

Step-Down Switching Regulators. The l denotes the speciﬁ cations

which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VOUT = VIN12 = VIN3 = 3.8V,

all regulators enabled unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

LDO Regulator 1 (LDO1 – Enabled via I2C)

VINLDO1 Input Voltage Range VINLDO1 ≤ VOUT + 0.3V l1.65 5.5 V

VOUT_UVLO VOUT Falling

VOUT Rising LDO1 is Disabled Below VOUT UVLO 2.5 2.7

2.8 2.9 V

IQLDO1_VO

IQLDO1_VI

LD01 VOUT Quiescent Current

LD01 VINLDO1 Quiescent Current LDO1 Enabled, PON State, ILDO1 = 0mA

LDO1 Enabled, PON State, ILDO1 = 0mA 18

0.1 30

2µA

µA

IVINLDO1 Shutdown Current LDO1 Disabled, PON or POFF State 0.01 1 µA

VLDO1_FB LDO1_FB Regulated Feedback Voltage ILDO1 = 1mA l0.78 0.8 0.82 V

LDO1_FB Line Regulation (Note 11) ILDO1 = 1mA, VIN = 1.65V to 5.5V 0.4 mV/V

LDO1_FB Load Regulation (Note 11) ILDO1 = 1mA to 150mA 5 µV/mA

ILDO1_FB LDO1_FB Input Current LDO1_FB = 0.8V –50 50 nA

ILDO1_OC Available Output Current l150 mA

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

RSW3_PD SW3 Pull-Down in Shutdown POFF State 10 kΩ

500mA Step-Down Switching Regulator 2 (Buck2 – Pushbutton Enabled, Second in Sequence)

IVIN12Q Pulse-Skipping Mode Input Current (Note 10) 100 µA

Burst Mode Operation Input Current (Note 10) 17 µA

Shutdown Input Current 0.01 µA

ILIM2 Peak PMOS Current Limit (Note 7) 650 900 1200 mA

VFB2 Feedback Voltage Pulse-Skipping Mode

Burst Mode Operation

0.78

0.78 0.8

0.8 0.82

0.824 V

IFB2 FB2 Input Current (Note 10) –0.05 0.05 µA

D2 Max Duty Cycle FB2 = 0V 100 %

RP2 RDS(ON) of PMOS ISW2 = 100mA 0.6 Ω

RN2 RDS(ON) of NMOS ISW2 = –100mA 0.6 Ω

RSW2_PD SW2 Pull-Down in Shutdown POFF State 10 kΩ

500mA Step-Down Switching Regulator 1 (Buck1 – Pushbutton Enabled, First in Sequence)

IVIN12Q Pulse-Skipping Mode Input Current (Note 10) 100 µA

Burst Mode Operation Input Current (Note 10) 17 µA

Shutdown Input Current 0.01 µA

ILIM1 Peak PMOS Current Limit (Note 7) 650 900 1200 mA

VFB1 Feedback Voltage Pulse-Skipping Mode

Burst Mode Operation

0.78

0.78 0.8

0.8 0.82

0.824 V

IFB1 FB1 Input Current (Note 10) –0.05 0.05 µA

D1 Max Duty Cycle FB1 = 0V 100 %

RP1 RDS(ON) of PMOS ISW1 = 100mA 0.6 Ω

RN1 RDS(ON) of NMOS ISW1 = –100mA 0.6 Ω

RSW1_PD SW1 Pull-Down in Shutdown POFF State 10 kΩ

LDO Regulators. The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations

are at TA = 25°C. VINLDO1 = VINLDO2 = VOUT = VBAT = 3.8V, LDO1 and LDO2 enabled unless otherwise noted.

LTC3577/LTC3577-1

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ELECTRICAL CHARACTERISTICS

LDO Regulators. The l denotes the speciﬁ cations which apply over the

full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VINLDO1 = VINLDO2 = VOUT = VBAT = 3.8V, LDO1 and LDO2

enabled unless otherwise noted.

LED Boost Switching Regulator. The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise

speciﬁ cations are at TA = 25°C. VIN3 = VOUT = 3.8V, ROV = 10M, RLED_FS = 20k, boost regulator disabled unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN3, VOUT Operating Supply Range (Note 9) l2.7 5.5 V

IVOUT_LED Operating Quiescent Current

Shutdown Quiescent Current (Notes 10, 14) 560

0.01 µA

µA

VLED_OV LED_OV Overvoltage Threshold LED_OV Rising

LED_OV Falling 0.6 1.0

0.85 1.25 V

ILIM Peak NMOS Switch Current 800 1000 1200 mA

ILED_FS ILED Pin Full-Scale Operating Current 18 20 22 mA

ILED_DIM ILED Pin Full-Scale Dimming Range 64 Steps 60 dB

RNSWON RDS(ON) of NMOS Switch 240 mΩ

INSWOFF NMOS Switch-Off Leakage Current VSW = 5.5V 0.01 1 µA

fOSC Oscillator Frequency 0.95 1.125 1.3 MHz

VLED_FS LED_FS Pin Voltage l780 800 820 mV

ILED_OV LED_OV Pin Current RLED_FS = 20k l3.8 4 4.2 µA

DBOOST Maximum Duty Cycle ILED = 0 97 %

VBOOSTFB Boost Mode ILED Feedback Voltage l775 800 825 mV

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ILDO1_SC Short-Circuit Output Current 270 mA

VDROP1 Dropout Voltage (Note 12) ILDO1 = 150mA, VINLDO1 = 3.6V

ILDO1 = 150mA, VINLDO1 = 2.5V

ILDO1 = 75mA, VINLDO1 = 1.8V

160

200

170

260

320

280

RLDO1_PD Output Pull-Down Resistance in Shutdown LDO1 Disabled 10 k

LDO Regulator 2 (LDO2 – Enabled via I2C)

VINLDO2 Input Voltage Range VINLDO2 ≤ VOUT + 0.3V l1.65 5.5 V

VOUT_UVLO VOUT Falling

VOUT Rising LDO2 is Disabled Below VOUT UVLO 2.5 2.7

2.8 2.9 V

IQLDO2_VO

IQLDO2_VI

LDO2 VOUT Quiescent Current

LDO2 VINLDO2 Quiescent Current LDO2 Enabled, PON State, ILDO2 = 0mA

LDO2 Enabled, PON State, ILDO2 = 0mA 18

0.1 30

2µA

µA

IVINLDO2 Shutdown Current LDO2 Disabled, PON or POFF State 0.01 1 µA

VLDO2_FB LDO2_FB Regulated Output Voltage ILDO2 = 1mA l0.78 0.8 0.82 V

LDO2_FB Line Regulation (Note 11) ILDO2 = 1mA, VIN = 1.65V to 5.5V 0.4 mV/V

LDO2_FB Load Regulation (Note 11) ILDO2 = 1mA to 150mA 5 µV/mA

ILDO2_FB LDO2_FB Input Current LDO2_FB = 0.8V –50 50 nA

ILDO2_OC Available Output Current l150 mA

ILDO2_SC Short-Circuit Output Current 270 mA

VDROP2 Dropout Voltage (Note 12) ILDO2 = 150mA, VINLDO2 = 3.6V

ILDO2 = 150mA, VINLDO2 = 2.5V

ILDO1 = 75mA, VINLDO1 = 1.8V

160

200

170

260

320

280

RLDO2_PD Output Pull-Down Resistance in Shutdown LDO2 Disabled 14 k

LTC3577/LTC3577-1

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ELECTRICAL CHARACTERISTICS

Pushbutton Controller. The l denotes the speciﬁ cations which apply

over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VOUT = 3.8V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Pushbutton Pin (ON)

VOUT Pushbutton Operating Supply Range (Note 9) l2.7 5.5 V

VOUT UVLO VOUT Falling

VOUT Rising Pushbutton is Disabled Below VOUT UVLO 2.5 2.7

2.8 2.9 V

VON_TH ON Threshold Rising

ON Threshold Falling 0.4 0.8

0.7 1.2 V

ION ON Input Current VON = VOUT

VON = 0V –1

–4 –9 1

–14 A

A

Power-On Input Pin (PWR_ON)

VPWR_ON PWR_ON Threshold Rising

PWR_ON Threshold Falling 0.4 0.8

0.7 1.2 V

IPWR_ON PWR_ON Input Current VPWR_ON = 3V –1 1 A

Status Output Pins (PBSTAT, WAKE, PG_DCDC)

IPBSTAT PBSTAT Output High Leakage Current VPBSTAT = 3V –1 1 A

VPBSTAT PBSTAT Output Low Voltage IPBSTAT = 3mA 0.1 0.4 V

IWAKE Wake Output High Leakage Current VWAKE = 3V –1 1 A

VWAKE Wake Low Output Voltage IWAKE = 3mA 0.1 0.4 V

IPG_DCDC PG_DCDC Output High Leakage Current VPG_DCDC = 3V –1 1 A

VPG_DCDC PG_DCDC Output Low Voltage IPG_DCDC = 3mA 0.1 0.4 V

VTHPG_DCDC PG_DCDC Threshold Voltage (Note 13) –8 %

Pushbutton Timing Parameters

tON_PBSTAT1 ON Low Time to PBSTAT Low WAKE High 50 ms

tON_PBSTAT2 ON High to PBSTAT High PBSTAT Low > tPBSTAT_PW 900 s

tON_WAKE ON Low Time to WAKE High WAKE Low > tPWR_ONBK2 400 ms

tON_HR ON Low to Hard Reset Hard Reset = All Supplies Disabled 4.2 5 5.8 Seconds

tPBSTAT_PW PBSTAT Minimum Pulse Width 40 50 60 ms

tWAKE_EXTP WAKE High from USB or Wall Present WAKE Low > tPWR_ONBK2 100 ms

tWAKE_DCDC WAKE High to Buck1 Enable WAKE Low > tPWR_ONBK2 5µs

tPWR_ONH PWR_ON High to WAKE High WAKE Low > tPWR_ONBK2 50 ms

tPWR_ONL PWR_ON Low to WAKE Low WAKE High > tPWR_ONBK1 50 ms

tPWR_ONBK1 PWR_ON Power-Up Blanking WAKE Rising Until PWR_ON Low Recognized 5 Seconds

tPWR_ONBK2 PWR_ON Power-Down Blanking WAKE Falling Until PWR_ON High Recognized 1 Seconds

tPG_DCDCH Bucks in Regulation to PG_DCDC High All Bucks Within PG_DCDC Threshold Voltage 230 ms

tPG_DCDCL Bucks Disabled to PG_DCDC Low All Bucks Disabled 44 s

LTC3577/LTC3577-1

3577fa

TYPICAL PERFORMANCE CHARACTERISTICS

Input Supply Current

vs Temperature

Input Supply Current

vs Temperature (Suspend Mode)

Battery Drain Current

vs Temperature

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3577E/LTC3577E-1 are guaranteed to meet performance

speciﬁ cations from 0°C to 85°C. Speciﬁ cations over the –40°C to 85°C

operating temperature range are assured by design, characterization and

correlation with statistical process controls.

Note 3: This IC includes over temperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperatures will exceed 110°C when over temperature protection is

active. Continuous operation above the speciﬁ ed maximum operating

junction temperature may result in device degradation or failure.

Note 4: VCC is the greater of VBUS, VOUT or BAT.

Note 5: Total input current is the sum of quiescent current, IBUSQ, and

measured current given by VCLPROG/RCLPROG • (hCLPROG + 1).

Note 6: hC/10 is expressed as a fraction of measured full charge current

with indicated PROG resistor.

Note 7: The current limit features of this part are intended to protect the

IC from short term or intermittent fault conditions. Continuous operation

above the speciﬁ ed maximum pin current rating may result in device

degradation or failure.

Note 8: The serial port is tested at rated operating frequency. Timing

parameters are tested and/or guaranteed by design.

Note 9: VOUT not in UVLO.

Note 10: FB high, not switching.

Note 11: Measured with the LDO running unity gain with output tied to

feedback pin.

Note 12: Dropout voltage is the minimum input to output voltage

differential needed for an LDO to maintain regulation at a speciﬁ ed output

current. When an LDO is in dropout, its output voltage will be equal to

VIN – VDROP

Note 13: PG_DCDC threshold is expressed as a percentage difference from

the Buck1-3 regulation voltages. The threshold is measured from Buck1-3

output rising.

Note 14: IVOUT_LED is the sum of VOUT and VIN3 current due to LED driver.

Note 15: The IBATQ speciﬁ cations represent the total battery load assuming

VINLDO1, VINLDO2, VIN12 and VIN3 are tied directly to VOUT.

Note 16: Long-term current density rating for the part.

TA = 25°C unless otherwise speciﬁ ed

TEMPERATURE (°C)

–50

IVBUS (mA)

0.7

3577 G01

0.4

0.2

–25 0 50

0.1

0.8

0.6

0.5

0.3

75 100 125

VBUS = 5V

1x MODE

TEMPERATURE (°C)

–50 –25

IVBUS (mA)

0.04

0.10

050 75

3577 G02

0.02

0.08

0.06

25 100 125

VBUS = 5V

TEMPERATURE (°C)

–50

IBAT (µA)

150

200

250

400

350

050 75

3577 G03

100

300

–25 25 100 125

PON STATE

Burst Mode OPERATION

NO LOAD ON SUPPLIES, LDOS AND LED

BOOST DISABLED. VBAT = 3.8V,

VBUS = 0V

POFF STATE

PON STATE

PULSE-SKIPPING MODE

HARD RESET STATE

LTC3577/LTC3577-1

3577fa

Input Current Limit

vs Temperature Input RON vs Temperature

Charge Current vs Temperature

(Thermal Regulation)

TEMPERATURE (°C)

–50

IVBUS (mA)

400

1000

1100

1200

050 75

3577 G04

200

100

800

600

300

900

700

500

–25 25 100 125

VBUS = 5V

RCLPROG = 2.1k 10x MODE

5x MODE

1x MODE

TEMPERATURE (°C)

–50

RON (m)

100

140

160

180

300

240

050 75

3577 G05

120

260

280

220

–25 25 100 125

IOUT = 400mA

VBUS = 4.5V

VBUS = 5.5V

VBUS = 5V

TEMPERATURE (°C)

–50

IBAT (mA)

400

500

600

25 75

3577 G06

300

200

–25 0 50 100 125

100

VBUS = 5V

10x MODE

RPROG = 2k

TYPICAL PERFORMANCE CHARACTERISTICS

Battery Current and Voltage

vs Time LTC3577 IBAT vs VBAT

LTC3577-1 IBAT vs VBAT

Forward Voltage vs Ideal Diode

Current (No External FET)

Forward Voltage vs Ideal Diode

Current (with Si2333DS External FET)

TA = 25°C unless otherwise speciﬁ ed

TIME (HOUR)

IBAT (mA)

VBAT AND VCHRG (V)

100

200

300

400

600

1234

3577 G07

500

VBAT

IBAT

C/10

1450mAhr

CELL

VBUS = 5V

RPROG = 2k

RCLPROG = 2k

CHRG

SAFETY

TIMER

TERMINATION

VBAT (V)

2.0

IBAT (mA)

100

200

600

400

2.4 2.8 3.2 3.6

3577 G09

500

300

4.0 4.4

RCLPROG = 2.1k

RPROG = 2k

VBUS = 5V

10x MODE

FALLING VBAT

RISING VBAT

VBAT (V)

2.0

IBAT (mA)

100

200

300

400

600

2.4 2.8 3.2 3.6

3577 G10

4.0 4.4

FALLING VBAT

500

RISING VBAT

RCLPROG = 2.1k

RPROG = 2k

VBUS = 5V

10x MODE

IBAT (A)

VFWD (V)

0.05

0.10

0.15

0.20

0.25

0.2 0.4 0.6 0.8

3577 G11

1.0 1.2

VBAT = 3.2V

VBUS = 0V

TA = 25°C

VBAT = 4.2V

VBAT = 3.6V

IBAT (A)

VFWD (mV)

0.6 1.0

3577 G12

00.2 0.4 0.8

40 VBAT = 3.8V

VBUS = 0V

TA = 25°C

Battery Regulation (Float) Voltage

vs Temperature

TEMPERATURE (°C)

–50

VBAT (V)

4.22

3577 G08

4.12

4.14

4.08

–25 0 50

4.06

4.04

4.24

4.20

4.18

4.16

4.10

75 100 125

LTC3577

IBAT = 2mA

LTC3577-1

LTC3577/LTC3577-1

3577fa

TYPICAL PERFORMANCE CHARACTERISTICS

Switching from Suspend Mode to

5x Mode WALL Connect Waveform WALL Disconnect Waveform

Oscillator Frequency

vs Temperature

Step-Down Switching Regulator 1

3.3V Output Efﬁ ciency vs IOUT1

Step-Down Switching Regulator 2

1.8V Output Efﬁ ciency vs IOUT2

TA = 25°C unless otherwise speciﬁ ed

ILIM0

5V/DIV

VOUT

5V/DIV

IBUS

0.5A/DIV

IBAT

0.5A/DIV

VBAT = 3.75V

IOUT = 100mA

RCLPROG = 2k

RPROG = 2k

ILIM1 = 5V

100µs/DIV 3577 G16

WALL

5V/DIV

VOUT

5V/DIV

IWALL

0.5A/DIV

IBAT

0.5A/DIV

VBAT = 3.75V

IOUT = 100mA

RPROG = 2k

1ms/DIV 3577 G17

WALL

5V/DIV

VOUT

5V/DIV

IWALL

0.5A/DIV

IBAT

0.5A/DIV

VBAT = 3.75V

IOUT = 100mA

RPROG = 2k

1ms/DIV 3577 G18

TEMPERATURE (°C)

–50

1.5

fOSC (MHz)

1.6

1.8

1.9

2.0

2.5

2.2

050 75

3577 G19

1.7

2.3

2.4

2.1

–25 25 100 125

VIN = 5V

VIN = 3.8V

VIN = 2.7V

VIN = 2.9V

IOUT (mA)

0.01

EFFICIENCY (%)

0.1 1 10 100 1000

3577 G20

100

VIN12 = 3.8V

VIN12 = 5V

Burst Mode

OPERATION

PULSE-SKIPPING MODE

VOUT1 = 3.3V

IOUT (mA)

0.01

EFFICIENCY (%)

0.1 1 10 100 1000

3577 G21

100

VIN12 = 3.8V

VIN12 = 5V

Burst Mode

OPERATION

VOUT2 = 1.8V

PULSE-SKIPPING MODE

Input Connect Waveform Input Disconnect Waveform Switching from 1x to 5x Mode

VBUS

5V/DIV

VOUT

5V/DIV

IBUS

0.5A/DIV

IBAT

0.5A/DIV

VBAT = 3.75V

IOUT = 100mA

RCLPROG = 2k

RPROG = 2k

1ms/DIV 3577 G13

VBUS

5V/DIV

VOUT

5V/DIV

IBUS

0.5A/DIV

IBAT

0.5A/DIV

VBAT = 3.75V

IOUT = 100mA

RCLPROG = 2k

RPROG = 2k

1ms/DIV 3577 G14

ILIM0/ILIM1

5V/DIV

IBUS

0.5A/DIV

IBAT

0.5A/DIV

VBAT = 3.75V

IOUT = 50mA

RCLPROG = 2k

RPROG = 2k

1ms/DIV 3577 G15

LTC3577/LTC3577-1

3577fa

Step-Down Switching Regulator 3

1.2V Output Efﬁ ciency vs IOUT3

Step-Down Switching Regulator 3

2.5V Output Efﬁ ciency vs IOUT3

TEMPERATURE (°C)

–50

SHORT-CIRCUIT CURRENT (mA)

1100

3577 G24

800

600

–25 0 50

500

1200

1300

1400

1500

1000

900

700

75 100 125

800mA BUCK

500mA BUCK

VINx = 3.8V

VINx = 5V

TYPICAL PERFORMANCE CHARACTERISTICS

Step-Down Switching Regulator

Output Transient (Burst Mode

Operation)

Step-Down Switching Regulator

Output Transient (Pulse-Skipping

Mode)

800mA Step-Down Switching

Regulator Feedback Voltage

vs Output Current

TA = 25°C unless otherwise speciﬁ ed

Step-Down Switching Regulator

Switch Impedance vs Temperature

500mA Step-Down Switching

Regulator Feedback Voltage

vs Output Current

TEMPERATURE (°C)

–50

SWITCH IMPEDANCE ()

0.1

0.3

0.4

0.5

0.9

3577 G27

0.2

–25 75 100

25 125

0.6

0.7

0.8

800mA NMOS

800mA PMOS

500mA

PMOS

500mA

NMOS

VINX = 3.2V

OUTPUT CURRENT (mA)

0.78

FEEDBACK (V)

0.84

0.85

0.77

0.76

0.83

0.80

0.82

0.81

0.79

0.1 10 100 1000

3577 G28

0.75 1

3.8V

Burst Mode

OPERATION

PULSE-SKIPPING MODE

OUTPUT CURRENT (mA)

0.78

FEEDBACK (V)

0.84

0.85

0.77

0.76

0.83

0.80

0.82

0.81

0.79

0.1 10 100 1000

3577 G29

0.75 1

3.8V

Burst Mode

OPERATION

PULSE-SKIPPING MODE

VOUT1

50mV/DIV

(AC)

VOUT2

50mV/DIV

(AC)

VOUT3

100mV/DIV

(AC)

IOUT3

500mA

5mA 3577 G25

50µs/DIV

VOUT1 = 3.3V

IOUT1 = 10mA

VOUT2 = 1.8V

IOUT2 = 20mA

VOUT3 = 1.2V

VOUT = VBAT = 3.8V

VOUT1

50mV/DIV

(AC)

VOUT2

50mV/DIV

(AC)

VOUT3

100mV/DIV

(AC)

IOUT3

500mA

5mA 3577 G26

50µs/DIV

VOUT1 = 3.3V

IOUT1 = 30mA

VOUT2 = 1.8V

IOUT2 = 20mA

VOUT3 = 1.2V

VOUT = VBAT = 3.8V

LDO Load Step

LDO1

50mV/DIV

(AC)

LDO2

20mV/DIV

(AC)

IOUT1

100mA

5mA 3577 G30

20µs/DIVLDO1 = 1.2V

LDO2 = 2.5V

ILDO2 = 40mA

VOUT = VBAT = 3.8V

Step-Down Switching Regulator

Short-Circuit Current vs Temperature

IOUT (mA)

0.01

EFFICIENCY (%)

0.1 1 10 100 1000

3577 G22

100

VIN3 = 3.8V

VIN3 = 5V

Burst Mode

OPERATION

VOUT3 = 1.2V

PULSE-SKIPPING MODE

IOUT (mA)

0.01

EFFICIENCY (%)

0.1 1 10 100 1000

3577 G23

100

VIN3 = 3.8V

VIN3 = 5V

Burst Mode

OPERATION

VOUT3 = 2.5V

PULSE-SKIPPING MODE

LTC3577/LTC3577-1

3577fa

TYPICAL PERFORMANCE CHARACTERISTICS

OVSENS Quiescent Current

vs Temperature OVGATE vs OVSENS

Input and Battery Current

vs Load Current

TA = 25°C unless otherwise speciﬁ ed

Rising Overvoltage Threshold

vs Temperature

LED Driver Efﬁ ciency 10 LEDs LED Driver Efﬁ ciency 8 LEDs

TEMPERATURE (°C)

–40

QUIESCENT CURRENT (µA)

3577 G34

27 –15 10 35 85

VOVSENS = 5V

TEMPERATURE (°C)

–40

OPV THRESHOLD (V)

6.270

6.275

6.280

3577 G35

6.265

6.260

6.255 –15 10 35 85

INPUT VOLTAGE (V)

OVGATE (V)

24 68

3577 G36

OVSENS CONNECTED

TO INPUT THROUGH

6.2k RESISTOR

ILOAD (mA)

600

500

400

300

200

100

–100 300 500

3577 G37

100 200 400 600

CURRENT (mA)

ILOAD

IIN

IBAT

(CHARGING)

IBAT

(DISCHARGING)

WALL = 0V

RPROG = 2k

RCLPROG = 2k

ILED (mA)

EFFICIENCY (%)

50 16

3577 G38

4 8 12 20142 6 10 18

3.6V

4.2V

4.8V

5.5V

ILED (mA)

EFFICIENCY (%)

50 16

35773 G39

4 8 12 20142 6 10 18

3.6V

4.2V

4.8V

5.5V

OVP Connection Waveform OVP Reconnection WaveformOVP Protection Waveform

VBUS

5V/DIV

OVGATE

5V/DIV

500µs/DIV 3577 G31

OVP

INPUT

VOLTAGE

0V TO 5V

STEP 5V/DIV

VBUS

5V/DIV

OVGATE

5V/DIV

500µs/DIV 3577 G32

OVP

INPUT

VOLTAGE

5V TO 10V

STEP 5V/DIV

VBUS

5V/DIV

OVGATE

5V/DIV

500µs/DIV 3577 G33

OVP

INPUT

VOLTAGE

10V TO 5V

STEP 5V/DIV

LTC3577/LTC3577-1

3577fa

LED Driver Efﬁ ciency 6 LEDs LED Driver Efﬁ ciency 4 LEDs

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C unless otherwise speciﬁ ed

LED PWM

vs Constant Current Efﬁ ciency Too Hot BAT Discharge

DAC Code vs LED Current LED Boost Start-Up Transient

LED Boost Maximum Duty Cycle

vs Temperature

ILED (mA)

EFFICIENCY (%)

50 16

3577 G40

4 8 12 20142 6 10 18

3.6V

4.2V

4.8V

5.5V

ILED (mA)

EFFICIENCY (%)

50 16

3577 G41

4 8 12 20142 6 10 18

3.6V

4.2V

4.8V

5.5V

DAC CODE

30 50

3577 G43

10 20 40 60 70

CURRENT (dB)

60dB = 20mA

0dB = 20µA

RLED_FS = 20k

VBAT (V)

3.8

IBAT (mA)

100

200

140

3.9 4.0

3577 G48

160

180

120

4.1 4.2

VNTC < VTOO_HOT

VBUS = 0V

LED Boost Current Limit

vs Temperature

TEMPERATURE (°C)

–40

CURRENT LIMIT (mA)

600

800

1000

1200

3577 G42

400

200

500

700

900

1100

300

100

0–20 020 60 80 100 120

ILED

10mA/DIV

VBOOST

20V/DIV

200mA/DIV

2ms/DIV 3577 G44

TEMPERATURE (°C)

–50

95.7

MAX DUTY CYCLE (%)

95.8

96.0

96.1

96.2

96.6

3577 G45

95.9

–25 75 100

25 125

96.3

96.4

96.5

3.6V

4.2V

5.5V

LED CURRENT (A)

EFFICIENCY (%)

1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01

3577 G46

MAX PWM CONSTANT

CURRENT

Battery Discharge

vs Temperature

TEMPERATURE (°C)

BATTERY DISCHARGE CURRENT (mA)

175

3577 G47

100

60 70 90

200

150

125

100 110 120

VBUS = 5V

VBUS = 0V

VBAT = 4.1V

VNTC < VTOO_HOT

5x MODE

IVOUT = 0mA

LTC3577/LTC3577-1

3577fa

PIN FUNCTIONS

ILIM0, ILIM1 (Pins 1, 2): Input Current Control Pins. ILIM0

and ILIM1 control the input current limit. See Table 1 in the

“USB PowerPath Controller” section. Both pins are pulled

low by a weak current sink.

LED_FS (Pin 3): A resistor between this pin and ground

sets the full-scale output current of the ILED pin.

WALL (Pin 4): Wall Adapter Present Input. Pulling this

pin above 4.3V will disconnect the power path from VBUS

to VOUT

. The ACPR pin will also be pulled low to indicate

that a wall adapter has been detected.

SW3 (Pin 5): Power Transmission (Switch) Pin for Step-

Down Switching Regulator 3 (buck3).

VIN3 (Pin 6): Power Input for Step-Down Switching Regula-

tor 3. This pin should be connected to VOUT

FB3 (Pin 7): Feedback Input for Step-Down Switching

Regulator 3 (buck3). This pin servos to a ﬁ xed voltage of

0.8V when the control loop is complete.

OVSENSE (Pin 8): Overvoltage Protection Sense Input.

OVSENSE should be connected through a 6.2k resistor

to the input power connector and the drain of an external

N-channel MOS pass transistor. When the voltage on

this pin exceeds a preset level, the OVGATE pin will be

pulled to GND to disable the pass transistor and protect

downstream circuitry.

LED_OV (Pin 9): A resistor between this pin and the boosted

LED backlight voltage sets the overvoltage limit on the

boost output. If the boost voltage exceeds the programmed

limit the LED boost converter will be disabled.

DVCC (Pin 10): Supply Voltage for I2C Lines. This pin sets

the logic reference level of the LTC3577. A UVLO circuit on

the DVCC pin forces all registers to all 0s whenever DVCC

is <1V. Bypass to GND with a 0.1µF capacitor.

SDA (Pin 11): I2C Data Input. Serial data is shifted one bit

per clock to control the LTC3577. The logic level for SDA

is referenced to DVCC.

SCL (Pin 12): I2C Clock Input. The logic level for SCL is

referenced to DVCC.

OVGATE (Pin 13): Overvoltage Protection Gate Output.

Connect OVGATE to the gate pin of an external N-channel

MOS pass transistor. The source of the transistor should

be connected to VBUS and the drain should be connected

to the product’s DC input connector. In the absence of an

overvoltage condition, this pin is connected to an internal

charge pump capable of creating sufﬁ cient overdrive to

fully enhance this transistor. If an overvoltage condition

is detected, OVGATE is brought rapidly to GND to prevent

damage. OVGATE works in conjunction with OVSENSE to

provide this protection.

PWR_ON (Pin 14): Logic Input Used to Keep Buck

DC/DCs Enabled After Power-Up. May also be used to

enable the buck DC/DCs directly (sequence = buck1 →

buck2 → buck3). See the “Pushbutton Interface Opera-

tion” section for more information.

ON (Pin 15): Pushbutton Input. A weak internal pull-up

forces ON high when left ﬂ oating. A normally open push-

button is connected from ON to ground to force a low

state on this pin.

PBSTAT (Pin 16): Open-drain output is a de-bounced

and buffered version of ON to be used for processor

interrupts.

WAKE (Pin 17): Open-Drain Output. The WAKE pin indicates

the operating state of the buck DC/DCs. If WAKE is Hi-Z,

the buck DC/DCs are enabled and either up or powering up.

A low on WAKE indicates that the buck DC/DCs are either

powered down or are powering down. See the “Pushbutton

Interface Operation” section for more information.

SW (Pins 18,19,20): Power Transmission (Switch) Pin

for LED Boost Converter. See the “LED Backlight/Boost

Operation” section for circuit hook-up and component

selection. I2C is used to control LED driver enable. I2C

default is LED driver off.

PG_DCDC (Pin 21): Open-Drain Output. PG_DCDC goes

high impedance 230ms after all buck DC/DCs are in regula-

tion (within 8% of ﬁ nal value).

LTC3577/LTC3577-1

3577fa

PIN FUNCTIONS

ILED (Pin 22): Series LED Backlight Current Sink Output.

This pin is connected to the cathode end of the series LED

backlight string. The current drawn through the series LEDs

can be programmed via a 6-bit 60dB DAC and dimmed via

an internal 4-bit PWM function. I2C is used to control LED

driver enable, brightness, gradation (soft on/soft off). I2C

default is LED driver off, current = 0mA.

VINLDO1 (Pin 23): Input Supply of Low Dropout Linear

Regulator 1 (LDO1). This pin should be bypassed to ground

with a 1µF or greater ceramic capacitor.

LDO2_FB (Pin 24): Feedback Voltage Input for Low Drop-

out Linear Regulator 2 (LDO2). LDO2 output voltage is

set using an external resistor divider between LDO2 and

LDO2_FB.

FB2 (Pin 25): Feedback Input for Step-Down Switching

Regulator 2 (buck2). This pin servos to a ﬁ xed voltage of

0.8V when the control loop is complete.

FB1 (Pin 26): Feedback Input for Step-Down Switching

Regulator 1 (buck1). This pin servos to a ﬁ xed voltage of

0.8V when the control loop is complete.

LDO1_FB (Pin 27): Feedback Voltage Input for Low Drop-

out Linear Regulator 1 (LDO1). LDO1 output voltage is

set using an external resistor divider between LDO1 and

LDO1_FB.

LDO1 (Pin 28): Output of Low Dropout Linear Regulator 1.

This pin must be bypassed to ground with a 1µF or greater

ceramic capacitor.

LDO2 (Pin 29): Output of Low Dropout Linear Regulator 2.

This pin must be bypassed to ground with a 1µF or greater

ceramic capacitor.

VINLDO2 (Pin 30): Input Supply of Low Dropout Linear

Regulator 2 (LDO2). This pin should be bypassed to ground

with a 1µF or greater ceramic capacitor.

SW2 (Pin 31): Power Transmission (Switch) Pin for Step-

Down Switching Regulator 2 (buck2).

VIN12 (Pin 32): Power Input for Step-Down Switching

Regulators 1 and 2. This pin will generally be connected

to VOUT

SW1 (Pin 33): Power Transmission (Switch) Pin for Step-

Down Switching Regulator 1 (buck1).

NTCBIAS (Pin 34): Output Bias Voltage for NTC. A

resistor from this pin to the NTC pin will bias the NTC

thermistor.

NTC (Pin 35): The NTC pin connects to a battery’s therm-

istor to determine if the battery is too hot or too cold

to charge. If the battery’s temperature is out of range,

charging is paused until it drops back into range. A low

drift bias resistor is required from NTCBIAS to NTC and

a thermistor is required from NTC to ground.

PROG (Pin 36): Charge Current Program and Charge

Current Monitor Pin. Connecting a resistor from PROG

to ground programs the charge current:

ICHG =1000V

RPROG

()

If sufﬁ cient input power is available in constant current

mode, this pin servos to 1V. The voltage on this pin always

represents the actual charge current.

IDGATE (Pin 37): Ideal Diode Gate Connection. This

pin controls the gate of an optional external P-channel

MOSFET transistor used to supplement the internal ideal

diode. The source of the P-channel MOSFET should be

connected to VOUT and the drain should be connected to

BAT. It is important to maintain high impedance on this

pin and minimize all leakage paths.

BAT (Pin 38): Single Cell Li-Ion Battery Pin. Depending

on available power and load, a Li-Ion battery on BAT will

either deliver system power to VOUT through the ideal

diode or be charged from the battery charger.

VOUT (Pin 39): Output Voltage of the PowerPath Controller

and Input Voltage of the Battery Charger. The majority of

the portable product should be powered from VOUT

. The

LTC3577 will partition the available power between the

external load on VOUT and the internal battery charger.

Priority is given to the external load and any extra power

is used to charge the battery. An ideal diode from BAT to

VOUT ensures that VOUT is powered even if the load exceeds

the allotted input current from VBUS or if the VBUS power

source is removed. VOUT should be bypassed with a low

impedance multilayer ceramic capacitor.

LTC3577/LTC3577-1

3577fa

VBUS (Pin 40): USB Input Voltage. VBUS will usually be

connected to the USB port of a computer or a DC output

wall adapter. VBUS should be bypassed with a low imped-

ance multilayer ceramic capacitor.

ACPR (Pin 41): Wall Adapter Present Output (Active Low).

A low on this pin indicates that the wall adapter input com-

parator has had its input pulled above its input threshold

(typically 4.3V). This pin can be used to drive the gate of

an external P-channel MOSFET to provide power to VOUT

from a power source other than a USB port.

VC (Pin 42): High Voltage Buck Regulator Control Pin.

This pin can be used to drive the VC pin of an approved

external high voltage buck switching regulator. The VC pin

is designed to work with the LT

3480, LT3653 and LT3505.

Consult factory for additional approved high voltage buck

regulators. See the “External HV Buck Control through the

VC Pin” section for operating information.

CLPROG (Pin 43): Input Current Program and Input

Current Monitor Pin. A resistor from CLPROG to ground

determines the upper limit of the current drawn from the

VBUS pin (i.e., the input current limit). A precise fraction

of the input current, hCLPROG, is sent to the CLPROG

pin. The input PowerPath delivers current until the

CLPROG pin reaches 2V (10x mode), 1V (5x mode) or 0.2V

(1x mode). Therefore, the current drawn from VBUS will

be limited to an amount given by hCLPROG and RCLPROG.

In USB applications the resistor RCLPROG should be set

to no less than 2.1k.

CHRG (Pin 44): Open-Drain Charge Status Output. The

CHRG pin indicates the status of the battery charger. If

CHRG is high then the charger is near the ﬂ oat voltage

(charge current less than 1/10th programmed charge cur-

rent) or charging is complete and charger is disabled. A low

on CHRG indicates that the charger is enabled. For more

information see the “Charge Status Indication” section.

Ground (Exposed Pad Pin 45): The exposed package pad is

ground and must be soldered to PCB ground for electrical

contact and rated thermal performance.

PIN FUNCTIONS

LTC3577/LTC3577-1

3577fa

BLOCK DIAGRAM

–

15mV

VOUT

HRST UVLO

IDEAL

DIODE

CC/CV

CHARGER

WALL

DETECT

500mA, 2.25MHz

BUCK REGULATOR

INPUT

CURRENT

LIMIT

OVERTEMP BATTERY

SAFETY DISCHARGE

OVERVOLTAGE

PROTECTON

BATTERY

TEMP

MONITOR

ILIM

LOGIC

I2C

LOGIC

40V LED BACKLIGHT

BOOST CONVERTER

0.8V

500mA, 2.25MHz

BUCK REGULATOR

0.8V

800mA, 2.25MHz

BUCK REGULATOR

0.8V

PG_DCDC

0.8V

150mA

LDO1

IDGATE

BAT

VIN12

PROG

SW1

FB1

FB2

SW3

FB3

SW2

VINLD01

VIN3

DVCC

PBSTAT

18,19,20

LED_OV

LDO1

LDO1_FB

0.8V

150mA

LDO2

EN 30

VINLD02

LDO2

LDO2_FB

3577 BD

230ms

FALLING

DELAY

CHRG

CHRGE

STATUS

ILED

LED_FS

DAC

0.8V

GND

SDA

SCL

PWR_ON

NTC

NTCBIAS

CLPROG

VBUS

OVSENS

ILIM1

ILIM0

WAKE

PUSH-

BUTTON

INPUT

OVGATE

WALL

ACPR

CONTROL

LTC3577/LTC3577-1

3577fa

OPERATION

PowerPath OPERATION

Introduction

The LTC3577 is a highly integrated power management

IC that features:

– PowerPath controller

– Battery charger

– Ideal diode

– Input overvoltage protection

– Pushbutton controller

– Three step-down switching regulators

– High voltage buck regulator VC controller

– Two low dropout linear regulators

– 40V LED backlight controller

Designed speciﬁ cally for USB applications, the PowerPath

controller incorporates a precision input current limit

which communicates with the battery charger to ensure

that input current does not violate the USB average input

current speciﬁ cation. The ideal diode from BAT to VOUT

guarantees that ample power is always available to VOUT

even if there is insufﬁ cient or absent power at VBUS. The

LTC3577 also has the ability to receive power from a wall

adapter or other non-current-limited power source. Such

a power supply can be connected to the VOUT pin of the

LTC3577 through an external device such as a power

Schottky or FET as shown in Figure 1. The LTC3577 has

the unique ability to use the output, which is powered by

an external supply, to charge the battery while provid-

ing power to the load. A comparator on the WALL pin is

conﬁ gured to detect the presence of the wall adapter and

shut off the connection to the USB. This prevents reverse

conduction from VOUT to VBUS when a wall adapter is pres-

ent. The LTC3577 provides a VC output pin which can be

used to drive the VC pin of an external high voltage buck

switching regulator such as the LT3480, LT3653 or LT3505

to provide power to the VOUT pin. The VC control circuitry

adjusts the regulation point of the switching regulator to

–

4.3V

(RISING)

3.2V

(FALLING)

75mV (RISING)

25mV (FALLING) ENABLE

USB CURRENT LIMIT

CONSTANT CURRENT

CONSTANT VOLTAGE

BATTERY CHARGER

WALL

FROM AC ADAPTER (OR HIGH VOLTAGE BUCK OUTPUT)

VBUS

FROM

USB 40

–

15mV

IDGATE

BAT

3577 F01 Li-Ion

OPTIONAL

EXTERNAL

IDEAL DIODE

PMOS

BAT

IDEAL

DIODE

VOUT

OPTIONAL CONTROL

FOR HIGH VOLTAGE BUCK REGS

LT3480, LT3481 OR LT3505

ACPR

SYSTEM

LOAD

Figure 1. Simpliﬁ ed PowerPath Block Diagram

LTC3577/LTC3577-1

3577fa

OPERATION

a small voltage above the BAT pin voltage. This control

method provides a high input voltage, high efﬁ ciency

battery charger and PowerPath function.

The LTC3577 also includes a pushbutton input to control

the three synchronous step-down switching regulators

and system reset. The three 2.25MHz constant frequency

current mode step-down switching regulators provide

500mA, 500mA and 800mA each and support 100% duty

cycle operation as well as Burst Mode operation for high

efﬁ ciency at light load. No external compensation compo-

nents are required for the switching regulators.

The onboard LED backlight boost circuitry can drive up

to 10 series LEDs and includes versatile digital dimming

via the I2C input. The I2C input also controls two 150mA

low dropout (LDO) linear regulators.

All regulators can be programmed for a minimum output

voltage of 0.8V and can be used to power a microcon-

troller core, microcontroller I/O, memory or other logic

circuitry.

USB PowerPath Controller

The input current limit and charge control circuits of the

LTC3577 are designed to limit input current as well as

control battery charge current as a function of IVOUT

VOUT drives the combination of the external load, the three

step-down switching regulators, two LDOs, LED backlight

and the battery charger.

If the combined load does not exceed the programmed

input current limit, VOUT will be connected to VBUS through

an internal 200m P-channel MOSFET. If the combined

load at VOUT exceeds the programmed input current limit,

the battery charger will reduce its charge current by the

amount necessary to enable the external load to be satisﬁ ed

while maintaining the programmed input current. Even if

the battery charge current is set to exceed the allowable

USB current, the average input current USB speciﬁ cation

will not be violated. Furthermore, load current at VOUT

will always be prioritized and only excess available cur-

rent will be used to charge the battery. The current out

of the CLPROG pin is a fraction (1/hCLPROG) of the VBUS

current. When a programming resistor is connected from

CLPROG to GND, the voltage on CLPROG represents the

input current:

IVBUS =IBUSQ +VCLPROG

RCLPROG

•hCLPROG

where IBUSQ and hCLPROG are given in the Electrical Char-

acteristics table.

The input current limit is programmed by the ILIM0 and

ILIM1 pins. The LTC3577 can be conﬁ gured to limit input

current to one of several possible settings as well as be

deactivated (USB suspend). The input current limit will be

set by the appropriate servo voltage and the resistor on

CLPROG according to the following expression:

IVBUS =IBUSQ +0.2V

RCLPROG

•hCLPROG 1x Mode

()

IVBUS =IBUSQ +1V

RCLPROG

•hCLPROG 5x Mode

()

IVBUS =IBUSQ +2V

RCLPROG

•hCLPROG 10x Mode

()

Under worst-case conditions, the USB speciﬁ cation for

average input current will not be violated with an RCLPROG

resistor of 2.1k or greater. Table 1 shows the available

settings for the ILIM0 and ILIM1 pins:

Table 1. Controlled Input Current Limit

ILIM1 ILIM0 IBUS(LIM)

0 0 100mA (1x)

0 1 1A (10x)

1 0 Suspend

1 1 500mA (5x)

Notice that when ILIM0 is high and ILIM1 is low, the input

current limit is set to a higher current limit for increased

charging and current availability at VOUT

. This mode is

typically used when there is a higher power, non-USB

source available at the VBUS pin.

LTC3577/LTC3577-1

3577fa

OPERATION

Ideal Diode from BAT to VOUT

The LTC3577 has an internal ideal diode as well as a con-

troller for an optional external ideal diode. Both the internal

and the external ideal diodes respond quickly whenever

VOUT drops below BAT. If the load increases beyond the

input current limit, additional current will be pulled from

the battery via the ideal diodes. Furthermore, if power to

VBUS (USB) or VOUT (external wall power or high voltage

regulator) is removed, then all of the application power

will be provided by the battery via the ideal diodes. The

ideal diodes are fast enough to keep VOUT from dropping

signiﬁ cantly with just the recommended output capacitor

(see Figure 2). The ideal diode consists of a precision ampli-

ﬁ er that enables an on-chip P-channel MOSFET whenever

the voltage at VOUT is approximately 15mV (VFWD) below

the voltage at BAT. The resistance of the internal ideal

diode is approximately 200m. If this is sufﬁ cient for

the application, then no external components are neces-

sary. However, if lower resistance is needed, an external

P-channel MOSFET can be added from BAT to VOUT

. The

IDGATE pin of the LTC3577 drives the gate of the external

P-channel MOSFET for automatic ideal diode control. The

source of the MOSFET should be connected to VOUT and

the drain should be connected to BAT. Capable of driving a

1nF load, the IDGATE pin can control an external P-channel

MOSFET having extremely low on-resistance.

Using the WALL Pin to Detect the Presence of an

External Power Source

The WALL input pin can be used to identify the presence

of an external power source (particularly one that is not

subject to a ﬁ xed current limit like the USB VBUS input).

Typically, such a power supply would be a 5V wall adapter

output or the low voltage output of a high voltage buck

regulator (speciﬁ cally, LT3480, LT3653 or LT3505). When

the wall adapter output (or buck regulator output) is con-

nected directly to the WALL pin, and the voltage exceeds

the WALL pin threshold, the USB power path (from VBUS

to VOUT) will be disconnected. Furthermore, the ACPR pin

will be pulled low. In order for the presence of an external

power supply to be acknowledged, both of the following

conditions must be satisﬁ ed:

1. The WALL pin voltage must exceed approximately

4.3V.

2. The WALL pin voltage must be greater than 75mV above

the BAT pin voltage.

The input power path (between VBUS and VOUT) is re-

enabled and the ACPR pin is pulled high when either of

the following conditions is met:

1. The WALL pin voltage falls to within 25mV of the BAT

pin voltage.

2. The WALL pin voltage falls below 3.2V.

Each of these thresholds is suitably ﬁ ltered in time to

prevent transient glitches on the WALL pin from falsely

triggering an event.

External HV Buck Control Through the VC Pin

The WALL, ACPR and VC pins can be used in conjunction

with an external high voltage buck regulator such as the

LT3480, LT3505 or LT3653 to provide power directly to the

VOUT pin as shown in Figures 3 to 5 (Consult factory for

complete list of approved high voltage buck regulators).

When the WALL pin voltage exceeds 4.3V, VC pin control

circuitry is enabled and drives the VC pin of the LT3480,

LT3505 or LT3653. The VC pin control circuitry is designed

so that no compensation components are required on the

VC node. The voltage at the VOUT pin is regulated to the

larger of (BAT + 300mV) or 3.6V as shown in Figure 6.

4.0V

3.8VVOUT

3.6V

500mA

–500mA

0IBAT

IVOUT

LOAD

10µs/DIV

CHARGE

DISCHARGE

3577 F02

VBAT = 3.8V

VBUS = 5V

5x MODE

COUT = 10µF

Figure 2. Ideal Diode Transient Response

LTC3577/LTC3577-1

3577fa

OPERATION

VIN 2

DFLS240L

0.47µF

22µF

COUT

VOUT

UP TO

BAT

3577 F03

Li-Ion

Si2333DS

(OPT)

6.8µH

BOOST

42 4 41

LTC3577

WALL ACPR

IDGATE

VOUT

BAT

RUN/SS

150k

40.2k

68nF

4.7µF

HVIN

8V TO 38V

(TRANSIENTS

TO 60V)

499k

100k

BD 8

11 9

LT3480

HIGH VOLTAGE

BUCK CIRCUITRY

GND VC

Figure 3. LT3480 Buck Control Using VC (800kHz Switching)

VIN

MBRM140

0.1µF

10µF

COUT

UP TO

1.2A

VOUT

BAT

3577 F04

Li-Ion

Si2333DS

(OPT)

6.8µH

1N4148

BOOST

42 4 41

LTC3577

WALL ACPR

IDGATE

VOUT

BAT

SHDN

150k

806k

BZT52C16T

20k

68nF

1µF

HVIN

8V TO 36V

49.9k

10.0k

5, 9 8

LT3505

HIGH VOLTAGE

BUCK CIRCUITRY

GND VC

Figure 4. LT3505 Buck Control Using VC (2.2MHz Switching with Frequency Foldback)

LTC3577/LTC3577-1

3577fa

OPERATION

VIN

ILIM ISENSE

DFLS240L

0.1µF

10V

COUT

UP TO

1.2A

VOUT

BAT

3577 F05

Li-Ion

Si2333DS

(OPT)

4.7µH

BOOST

42 4 41

LTC3577

WALL ACPR

IDGATE

VOUT

BAT

324k

4.7µF

60V

HVIN

7.5V TO 30V

(TRANSIENTS

TO 60V) SW

VOUT

LT3653

HIGH VOLTAGE

BUCK CIRCUITRY

GND

VCHVOK

Figure 5. LT3653 Buck Control Using VC

BAT (V)

2.5

VOUT (V)

3.5

4.0

4.5

3577 F06

3.0

2.5 33.5 4

5.0

4.5

IO = 0.0A

IO = 0.75A

IO = 1.5A

BAT

Figure 6. VOUT Voltage vs Battery Voltage (LT3480)

BAT (V)

2.5

VOUT (V)

3.5

4.0

4.5

3577 F07

3.0

2.5 33.5 4

5.0

4.5

IO = 0.0A

IO = 0.6A

BAT

Figure 7. VOUT Voltage vs Battery Voltage (LT3505)

LTC3577/LTC3577-1

3577fa

OPERATION

The feedback network of the high voltage buck regulator

should be set to generate an output voltage higher than

4.4V (be sure to include the output voltage tolerance

of the buck regulator). The VC control of the LTC3577

overdrives the local VC control of the external high volt-

age buck. Therefore, once the VC control is enabled, the

output voltage is set independent of the buck regulator

feedback network.

This technique provides a signiﬁ cant efﬁ ciency advantage

over the use of a 5V buck to drive the battery charger. With

a simple 5V buck output driving VOUT

, battery charger

efﬁ ciency is approximately:

ηCHARGER =η

BUCK •VBAT

where ηBUCK is the efﬁ ciency of the high voltage buck

regulator and 5V is the output voltage of the buck regu-

lator. With a typical buck efﬁ ciency of 87% and a typical

battery voltage of 3.8V, the total battery charger efﬁ ciency

is approximately 66%. Assuming a 1A charge current,

this works out to nearly 2W of power dissipation just to

charge the battery!

With the VC control technique, battery charger efﬁ ciency

is approximately:

ηCHARGER =η

BUCK •VBAT

0.3V +VBAT

With the same assumptions as above, the total battery

charger efﬁ ciency is approximately 81%. This example

works out to just 900mW of power dissipation. For applica-

tions, component selection and board layout information

beyond those listed here please refer to the respective

high voltage buck regulator data sheet.

Suspend Mode

When ILIM0 is pulled low and ILIM1 is pulled high the

LTC3577 enters suspend mode to comply with the USB

speciﬁ cation. In this mode, the power path between VBUS

and VOUT is put in a high impedance state to reduce the

VBUS input current to 50A. If no other power source

is available to drive WALL and VOUT

, the system load

connected to VOUT is supplied through the ideal diodes

connected to BAT.

VBUS Undervoltage Lockout (UVLO) and Undervoltage

Current Limit (UVCL)

An internal undervoltage lockout circuit monitors VBUS

and keeps the input current limit circuitry off until VBUS

rises above the rising UVLO threshold (3.8V) and at least

50mV above VOUT

. Hysteresis on the UVLO turns off the

input current limit if VBUS drops below 3.7V or 50mV below

VOUT

. When this happens, system power at VOUT will be

drawn from the battery via the ideal diode. To minimize the

possibility of oscillation in and out of UVLO when using

resistive input supplies, the input current limit is reduced

as VBUS falls below 4.45V (typ).

Battery Charger

The LTC3577 includes a constant-current/constant-volt-

age battery charger with automatic recharge, automatic

termination by safety timer, low voltage trickle charging,

bad cell detection and thermistor sensor input for out of

temperature charge pausing. When a battery charge cycle

begins, the battery charger ﬁ rst determines if the battery

is deeply discharged. If the battery voltage is below VTRKL,

typically 2.85V, an automatic trickle charge feature sets the

battery charge current to 10% of the programmed value.

If the low voltage persists for more than one-half hour, the

battery charger automatically terminates. Once the battery

voltage is above 2.85V, the battery charger begins charging

in full power constant current mode. The current delivered

to the battery will try to reach 1000V/RPROG. Depending

on available input power and external load conditions, the

battery charger may or may not be able to charge at the

full programmed rate. The external load will always be

prioritized over the battery charge current. The USB cur-

rent limit programming will always be observed and only

additional current will be available to charge the battery.

When system loads are light, battery charge current will

be maximized.

Charge Termination

The battery charger has a built-in safety timer. When the

battery voltage approaches the ﬂ oat voltage, the charge

current begins to decrease as the LTC3577 enters constant

voltage mode. Once the battery charger detects that it

has entered constant voltage mode, the four hour safety

LTC3577/LTC3577-1

3577fa

OPERATION

timer is started. After the safety timer expires, charging

of the battery will terminate and no more current will be

delivered.

Automatic Recharge

After the battery charger terminates, it will remain off

drawing only microamperes of current from the battery.

If the portable product remains in this state long enough,

the battery will eventually self discharge. To ensure that the

battery is always topped off, a charge cycle will automati-

cally begin when the battery voltage falls below VRECHRG

(typically 4.0V for LTC3577-1 and 4.1V for LTC3577). In

the event that the safety timer is running when the battery

voltage falls below VRECHRG, the timer will reset back to

zero. To prevent brief excursions below VRECHRG from re-

setting the safety timer, the battery voltage must be below

VRECHRG for more than 1.3ms. The charge cycle and safety

timer will also restart if the VBUS UVLO cycles low and then

high (e.g., VBUS, is removed and then replaced).

Charge Current

The charge current is programmed using a single resistor

from PROG to ground. 1/1000th of the battery charge cur-

rent is delivered to PROG which will attempt to servo to

1.000V . Thus, the battery charge current will try to reach

1000 times the current in the PROG pin. The program

resistor and the charge current are calculated using the

following equations:

RPROG =1000V

ICHG

, ICHG =1000V

RPROG

In either the constant-current or constant-voltage charging

modes, the PROG pin voltage will be proportional to the

actual charge current delivered to the battery. Therefore,

the actual charge current can be determined at any time

by monitoring the PROG pin voltage and using the fol-

lowing equation:

IBAT =VPROG

RPROG

•1000

In many cases, the actual battery charge current, IBAT

, will

be lower than ICHG due to limited input current available and

prioritization with the system load drawn from VOUT.

Thermal Regulation

To prevent thermal damage to the IC or surrounding

components, an internal thermal feedback loop will

automatically decrease the programmed charge current

if the die temperature rises to approximately 110°C.

Thermal regulation protects the LTC3577 from excessive

temperature due to high power operation or high ambient

thermal conditions and allows the user to push the limits

of the power handling capability with a given circuit board

design without risk of damaging the LTC3577 or external

components. The beneﬁ t of the LTC3577 thermal regula-

tion loop is that charge current can be set according to

actual conditions rather than worst-case conditions with

the assurance that the battery charger will automatically

reduce the current in worst-case conditions.

Charge Status Indication

The CHRG pin indicates the status of the battery charger. An

open-drain output, the CHRG pin can drive an indicator LED

through a current limiting resistor for human interfacing or

simply a pull-up resistor for microprocessor interfacing.

When charging begins, CHRG is pulled low and remains

low for the duration of a normal charge cycle. When charg-

ing is complete, i.e., the charger enters constant voltage

mode and the charge current has dropped to one-tenth

of the programmed value, the CHRG pin is released (high

impedance). The CHRG pin does not respond to the C/10

threshold if the LTC3577 is in input current limit. This

prevents false end-of-charge indications due to insufﬁ cient

power available to the battery charger. Even though charg-

ing is stopped during an NTC fault, the CHRG pin will stay

low indicating that charging is not complete.

Battery Charger Stability Considerations

The LTC3577’s battery charger contains both a constant-

voltage and a constant-current control loop. The constant-

voltage loop is stable without any compensation when a

battery is connected with low impedance leads. Excessive

lead length, however, may add enough series inductance

to require a bypass capacitor of at least 1µF from BAT to

GND. Furthermore, a 4.7µF capacitor in series with a 0.2Ω

to 1Ω resistor from BAT to GND is required to keep ripple

voltage low when the battery is disconnected.

LTC3577/LTC3577-1

3577fa

OPERATION

High value, low ESR multilayer ceramic chip capacitors

reduce the constant-voltage loop phase margin, possibly

resulting in instability. Ceramic capacitors up to 22µF may

be used in parallel with a battery, but larger ceramics should

be decoupled with 0.2Ω to 1Ω of series resistance.

In constant-current mode, the PROG pin is in the feed-

back loop rather than the battery voltage. Because of the

additional pole created by any PROG pin capacitance,

capacitance on this pin must be kept to a minimum. With

no additional capacitance on the PROG pin, the battery

charger is stable with program resistor values as high

as 25k. However, additional capacitance on this node

reduces the maximum allowed program resistor. The pole

frequency at the PROG pin should be kept above 100kHz.

Therefore, if the PROG pin has a parasitic capacitance,

CPROG, the following equation should be used to calculate

the maximum resistance value for RPROG:

RPROG ≤1

2π•100kHz • CPROG

NTC Thermistor and Battery Voltage Reduction

The battery temperature is measured by placing a nega-

tive temperature coefﬁ cient (NTC) thermistor close to

the battery pack. To use this feature connect the NTC

thermistor, RNTC, between the NTC pin and ground and a

bias resistor, RNOM, from NTCBIAS to NTC. RNOM should

be a 1% resistor with a value equal to the value of the

chosen NTC thermistor at 25°C (R25). The LTC3577 will

pause charging when the resistance of the NTC thermistor

drops to 0.54 times the value of R25 or approximately 54k

(for a Vishay “Curve 1” thermistor, this corresponds to

approximately 40°C). If the battery charger is in constant

voltage (ﬂ oat) mode, the safety timer also pauses until the

thermistor indicates a return to a valid temperature. As the

temperature drops, the resistance of the NTC thermistor

rises. The LTC3577 is also designed to pause charging

when the value of the NTC thermistor increases to 3.17

times the value of R25. For a Vishay “Curve 1” thermistor

this resistance, 317k, corresponds to approximately 0°C.

The hot and cold comparators each have approximately

3°C of hysteresis to prevent oscillation about the trip point.

The typical NTC circuit is shown in Figure 8.

To improve safety and reliability the battery voltage is re-

duced when the battery temperature becomes excessively

high. When the resistance of the NTC thermistor drops to

about 0.35 times the value of R25 or approximately 35k

(for a Vishay “Curve 1” thermistor, this corresponds to

approximately 50°C) the NTC enables circuitry to moni-

tor the battery voltage. If the battery voltage is above the

battery discharge threshold (about 3.9V) then the battery

discharge circuitry is enabled and draws about 140mA

from the battery when VBUS = 0V and about 180mA when

VBUS = 5V. As the battery voltage approaches the discharge

threshold the discharge current is linearly reduced until

it reaches 0mA at which point the discharge circuitry is

disabled. Reducing the discharge current in this fashion

keeps the circuit from causing oscillations on VBAT due

to battery ESR.

When the charger is disabled an internal watchdog timer

samples the NTC thermistor for about 150µs every 150ms

and will enable the battery monitoring circuitry if the bat-

tery temperature exceeds the NTC TOO_HOT threshold.

If adding a capacitor to the NTC pin for ﬁ ltering the time

constant must be much less than 150µs so that the NTC

pin can settle to its ﬁ nal value during the sampling period.

A time constant of less than 10µs is recommended. Once

the battery monitoring circuitry is enabled it will remain

enabled and monitoring the battery voltage until the battery

–

RNOM

100k

RNTC

100k

NTC

NTCBIAS

0.26 • NTCBIAS BATTERY

OVERTEMP

3577 F08

NTC BLOCK LTC3577

TOO_COLD

TOO_HOT

0.76 • NTCBIAS

0.35 • NTCBIAS

–

Figure 8. Typical NTC Thermistor Circuit

LTC3577/LTC3577-1

3577fa

OPERATION

temperature falls back below the discharge temperature

threshold. The battery discharge circuitry is only enabled

if the battery voltage is greater than the battery discharge

threshold.

Alternate NTC Thermistors and Biasing

The LTC3577 provides temperature qualiﬁ ed charging if

a grounded thermistor and a bias resistor are connected

to NTC. By using a bias resistor whose value is equal to

the room temperature resistance of the thermistor (R25)

the upper and lower temperatures are pre-programmed

to approximately 40°C and 0°C, respectively (assuming

a Vishay “Curve 1” thermistor).

The upper and lower temperature thresholds can be ad-

justed by either a modiﬁ cation of the bias resistor value

or by adding a second adjustment resistor to the circuit.

If only the bias resistor is adjusted, then either the upper

or the lower threshold can be modiﬁ ed but not both. The

other trip point will be determined by the characteristics

of the thermistor. Using the bias resistor in addition to an

adjustment resistor, both the upper and the lower tempera-

ture trip points can be independently programmed with

the constraint that the difference between the upper and

lower temperature thresholds cannot decrease. Examples

of each technique follows.

NTC thermistors have temperature characteristics which

are indicated on resistance-temperature conversion tables.

The Vishay-Dale thermistor NTHS0603N011-N1003F, used

in the following examples, has a nominal value of 100k

and follows the Vishay “Curve 1” resistance-temperature

characteristic.

In the following explanation, this notation is used.

R25 = Value of the thermistor at 25°C

NTC|COLD = Value of thermistor at the cold trip point

NTC|HOT = Value of the thermistor at the hot trip point

COLD = Ratio of RNTC|COLD to R25

HOT= Ratio of RNTC|HOT to R25

NOM = Primary thermistor bias resistor (see Figure 9)

R1 = Optional temperature range adjustment resistor

(see Figure 9)

The trip points for the LTC3577’s temperature qualiﬁ ca-

tion are internally programmed at 0.35 • VNTC for the hot

threshold and 0.76 • VNTC for the cold threshold.

Therefore, the hot trip point is set when:

RNTC|HOT

RNOM +RNTC|HOT

•NTCBIAS =0.35 •NTCBIAS

and the cold trip point is set when:

RNTC|COLD

RNOM +RNTC|COLD

•NTCBIAS =0.76 •NTCBIAS

Solving these equations for RNTC|COLD and RNTC|HOT results

in the following:

NTC|HOT = 0.538 • RNOM

and

NTC|COLD = 3.17 • RNOM

By setting RNOM equal to R25, the above equations result

in rHOT = 0.538 and rCOLD = 3.17. Referencing these ratios

to the Vishay Resistance-Temperature Curve 1 chart gives

a hot trip point of about 40°C and a cold trip point of about

0°C. The difference between the hot and cold trip points

is approximately 40°C.

–

RNOM

105k

RNTC

100k

12.7k

NTC

NTCBIAS

0.26 • NTCBIAS BATTERY

OVERTEMP

3577 F09

NTC BLOCK LTC3577

TOO_COLD

TOO_HOT

0.76 • NTCBIAS

0.35 • NTCBIAS

–

Figure 9. NTC Thermistor Circuit with Additional Bias Resistor

LTC3577/LTC3577-1

3577fa

OPERATION

By using a bias resistor, RNOM, different in value from R25,

the hot and cold trip points can be moved in either direc-

tion. The temperature span will change somewhat due to

the non-linear behavior of the thermistor. The following

equations can be used to easily calculate a new value for

the bias resistor:

RNOM =rHOT

0.538 •R25

RNOM =rCOLD

3.17 •R25

where rHOT and rCOLD are the resistance ratios at the de-

sired hot and cold trip points. Note that these equations

are linked. Therefore, only one of the two trip points can

be chosen, the other is determined by the default ratios

designed in the IC.

Consider an example where a 60°C hot trip point is

desired. From the Vishay Curve 1 R-T characteristics,

rHOT is 0.2488 at 60°C. Using the above equation, RNOM

should be set to 46.4k. With this value of RNOM, the cold

trip point is about 16°C. Notice that the span is now 44°C

rather than the previous 40°C. This is due to the decrease

in “temperature gain” of the thermistor as absolute tem-

perature increases.

The upper and lower temperature trip points can be inde-

pendently programmed by using an additional bias resistor

as shown in Figure 9. The following formulas can be used

to compute the values of RNOM and R1:

RNOM =rCOLD –r

HOT

2.714 •R25

R1=0.536 •RNOM –r

HOT •R25

For example, to set the trip points to 0°C and 45°C with

a Vishay Curve 1 thermistor choose

RNOM =3.266 – 0.4368

2.714 •100k =104.2k

the nearest 1% value is 105k.

R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k

the nearest 1% value is 12.7k. The ﬁ nal solution is shown

in Figure 9 and results in an upper trip point of 45°C and

a lower trip point of 0°C.

Overvoltage Protection (OVP)

The LTC3577 can protect itself from the inadvertent ap-

plication of excessive voltage to VBUS or WALL with just

two external components: an N-channel FET and a 6.2k

resistor. The maximum safe overvoltage magnitude will

be determined by the choice of the external NMOS and

its associated drain breakdown voltage.

The overvoltage protection module consists of two pins.

The ﬁ rst, OVSENS, is used to measure the externally applied

voltage through an external resistor. The second, OVGATE,

is an output used to drive the gate pin of an external FET.

The voltage at OVSENS will be lower than the OVP input

voltage by (IOVSENS • 6.2k) due to the OVP circuit’s qui-

escent current. The OVP input will be 200mV to 400mV

higher than OVSENS under normal operating conditions.

When OVSENS is below 6V, an internal charge pump will

drive OVGATE to approximately 1.88 • OVSENS. This will

enhance the N-channel FET and provide a low impedance

connection to VBUS or WALL which will, in turn, power the

LTC3577. If OVSENS should rise above 6V (6.35V OVP

input) due to a fault or use of an incorrect wall adapter,

OVGATE will be pulled to GND, disabling the external FET

to protect downstream circuitry. When the voltage drops

below 6V again, the external FET will be re-enabled.

In an overvoltage condition, the OVSENS pin will be

clamped at 6V. The external 6.2k resistor must be

sized appropriately to dissipate the resultant power.

For example, a 1/10W 6.2k resistor can have at most

√PMAX • 6.2k = 24V applied across its terminals. With

the 6V at OVSENS, the maximum overvoltage magnitude

that this resistor can withstand is 30V. A 1/4W 6.2k resis-

tor raises this value to 45V.

The charge pump output on OVGATE has limited output

drive capability. Care must be taken to avoid leakage on

this pin, as it may adversely affect operation.

Dual Input Overvoltage Protection

It is possible to protect both VBUS and WALL from

overvoltage damage with several additional components,

as shown in Figure 10. Schottky diodes D1 and D2 pass

the larger of V1 and V2 to R1 and OVSENS. If either V1 or

V2 exceeds 6V plus VF(SCHOTTKY), OVGATE will be pulled to

GND and both the WALL and USB inputs will be protected.

LTC3577/LTC3577-1

3577fa

C1D1

MN2

MN1

3577 F10

WALL

OVGATE

LTC3577

VBUS

OVSENS

Figure 10. Dual Input Overvoltage Protection

OPERATION

Each input is protected up to the drain-source breakdown,

BVDSS, of MN1 and MN2. R1 must also be rated for the

power dissipated during maximum overvoltage. See the

“Overvoltage Protection” section for an explanation of

this calculation. Table 2 shows some NMOS FETs that are

suitable for overvoltage protection.

Table 2. Recommended Overvoltage FETs

NMOS FET BVDSS RON PACKAGE

Si1472DH 30V 82mΩ SC70-6

Si2302ADS 20V 60mΩ SOT-23

Si2306BDS 30V 65mΩ SOT-23

Si2316BDS 30V 80mΩ SOT-23

IRLML2502 20V 35mΩ SOT-23

Reverse Input Voltage Protection

The LTC3577 can also be easily protected against the

application of reverse voltage as shown in Figure 10. D1

and R1 are necessary to limit the maximum VGS seen by

MP1 during positive overvoltage events. D1’s breakdown

voltage must be safely below MP1’s BVGS. The circuit

shown in Figure 11 offers forward voltage protection up

to MN1’s BVDSS and reverse voltage protection up to

MP1’s BVDSS.

LOW DROPOUT LINEAR REGULATOR OPERATION

LDO Operation and Voltage Programming

The LTC3577 contains two 150mA adjustable output LDO

regulators. To enable the LDOs write a 1 to the LDO1EN

and/or LDO2EN I2C registers. The LDOs can be disabled

three ways: 1) Write a 0 to the LDO1EN and LDO2EN

registers; 2) Bring DVCC below the DVCC undervoltage

threshold; 3) Enter the power-down pushbutton state.

0.8V

LDOx

OUTPUT

COUT

3577 F12

VINLDOx

GND

LDOx_FB

LDOx

LDOxEN

Figure 12. LDO Application Circuit

The LDOs are further disabled if VOUT falls below the VOUT

UVLO threshold and cannot be enabled until the UVLO

condition is removed.

When disabled all LDO circuitry is powered off leaving only

a few nanoamps of leakage current on the LDO supply.

The LDO outputs are individually pulled to ground through

internal resistors when disabled.

The power good status bits of LDO1 and LDO2 are avail-

able in I2C through the read-back registers PGLDO[1] and

PGLDO[2] for LDO1 and LDO2 respectively. The power

good comparators for both LDOs are sampled when the

I2C port receives the correct I2C read address.

Figure 12 shows the LDO application circuit. The full-

scale output voltage for each LDO is programmed using

a resistor divider from the LDO output (LDO1 or LDO2)

connected to the feedback pins (LDO1_FB or LDO2_FB)

such that:

VLDOx =0.8V • R1

R2 +1

⎛

⎝

⎜⎞

⎠

⎟

D1 C1

6.2k

500k

D1: 5.6V ZENER

MP1: Si2323DS, BVDSS = 20V

VBUS POSITIVE PROTECTION UP TO BVDSS OF MN1

VBUS NEGATIVE PROTECTION UP TO BVDSS OF MP1

MN1MP1

USB/WALL

ADAPTER

3577 F11

VBUS

OVGATE

LTC3577

OVSENS

Figure 11. Dual Polarity Voltage Protection

LTC3577/LTC3577-1

3577fa

OPERATION

For stability, each LDO output must be bypassed to ground

with a minimum 1F ceramic capacitor (COUT).

LDO Operating as a Current Limited Switch

The LDO can be used as a current limited switch by simply

connecting the LDOx_FB input to ground. In this case

the LDOx output will be pulled up to VINLDOx through the

LDO’s internal current limit (about 300mA). Enabling the

LDO via the I2C interface effectively connects LDOx and

VINLDOx, while disabling the LDO disconnected LDOx

from VINLDOx.

STEP-DOWN SWITCHING REGULATOR OPERATION

Introduction

The LTC3577 includes three 2.25MHz constant frequency

current mode step-down switching regulators providing

500mA, 500mA and 800mA each. All step-down switch-

ing regulators can be programmed for a minimum output

voltage of 0.8V and can be used to power a microcontroller

core, microcontroller I/O, memory or other logic circuitry.

All step-down switching regulators support 100% duty

cycle operation (low dropout mode) when the input volt-

age drops very close to the output voltage and are also

capable of Burst Mode operation for highest efﬁ ciencies

at light loads. Burst Mode operation is individually select-

able for each step-down switching regulator through the

I2C register bits BK1BRST, BK2BRST and BK3BRST. The

step-down switching regulators also include soft-start to

limit inrush current when powering on, short-circuit cur-

rent protection, and switch node slew limiting circuitry

to reduce EMI radiation. No external compensation com-

ponents are required for the switching regulators. The

regulators are sequenced up and down together through

the pushbutton interface (see the “Pushbutton Interface”

section for more information). It is recommended that

the step-down switching regulator input supplies (VIN12

and VIN3) be connected to the system supply pin (VOUT).

This is recommended because the undervoltage lockout

circuit on the VOUT pin (VOUT UVLO) disables the step-

down switching regulators when the VOUT voltage drops

below the VOUT UVLO threshold. If driving the step-down

switching regulator input supplies from a voltage other

than VOUT the regulators should not be operated outside

the speciﬁ ed operating range as operation is not guaranteed

beyond this range.

Output Voltage Programming

Figure 13 shows the step-down switching regulator ap-

plication circuit. The full-scale output voltage for each

step-down switching regulator is programmed using a

resistor divider from the step-down switching regulator

output connected to the feedback pins (FB1, FB2 and

FB3) such that:

VOUTx =0.8V • R1

R2 +1

⎛

⎝

⎜⎞

⎠

⎟

Typical values for R1 are in the range of 40k to 1M. The

capacitor CFB cancels the pole created by feedback resis-

tors and the input capacitance of the FB pin and also helps

to improve transient response for output voltages much

greater than 0.8V. A variety of capacitor sizes can be used

for CFB but a value of 10pF is recommended for most ap-

plications. Experimentation with capacitor sizes between

2pF and 22pF may yield improved transient response.

PG_DCDC Operation

The PG_DCDC pin is an open-drain output used to indi-

cate that all step-down switching regulators are enabled

and have reached their ﬁ nal regulation voltage. A 230ms

delay is included from the time all switching regulators

reach 92% of their regulation value to allow a system

controller ample time to reset itself. PG_DCDC may be

used as a power-on reset to a microprocessor powered

by the step-down switching regulators. PG_DCDC is an

0.8V

VOUTx

COUT

CFB

3577 F13

MODE

SLEW

VIN

GND

FBx

SWx

PWM

CONTROL

Figure 13. Step-Down Switching Regulator Application Circuit

LTC3577/LTC3577-1

3577fa

OPERATION

open-drain output and requires a pull-up resistor to an

appropriate power source. Optimally the pull-up resistor

is connected to one of the step-down switching regulator

output voltages so that power is not dissipated while the

regulators are disabled.

Operating Modes

The step-down switching regulators include two possible

operating modes to meet the noise/power needs of a variety

of applications. In pulse-skipping mode, an internal latch

is set at the start of every cycle, which turns on the main

P-channel MOSFET switch. During each cycle, a current

comparator compares the peak inductor current to the

output of an error ampliﬁ er. The output of the current

comparator resets the internal latch, which causes the main

P-channel MOSFET switch to turn off and the N-channel

MOSFET synchronous rectiﬁ er to turn on. The N-channel

MOSFET synchronous rectiﬁ er turns off at the end of the

2.25MHz cycle or if the current through the N-channel

MOSFET synchronous rectiﬁ er drops to zero. Using this

method of operation, the error ampliﬁ er adjusts the peak

inductor current to deliver the required output power. All

necessary compensation is internal to the step-down

switching regulator requiring only a single ceramic output

capacitor for stability. At light loads in pulse-skipping mode,

the inductor current may reach zero on each pulse which

will turn off the N-channel MOSFET synchronous rectiﬁ er.

In this case, the switch node (SW1, SW2 or SW3) goes

high impedance and the switch node voltage will ring. This

is discontinuous operation, and is normal behavior for a

switching regulator. At very light loads in pulse-skipping

mode, the step-down switching regulators will automati-

cally skip pulses as needed to maintain output regulation.

At high duty cycle (VOUTX approaching VINX) it is possible

for the inductor current to reverse at light loads causing

the stepped down switching regulator to operate continu-

ously. When operating continuously, regulation and low

noise output voltage are maintained, but input operating

current will increase to a few milliamps.

In Burst Mode operation, the step-down switching regula-

tors automatically switch between ﬁ xed frequency PWM

operation and hysteretic control as a function of the load

current. At light loads the step-down switching regulators

control the inductor current directly and use a hysteretic

control loop to minimize both noise and switching losses.

While operating in Burst Mode operation, the output

capacitor is charged to a voltage slightly higher than the

regulation point. The step-down switching regulator then

goes into sleep mode, during which the output capacitor

provides the load current. In sleep mode, most of the

switching regulator’s circuitry is powered down, helping

conserve battery power. When the output voltage drops

below a pre-determined value, the step-down switching

regulator circuitry is powered on and another burst cycle

begins. The sleep time decreases as the load current

increases. Beyond a certain load current point (about

1/4 rated output load current) the step-down switching

regulators will switch to a low noise constant frequency

PWM mode of operation, much the same as pulse-skip-

ping operation at high loads.

For applications that can tolerate some output ripple at low

output currents, Burst Mode operation provides better ef-

ﬁ ciency than pulse-skipping at light loads. The step-down

switching regulators allow mode transition on-the-ﬂ y,

providing seamless transition between modes even under

load. This allows the user to switch back and forth between

modes to reduce output ripple or increase low current ef-

ﬁ ciency as needed. Burst Mode operation is individually

selectable for each step-down switching regulator through

the I2C register bits BK1BRST, BK2BRST and BK3BRST.

Shutdown

The step-down switching regulators are shut down when

the pushbutton circuitry is in the power-down, power

off or hard reset states. In shutdown all circuitry in the

step-down switching regulator is disconnected from

the switching regulator input supply leaving only a few

nanoamps of leakage current. The step-down switching

regulator outputs are individually pulled to ground through

internal 10k resistors on the switch pin (SW1, SW2 or

SW3) when in shutdown.

Dropout Operation

It is possible for a step-down switching regulator’s input

voltage to approach its programmed output voltage (e.g., a

battery voltage of 3.4V with a programmed output voltage

of 3.3V). When this happens, the PMOS switch duty cycle

LTC3577/LTC3577-1

3577fa

OPERATION

increases until it is turned on continuously at 100%. In this

dropout condition, the respective output voltage equals the

regulator’s input voltage minus the voltage drops across

the internal P-channel MOSFET and the inductor.

Soft-Start Operation

Soft-start is accomplished by gradually increasing the peak

inductor current for each step-down switching regulator

over a 500s period. This allows each output to rise slowly,

helping minimize inrush current required to charge up the

switching regulator output capacitor. A soft-start cycle

occurs whenever a given switching regulator is enabled.

A soft-start cycle is not triggered by changing operating

modes. This allows seamless output transition when

actively changing between operating modes.

Slew Rate Control

The step-down switching regulators contain new patent

pending circuitry to limit the slew rate of the switch node

(SW1, SW2 and SW3). This new circuitry is designed to

transition the switch node over a period of a few nanosec-

onds, signiﬁ cantly reducing radiated EMI and conducted

supply noise while maintaining high efﬁ ciency. Since

slowing the slew rate of the switch nodes causes efﬁ ciency

loss, the slew rate of the step-down switching regulators is

adjustable via the I2C registers SLEWCTL1 and SLEWCTL2.

This allows the user to optimize efﬁ ciency or EMI as neces-

sary with four different slew rate settings. The power-up

default is the fastest slew rate (highest efﬁ ciency) setting.

Figures 14 and 15 show the efﬁ ciency and power loss

graph for Buck3 programmed for 1.2V and 2.5V outputs.

Note that the power loss curves remain fairly constant for

both graphs yet changing the slew rate has a larger effect

on the 1.2V output efﬁ ciency. This is mainly because for

a given output current the 2.5V output is delivering more

than 2x the power than the 1.2V output. Efﬁ ciency will

always decrease and show more variation to slew rate as

the programmed output voltage is decreased.

Low Supply Operation

An undervoltage lockout circuit on VOUT (VOUT UVLO)

shuts down the step-down switching regulators when VOUT

drops below about 2.7V. It is recommended that the step-

down switching regulator input supplies (VIN12, VIN3) be

connected to the power path output (VOUT) directly. This

UVLO prevents the step-down switching regulators from

operating at low supply voltages where loss of regula-

tion or other undesirable operation may occur. If driving

the step-down switching regulator input supplies from

a voltage other than the VOUT pin, the regulators should

not be operated outside the speciﬁ ed operating range as

operation is not guaranteed beyond this range.

Inductor Selection

Many different sizes and shapes of inductors are available

from numerous manufacturers. Choosing the right inductor

from such a large selection of devices can be overwhelming,

but following a few basic guidelines will make the selection

Figure 14. VOUT3 (1.2V) Efﬁ ciency and Power Loss vs IOUT3 Figure 15. VOUT3 (2.5V) Efﬁ ciency and Power Loss vs IOUT3

IOUT3 (mA)

1.00E-05

EFFICIENCY (%)

POWER LOSS (W)

100

1.00E-01

3577 F14

1.00E-02

1.00e-01

1.00E+00

1.00E-03

1.00E-04

1.00E-05

1.00E-0.3

Burst Mode

OPERATION

VIN = 3.8V

SW[1:0] =00

IOUT3 (mA)

1.00E-05

EFFICIENCY (%)

POWER LOSS (W)

100

1.00E-01

3577 F15

1.00E-02

1.00e-01

1.00E+00

1.00E-03

1.00E-04

1.00E-05

1.00E-0.3

Burst Mode

OPERATION

VIN = 3.8V

SW[1:0] =00

LTC3577/LTC3577-1

3577fa

OPERATION

process much simpler. The step-down switching regula-

tors are designed to work with inductors in the range of

2.2H to 10H. For most applications a 4.7H inductor is

suggested for step-down switching regulators providing

up to 500mA of output current while a 3.3H inductor is

suggested for step-down switching regulators providing

up to 800mA. Larger value inductors reduce ripple current,

which improves output ripple voltage. Lower value induc-

tors result in higher ripple current and improved transient

response time, but will reduce the available output current.

To maximize efﬁ ciency, choose an inductor with a low DC

resistance. For a 1.2V output, efﬁ ciency is reduced about

2% for 100m series resistance at 400mA load current,

and about 2% for 300m series resistance at 100mA load

current. Choose an inductor with a DC current rating at

least 1.5 times larger than the maximum load current to

ensure that the inductor does not saturate during normal

operation. If output short-circuit is a possible condition,

the inductor should be rated to handle the maximum peak

current speciﬁ ed for the step-down converters. Different

core materials and shapes will change the size/current

and price/current relationship of an inductor. Toroid or

shielded pot cores in ferrite or Permalloy materials are

small and don’t radiate much energy, but generally cost

more than powdered iron core inductors with similar

electrical characteristics. Inductors that are very thin or

have a very small volume typically have much higher core

and DCR losses, and will not give the best efﬁ ciency. The

choice of which style inductor to use often depends more

on the price versus size, performance, and any radiated

EMI requirements than on what the step-down switching

regulators requires to operate. The inductor value also has

an effect on Burst Mode operation. Lower inductor values

will cause Burst Mode switching frequency to increase.

Table 3 shows several inductors that work well with the

step-down switching regulators. These inductors offer a

good compromise in current rating, DCR and physical

size. Consult each manufacturer for detailed information

on their entire selection of inductors.

Input/Output Capacitor Selection

Low ESR (equivalent series resistance) ceramic capacitors

should be used at both step-down switching regulator

outputs as well as at each step-down switching regulator

input supply. Only X5R or X7R ceramic capacitors should

be used because they retain their capacitance over wider

voltage and temperature ranges than other ceramic types.

A 10F output capacitor is sufﬁ cient for the step-down

switching regulator outputs. For good transient response

Table 3. Recommended Inductors for Step-Down Switching Regulators

INDUCTOR TYPE L (H) MAX IDC (A) MAX DCR () SIZE in mm (L × W × H) MANUFACTURER

DB318C

D312C

DE2812C

4.7

3.3

4.7

3.3

4.7

3.3

1.07

1.20

0.79

0.90

1.15

1.37

0.1

0.07

0.24

0.20

0.13*

0.105*

3.8 × 3.8 × 1.8

3.6 × 3.6 × 1.2

3.0 × 2.8 × 1.2

Toko

www.toko.com

CDRH3D16

CDRH2D11

CLS4D09

4.7

3.3

4.7

3.3

4.7

0.9

1.1

0.5

0.6

0.75

0.11

0.085

0.17

0.123

0.19

4 × 4 × 1.8

3.2 × 3.2 × 1.2

4.9 × 4.9 × 1

Sumida

www.sumida.com

SD3118

SD3112

SD12

SD10

4.7

3.3

4.7

3.3

4.7

3.3

4.7

3.3

1.3

1.59

0.8

0.97

1.29

1.42

1.08

1.31

0.162

0.113

0.246

0.165

0.117*

0.104*

0.153*

0.108*

3.1 × 3.1 × 1.8

3.1 × 3.1 × 1.2

5.2 × 5.2 × 1.2

5.2 × 5.2 × 1.0

Cooper

www.cooperet.com

LPS3015 4.7

3.3 1.1

1.3 0.2

0.13 3.0 × 3.0 × 1.5

3.0 × 3.0 × 1.5

Coil Craft

www.coilcraft.com

*Typical DCR

LTC3577/LTC3577-1

3577fa

OPERATION

and stability the output capacitor for step-down switching

regulators should retain at least 4F of capacitance over

operating temperature and bias voltage. Each switching

regulator input supply should be bypassed with a 2.2F

capacitor. Consult with capacitor manufacturers for de-

tailed information on their selection and speciﬁ cations

of ceramic capacitors. Many manufacturers now offer

very thin (<1mm tall) ceramic capacitors ideal for use in

height-restricted designs. Table 4 shows a list of several

ceramic capacitor manufacturers.

Table 4. Ceramic Capacitor Manufacturers

AVX www.avxcorp.com

Murata www.murata.com

Taiyo Yuden www.t-yuden.com

Vishay Siliconix www.vishay.com

TDK www.tdk.com

LED BACKLIGHT/BOOST OPERATION

Introduction

The LED driver uses a constant frequency, current mode

boost converter to supply power to up to 10 series LEDs.

As shown in Figure 16 the series string of LEDs is con-

nected from the output of the boost converter (BOOST) to

the ILED pin. Under normal operation the boost converter

BOOST output will be driven to a voltage where the ILED

pin regulates at 300mV. The ILED pin is a constant-current

sink that is programmed via I2C “LED DAC register”. The

LED can be further controlled using I2C to program bright-

ness levels and soft turn-on/turn-off effects. See the “I2C

Interface” section for more information on programming

the ILED current. The boost converter also includes an

overvoltage protection feature to limit the BOOST output

voltage as well as variable slew rate control of the SW pin

to reduce EMI.

LED Boost Operation

The LED boost converter is designed for very high duty

cycle operation and can boost from 3V to 40V for load

currents up to 20mA. The boost converter also features

an overvoltage protection feature to protect the output in

case of an open circuit in the LED string. The overvoltage

protection threshold is set by adjusting R1 in Figure 16

such that:

BOOST(MAX) =800mV • R1

10 •R2 +LED_OV

where LED_OV is about 1.0V.

In the case of Figure 16 BOOST(MAX) is set to 40V for a

10-LED string.

Capacitor C3 provides soft-start, limiting the inrush cur-

rent when the boost converter is ﬁ rst enabled. C3 provides

feedback to the ILED pin. This feedback limits the rise time

of output voltage and the inrush current while the output

capacitor, C2, is charging.

The boost converter will be operated in either continuous

conduction mode, discontinuous conduction mode or

pulse-skipping mode depending on the inductor current

required for regulation.

1µF

50V

22nF

50V

D12

ZLLS400

22µF

10M

20k

10µH

LPS4018-103ML

BOOST

3577 F16

VOUT

LED_OV

ILED_FS

ILED

LTC3577

D2 D3 D4 D5

D10 D9 D8 D7 D6

Figure 16. LED Boost Application Circuit

LED Constant Current Sink

The LED driver uses a precision current sink to regulate the

LED current up to 20mA. The current sink is programmed

via I2C “LED DAC Register” and utilizes a 6-bit 60dB expo-

nential DAC. This DAC provides accurate current control

from 20A to 20mA with approximately 1dB per step for

ILED(FS) = 20mA. The LED current can be approximated

by the following equations:

ILED =ILED(FS) •10

3 • DAC – 63

⎛

⎝

⎜⎞

⎠

⎟

ILED(FS) =0.8V

R2 • 500

(1)

LTC3577/LTC3577-1

3577fa

OPERATION

where DAC is the decimal value programmed into the I2C

“LED DAC register”. For example with ILED(FS) = 20mA and

DAC[5:0] = 000000 (0 decimal) ILED equates to 20A, while

DAC[5:0] = 111111 (63 decimal) ILED equates to 20mA. As a

ﬁ nal example DAC[5:0] = 101010 is 42 decimal and equates

to ILED = 2mA for ILED(FS) = 20mA. The DAC approximates

the Equation 1 using the nominal values in Table 5. The

differences between the approximation equation and the

table are due to design of the DAC using eight linear seg-

ments that approximate the exponential function.

Table 5. LED DAC Codes to Output Current

DAC Codes Output Current DAC Codes Output Current

0 20.0µA 32 668µA

1 23.5µA 33 786µA

2 27.0µA 34 903µA

3 30.5µA 35 1.02mA

4 34.0µA 36 1.14mA

5 37.6µA 37 1.26mA

6 41.1µA 38 1.37mA

7 44.6µA 39 1.49mA

8 48.1µA 40 1.61mA

9 56.5µA 41 1.89mA

10 65.0µA 42 2.17mA

11 73.4µA 43 2.45mA

12 81.9µA 44 2.74mA

13 90.3µA 45 3.02mA

14 98.7µA 46 3.30mA

15 107µA 47 3.58mA

16 116µA 48 3.86mA

17 136µA 49 4.54mA

18 156µA 50 5.22mA

19 177µA 51 5.90mA

20 197µA 52 6.58mA

21 217µA 53 7.26mA

22 237µA 54 7.93mA

23 258µA 55 8.61mA

24 278µA 56 9.29mA

25 327µA 57 10.8mA

26 376µA 58 12.4mA

27 424µA 59 13.9mA

28 473µA 60 15.4mA

29 522µA 61 17.0mA

30 571µA 62 18.5mA

31 620µA 63 20.0mA

The full-scale LED current is set using a resistor (R2 in

Figure 16) connected between the LED_FS pin and ground.

Typically R2 should be set to 20k to give 20mA of LED

current at full-scale. The resistance may be increased to

decrease the current or the resistance may be decreased

to increase the LED current. The DAC has been optimized

for best performance at 20mA full-scale. The full-scale

current may be adjusted but the accuracy of the output

current will be degraded the further it is programmed

from 20mA. The LED_FS pin is current limited and will

only source about 80µA. This protects the pin and limits

the ILED current in a case where LED_FS is shorted to

ground, it is not recommended to program the LED cur-

rent above 25mA.

LED Gradation

The LED driver features an automatic gradation circuit.

The gradation circuit ramps the LED current up when

the LED driver is enabled and ramps the current down

when the LED driver is disabled. The DAC is enabled and

disabled with the EN bit of the I2C “LED control register.”

The gradation function is automatic when enabling and

disabling the LED driver; only the gradation speed needs to

be programmed to use this function. The gradation speed

is set by the GR1 and GR2 bits of the I2C “LED control

15ms, one-half second, one second and two seconds.

See the “I2C Interface” section for more information. The

gradation function allows the LEDs to turn on and off

gradually as opposed to an abrupt step.

LED PWM vs Constant Current Operation

The LED driver provides both linear LED current mode as

well as PWM LED current mode. These modes are selected

through the MD1 and MD2 bits of the I2C “LED control

in constant current (CC) mode and the ILED current sink

is constant whose value is set by the DAC[5:0] bits of the

I2C “LED DAC register.”

Setting MD1 to 0 and MD2 to 1 selects the LED PWM mode.

In this mode the LED driver is pulsed using an internally

generated PWM signal. The PWM mode may be used to re-

duce the LED intensity for a given programmed current.

LTC3577/LTC3577-1

3577fa

OPERATION

When dimming via PWM the LED driver and boost converter

are both turned on and off together. This allows some

degree of additional control over the LED current, and in

some cases may offer a more efﬁ cient method of dimming

since the boost could be operated at an optimal efﬁ ciency

point and then pulsed for the desired LED intensity.

The PWM mode, if enabled, is set up using 3 values;

PWMNUM[3:0] and PWMDEN[3:0] in the I2C “LED PWM

the I2C “LED Control Register.”

Duty Cycle =PWMNUM

PWMDEN

Frequency =PWMCLK

PWMDEN

Table 6. PWM Clock Frequency

PWMC2 PWMC1 PWMCLK

0 0 8.77kHz

0 1 4.39kHz

1 0 2.92kHz

1 1 2.19kHz

Using the PWM control, a 4-bit internally generated PWM is

possible as additional dimming. Using these control bits a

number of PWM duty cycles and frequencies are available

in the 100Hz to 500Hz range. This range was selected to

be below the audio range and above the frequency where

the PWM is visible.

For example, given PWMC2 = 1, PWMC1 = 0, PWM-

NUM[3:0] = 0111 and PWMDEN[3:0] = 1100 then the duty

cycle will be 58.3% and PWM frequency will be 243Hz.

If PWMNUM is set to 0 then the duty cycle will be 0%

and the current sink will effectively be off. If PWMNUM

is programmed to a value larger than PWMDEN the duty

cycle will be 100% and the current sink will effectively be

constant. PWMDEN and PWMNUM may both be changed

to result in 73 different duty cycle possibilities and 41 dif-

ferent PWM frequencies between 8.77kHz and 100Hz.

When PWM mode is enabled, a small (2µA) standby current

source is always enabled on the ILED pin. The purpose of

this is to have some current ﬂ owing in the LEDs at all times.

This helps to reduce the magnitude of the voltage swing

on the ILED pin as the current is pulsed on and off.

Fixed Boost Output

Setting MD1 to 1 and MD2 to 0 selects the ﬁ xed high voltage

boost mode. This mode can be used to generate output

voltages at or greater than VOUT

. When conﬁ gured as a

boost converter the ILED pin becomes the feedback pin,

and will regulate the output voltage such that the voltage

on the ILED pin is 800mV.

Figure 17 shows a ﬁ xed 12V output generated using the

boost converter in the ﬁ xed high voltage boost mode. Any

output voltage up to 40V may be programmed by select-

ing appropriate values for the R1 and R2 voltage divider

from the equation:

VBOOST =0.8V • R1

R2 +1

⎛

⎝

⎜⎞

⎠

⎟

Values for R2 should be kept below 24.3k to keep the pole

at ILED beyond cross over.

The boost is designed primarily as a high voltage, high duty

cycle converter. When operating with a lower boost ratio,

a larger output capacitor, 10µF, should be used. Operating

with a very low duty cycle will cause cycle skipping which

will increase ripple.

10µF

10V

D12

ZLLS400

800mV VREF

22µF

301k

21.5k

10µH

LPS4018-103ML

BOOST

3577 F17

VOUT

ILED_FS

ILED

LED_OV

LTC3577

Figure 17. Fixed 12V/75mA Boost Output Application

LTC3577/LTC3577-1

3577fa

OPERATION

To keep the average steady-state inductor current below

300mA the maximum output current is reduced as pro-

grammed output voltage increases. The output current

available is given by:

IBOOST(MAX) =300mA • VOUT(MIN)

VBOOST

Note that the maximum boost output current must be

set by the minimum VOUT operating voltage. If the boost

converter is allowed to operate down to the VOUT UVLO

then 2.5V must be assumed as the minimum operating

VOUT voltage.

Inductor Selection

The LED boost converter is designed to work with a 10H

inductor. The inductor must be able to handle a peak

current of 1A and should have a low ESR value for good

efﬁ ciency. Table 7 shows several inductors that work

well with the LED boost converter. These inductors offer

a good compromise in current rating, DCR and physical

size. Consult each manufacturer for detailed information

on their entire selection of inductors.

Diode Selection

When boosting to increasingly higher voltages, parasitic

capacitance at the switch pin becomes an increasing

large component of the switching loses. For this reason

it is important to minimize the capacitance on the switch

node. The diode selected should be sized to handle the

peak inductor current and the average output current.

At high boost voltages a diode with the lowest possible

junction capacitance will often result in a more efﬁ cient

solution than one with a lower forward drop.

I2C OPERATION

I2C Interface

The LTC3577 may communicate with a bus master using

the standard I2C 2-wire interface. The Timing Diagram

shows the relationship of the signals on the bus. The two

bus lines, SDA and SCL, must be high when the bus is

not in use. External pull-up resistors or current sources,

such as the LTC1694 SMBus accelerator, are required

on these lines. The LTC3577 is both a slave receiver and

slave transmitter. The I2C control signals, SDA and SCL

are scaled internally to the DVCC supply. DVCC should be

connected to the same power supply as the bus pull-up

resistors.

The I2C port has an undervoltage lockout on the DVCC pin.

When DVCC is below approximately 1V , the I2C serial port

is cleared, the LTC3577 is set to its default conﬁ guration

of all zeros.

Table 7. Recommended Inductors for Boost Switching Regulators

INDUCTOR TYPE L (H) MAX IDC (A) MAX DCR () SIZE in mm (L × W × H) MANUFACTURER

DB62LCB 10 1.22 0.118 6.2 × 6.2 × 2 Toko

www.toko.com

CDRH4D16NP-100M 10 10.5 0.155 4.8 × 4.8 × 1.8 Sumida

www.sumida.com

SD18-100-R 10 1.28 0.158* 5.2 × 5.2 × 1.8 Cooper

www.cooperet.com

LPS4018-103 10 1.1 0.200 4.0 × 4.0 × 1.8 Coil Craft

www.coilcraft.com

*Typical

LTC3577/LTC3577-1

3577fa

OPERATION

I2C Bus Speed

The I2C port is designed to be operated at speeds of up

to 400kHz. It has built-in timing delays to ensure correct

operation when addressed from an I2C compliant master

device. It also contains input ﬁ lters designed to suppress

glitches should the bus become corrupted.

I2C START and STOP Conditions

A bus master signals the beginning of communications

by transmitting a START condition. A START condition is

generated by transitioning SDA from HIGH to LOW while

SCL is HIGH. The master may transmit either the slave

write or the slave read address. Once data is written to the

LTC3577, the master may transmit a STOP condition which

commands the LTC3577 to act upon its new command set.

A STOP condition is sent by the master by transitioning

SDA from LOW to HIGH while SCL is HIGH. The bus is

then free for communication with another I2C device.

I2C Byte Format

Each byte sent to or received from the LTC3577 must

be 8 bits long followed by an extra clock cycle for the

acknowledge bit. The data should be sent to the LTC3577

most signiﬁ cant bit (MSB) ﬁ rst.

I2C Acknowledge

The acknowledge signal is used for handshaking between

the master and the slave. When the LTC3577 is written

to (write address), it acknowledges its write address as

well as the subsequent two data bytes. When it is read

from (read address), the LTC3577 acknowledges its read

address only. The bus master should acknowledge receipt

of information from the LTC3577.

An acknowledge (active LOW) generated by the LTC3577

lets the master know that the latest byte of information was

received. The acknowledge related clock pulse is generated

by the master. The master releases the SDA line (HIGH)

during the acknowledge clock cycle. The LTC3577 pulls

down the SDA line during the write acknowledge clock

pulse so that it is a stable LOW during the HIGH period

of this clock pulse.

When the LTC3577 is read from, it releases the SDA line so

that the master may acknowledge receipt of the data. Since

the LTC3577 only transmits one byte of data, a master not

acknowledging the data sent by the LTC3577 has no I2C

speciﬁ c consequence on the operation of the I2C port.

I2C Timing Diagram

tSU, DAT

tHD, STA

tHD, DAT

SDA

SCL

tSU, STA

tHD, STA tSU, STO

3577 TD

tBUF

tLOW

tHIGH

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

START

CONDITION

trtf

tSP

ACK ACK

123

ADDRESS WR

456789123456789123456789

00 01 0 01 0

00010010 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0

ACK

STOPSTART

SDA

SCL

DATA BYTE A DATA BYTE B

LTC3577/LTC3577-1

3577fa

OPERATION

I2C Slave Address

The LTC3577 responds to a 7-bit address which has been

factory programmed to b’0001001[R/W]’. The LSB of

the address byte, known as the read/write bit, should be

0 when writing data to the LTC3577 and 1 when reading

data from it. Considering the address an eight bit word,

then the write address is 0x12 and the read address is

0x13. The LTC3577 will acknowledge both its read and

write address.

I2C Sub-Addressed Writing

The LTC3577 has four command registers for control

input. They are accessed by the I2C port via a sub-

addressed writing system.

Each write cycle of the LTC3577 consists of exactly three

bytes. The ﬁ rst byte is always the LTC3577’s write address.

The second byte represents the LTC3577’s sub-address.

The sub address is a pointer which directs the subsequent

data byte within the LTC3577. The third byte consists of

the data to be written to the location pointed to by the sub-

address. The LTC3577 contains control registers at only

four sub-address locations: 0x00, 0x01, 0x02 and 0x03.

Writing to sub-addresses outside the four sub-addresses

listed is not recommended as it can cause data in one of

the four listed sub-addresses to be overwritten.

I2C Bus Write Operation

The master initiates communication with the LTC3577

with a START condition and the LTC3577’s write address.

If the address matches that of the LTC3577, the LTC3577

returns an acknowledge. The master should then deliver

the sub-address. Again the LTC3577 acknowledges and

the cycle is repeated for the data byte. The data byte is

transferred to an internal holding latch upon the return of

its acknowledge by the LTC3577. This procedure must be

repeated for each sub-address that requires new data. After

one or more cycles of [ADDRESS][SUB-ADDRESS][DATA],

the master may terminate the communication with a STOP

condition. Alternatively, a REPEAT-START condition can be

initiated by the master and another chip on the I2C bus can

be addressed. This cycle can continue indeﬁ nitely and the

LTC3577 will remember the last input of valid data that it

received. Once all chips on the bus have been addressed

and sent valid data, a global STOP can be sent and the

LTC3577 will update its command latches with the data

that it had received.

I2C Bus Read Operation

The bus master reads the status of the LTC3577 with a

START condition followed by the LTC3577 read address. If

the read address matches that of the LTC3577, the LTC3577

returns an acknowledge. Following the acknowledgement

of its read address the LTC3577 returns one bit of status

information for each of the next 8 clock cycles. A STOP

command is not required for the bus read operation.

I2C Input Data

There are 4 bytes of data that can be written to on the

LTC3577. The bytes are accessed through the sub-

addresses 0x00 to 0x03. At ﬁ rst power application (VBUS,

WALL or BAT) all bits default to 0. Additionally all bits are

cleared to 0 when DVCC drops below its undervoltage lock

out or if the pushbutton enters the power-down (PDN1

or PDN2) state.

Table 8. LDO and Buck Control Register

LDO and BUCK

CONTROL REGISTER

ADDRESS: 00010010

SUB-ADDRESS: 00000000

BIT NAME FUNCTION

B0 LDO1EN Enable LDO 1

B1 LDO2EN Enable LDO 2

B2 BK1BRST Buck1 Burst Mode Enable

B3 BK2BRST Buck2 Burst Mode Enable

B4 BK3BRST Buck2 Burst Mode Enable

B5 SLEWCTL1 Buck SW Slew Rate: 00 = 1ns,

01 = 2ns, 10 = 4ns, 11 = 8ns

B6 SLEWCTL2

B7 N/A Not Used—No Effect on Operation

Table 8 shows the ﬁ rst byte of data that can be written to

at sub-address 0x00. This byte of data is referred to as

the “LDO and buck control register.”

Bits B0 and B1 enable and disable the LDOs. Writing 1

to B0 or B1 will enable LDO1 or LDO2 respectively, while

writing a 0 will disable the respective LDO.

LTC3577/LTC3577-1

3577fa

OPERATION

Bits B2, B3, and B4 set the operating modes of the step-

down switching regulators (bucks). Writing 1 to any of

these three registers will put that respective buck converter

in the high efﬁ ciency Burst Mode operation, while a 0 will

enable the low noise pulse-skipping mode operation.

The B5 and B6 bits adjust the slew rate of all SW pins

together so they all slew at the same rate. It is recom-

mended that the fastest slew rate (B6:B5 = 00) be used

unless EMI is an issue in the application as slower slew

rates cause reduced efﬁ ciency.

Table 9. I2C LED Control Register

LED CONTROL

ADDRESS: 00010010

SUB-ADDRESS: 00000001

BIT NAME FUNCTION

B0 EN Enable: 1 = Enable 0 = Off

B1 GR2 Gradation GR[2:1]: 00 = 15ms, 01 = 460ms,

10 = 930ms, 11 = 1.85s

B2 GR1

B3 MD1 Mode MD[2:1]: 00 = CC Boost,

10 = PWM Boost; 01 = HV Boost

B4 MD2

B5 PWMC1 PWM CLK PWMC[2:1]: 00 = 8.77kHz,

01 = 4.39kHz, 10 = 2.92kHz, 11 = 2.19kHz

B6 PWMC2

B7 SLEWLED LED SW Slew Rate: 0/1 = Fast/Slow

Table 9 shows the second byte of data that can be written

to at sub-address 0x01. This byte of data is referred to as

the “LED control register.”

Bit B0 enables and disables the LED boost circuitry. Writing

a 1 to B0 enables the LED boost circuitry, while writing a

0 disables the LED boost circuitry.

Bits B1 and B2 are the LED gradation which sets the ramp

up and down time of the LED current when enabled or

disabled. The gradation function allows the LEDs to turn

on/off gradually as opposed to an abrupt step.

Bits B3 and B4 set the operating mode of the LED boost

circuitry. The operating modes are: B4:B3 = 00 LED

constant current (CC) boost operation; B4:B3 = 10 LED

PWM boost operation; B4:B3 = 01 ﬁ xed high voltage (HV)

output boost operation; B4:B3 = 11 not supported, do not

use. See the “LED Backlight/Boost Operation” section for

more information on the operating modes.

Bits B5 and B6 set the PWM clock speed as shown in

Table 9 of the “LED Backlight/Boost Operation” section.

Bit B7 sets the slew rate of the LED boost SW pin. Setting

B7 to 0 results in the fastest slew rate and provides the

most efﬁ cient mode of operation. Setting B7 to 1 should

only be used in cases where EMI due to SW slewing is an

issue as the slower slew rate causes a loss in efﬁ ciency.

See the “LED Backlight/Boost Operation” section for more

detailed operating information.

Table 10 shows the third byte of data that can be written

to at sub-address 0x02. This byte of data is referred to as

the “LED DAC register.” The LED current source utilizes a

6-bit 60dB exponential DAC. This DAC provides accurate

current control from 20A to 20mA with approximately

1dB per step with ILED(FS) programmed to 20mA. The LED

current can be approximated by the following equation:

ILED =ILED(FS) •10

3 • DAC – 63

⎛

⎝

⎜⎞

⎠

⎟

where DAC is the decimal value programmed into the I2C

“LED DAC register.” For example with ILED(FS) = 20mA and

DAC[5:0] = 101010 (42 decimal) ILED equates to 2mA.

Table 10. I2C LED DAC Register

LED DAC REGISTER

ADDRESS: 00010010

SUB-ADDRESS: 00000010

BIT NAME FUNCTION

B0 DAC[0] 6-Bit Log DAC Code

B1 DAC[1]

B2 DAC[2]

B3 DAC[3]

B4 DAC[4]

B5 DAC[5]

B6 N/A Not Used—No Effect On Operation

B7 N/A Not Used—No Effect On Operation

LTC3577/LTC3577-1

3577fa

OPERATION

Table 11 shows the ﬁ nal byte of data that can be written

to at sub-address 0x03. This byte of data is referred to as

the “LED PWM register”. See the “LED PWM vs Constant

Current Operation” section for detailed information on

how to set the values of this register.

Table 11. LED PWM Register

LED PWM REGISTER

ADDRESS: 00010010

SUB-ADDRESS: 00000011

BIT NAME FUNCTION

B0 PWMDEN[0] PWM DENOMINATOR

B1 PWMDEN[1]

B2 PWMDEN[2]

B3 PWMDEN[3]

B4 PWMNUM[0] PWM NUMERATOR

B5 PWMNUM[1]

B6 PWMNUM[2]

B7 PWMNUM[3]

I2C Output Data

One status byte may be read from the LTC3577. Table 12

represents the status byte information. A 1 read back in

the any of the bit positions indicates that the condition is

true. For example, 1 read back from bit A3 indicate that

LDO1 is enabled and regulating correctly. A status read

from the LTC3577 captures the status information when

the LTC3577 acknowledges its read address.

Table 12. I2C READ Register

STATUS REGISTER

ADDRESS: 00010011

SUB-ADDRESS: None

BIT NAME FUNCTION

A0 CHARGE Charge Status (1 = Charging)

A1 STAT[0] STAT[1:0]; 00 = No Fault

01 = TOO COLD/HOT

10 = BATTERY OVERTEMP

11 = BATTERY FAULT

A2 STAT[1]

A3 PGLDO[1] LDO1 Power Good

A4 PGLDO[2] LDO2 Power Good

A5 PGBCK[1] Buck1 Power Good

A6 PGBCK[2] Buck2 Power Good

A7 PGBCK[3] Buck3 Power Good

Bit A7 shows the power good status of buck3. A 1 indicates

that buck3 is enabled and is regulating correctly. A 0 indi-

cates that either buck3 is not enabled, or that the buck3 is

enabled, but is out of regulation by more than 8%.

Bit A6 shows the power good status of buck2. A 1 indicates

that buck2 is enabled and is regulating correctly. A 0 indi-

cates that either buck2 is not enabled, or that the buck2 is

enabled, but is out of regulation by more than 8%.

Bit A5 shows the power good status of buck1. A 1 indicates

that buck1 is enabled and is regulating correctly. A 0 indi-

cates that either buck1 is not enabled, or that the buck1 is

enabled, but is out of regulation by more than 8%.

Bit A4 shows the power good status of LDO2. A 1 indicates

that LDO2 is enabled and is regulating correctly. A 0 indi-

cates that either LDO2 is not enabled, or that the LDO2 is

enabled, but is out of regulation by more than 8%.

Bit A3 shows the power good status of LDO1. A 1 indicates

that LDO1 is enabled and is regulating correctly. A 0 indi-

cates that either LDO1 is not enabled, or that the LDO1 is

enabled, but is out of regulation by more than 8%.

Bits A2 and A1 indicate the fault status of the charger

circuit and are decoded in Table 12. The “too cold/hot”

state indicates that the thermistor temperature is out of

the valid charging range (either below 0°C or above 40°C

for a curve 1 thermistor) and that charging has paused

until a return to valid temperature. The battery overtemp

state indicates that the battery’s thermistor has reached

a critical temperature (above 50°C for a curve 1 thermis-

tor) and that long-term battery capacity may be seriously

compromised if the condition persists. The battery fault

state indicates that an attempt was made to charge a

low battery (typically < 2.85V) but that the low voltage

condition persisted for more than 1/2 hour. In this case

charging has terminated.

Bit A0 indicates the status of the battery charger. A 1 in-

dicates that the charger is enabled and is in the constant

current charge state. In this case the battery is being

charged unless the NTC thermistor is outside its valid

charge range in which case charging is temporarily sus-

pended but not complete. Charging will continue once the

LTC3577/LTC3577-1

3577fa

OPERATION

battery has returned to a valid charging temperature. A 0

in bit A0 indicates that charging has entered the end-of-

charge state (hC/10) and is near VFLOAT or that charging

has been terminated. Charging can be terminated by

reaching the end of the charge timer or by a battery fault

as described previously.

I2C WRITE REGISTER MAP (see the “I2C Input Data” section

for more details, all registers default to 0 when reset)

LDO and BUCK CONTOL

ADDRESS: 00010010

SUB-ADDRESS: 00000000

BIT NAME FUNCTION

B0 LDO1EN Enable LDO 1

B1 LDO2EN Enable LDO 2

B2 BK1BRST Buck1 Burst Mode Enable

B3 BK2BRST Buck2 Burst Mode Enable

B4 BK3BRST Buck2 Burst Mode Enable

B5 SLEWCTL1 Buck SW Slew Rate: 00 = 1ns,

01 = 2ns, 10 = 4ns, 11 = 8ns

B6 SLEWCTL2

B7 N/A Not Used—No Effect On Operation

LED CONTROL

ADDRESS: 00010010

SUB-ADDRESS: 00000001

BIT NAME FUNCTION

B0 EN Enable: 1= Enable 0 = Off

B1 GR2 Gradation GR[2:1]: 00 = 15ms, 01 = 460ms,

10 = 930ms, 11 = 1.85 Seconds

B2 GR1

B3 MD1 Mode MD[2:1]: 00 = CC Boost,

10 = PWM Boost, 01 = HV Boost

B4 MD2

B5 PWMC1 PWM CLK PWMC[2:1]: 00 = 8.77kHz,

01 = 4.39kHz, 10 = 2.92kHz, 11 = 2.19kHz

B6 PWMC2

B7 SLEWLED LED SW Slew rate: 0/1 = Fast/Slow

LED DAC REGISTER

ADDRESS: 00010010

SUB-ADDRESS: 00000010

BIT NAME FUNCTION

B0 DAC[0] 6-Bit Log DAC Code

B1 DAC[1]

B2 DAC[2]

B3 DAC[3]

B4 DAC[4]

B5 DAC[5]

B6 N/A Not Used—No Effect On 0peration

B7 N/A Not Used—No Effect On 0peration

LED PWM REGISTER

ADDRESS: 00010010

SUB-ADDRESS: 00000011

BIT

NAME FUNCTION

PWMDEN[0] PWM Denominator

PWMDEN[1]

PWMDEN[2]

PWMDEN[3]

PWMNUM[0] PWM Numerator

PWMNUM[1]

PWMNUM[2]

PWMNUM[3]

PUSHBUTTON INTERFACE OPERATION

State Diagram/Operation

Figure 18 shows the LTC3577 pushbutton state diagram.

Upon ﬁ rst application of power (VBUS, WALL or BAT) an

internal power-on reset (POR) signal places the pushbutton

circuitry into the power-down (PDN1) state. One second

after entering the PDN1 state the pushbutton circuitry will

transition into the hard reset (HR) state. The following

events cause the state machine to transition out of HR

into the power-up (PUP1) state:

1) ON input low for 400ms (PB400MS)

2) Application of external power (EXTPWR)

3) PWR_ON input going high (PWR_ON)

PDN2 HRST

PWR_ON

+UVLO HRST

HRST

1SEC

POR

PDN1

PONPOFF

PUP1

5SEC

PB400MS +

EXTPWR +

PWR_ON

PB400MS +

EXTPWR +

PWR_ON

PUP2

5SEC

Figure 18. Pushbutton State Diagram

LTC3577/LTC3577-1

3577fa

OPERATION

Upon entering the PUP1 state, the pushbutton circuitry

will sequence up the three step-down switching regula-

tors in numerical order. LDO1, LDO2 and LED backlight

are enabled via I2C and do not take part in the power-up

sequence of the pushbutton. Five seconds after entering

the PUP1 state, the pushbutton circuitry will transition into

the power-on (PON) state. Note that the PWR_ON input

must be brought high before entering the PON state if the

part is to remain in the PON state.

PWR_ON going low, or VOUT dropping to its undervoltage

lockout (VOUT UVLO) threshold will cause the state machine

to leave the PON state and enter the power-down (PDN2)

state. The PDN1 and PDN2 states reset the I2C registers

effectively shutting down the LDOs and LED backlight as

well as disable all switching regulators together. The one

second delay before leaving either power-down state allows

all LTC3577 generated supplies to power down completely

before they can be re-enabled.

The same three events used to exit HR are also used to

exit the POFF state and enter PUP2 state. The PUP2 state

operates in the same manner as the PUP1 state previously

described.

The hard reset (HRST) event is generated by pressing and

holding the pushbutton (ON input low) for 5 seconds. For

a valid HRST event to occur the initial pushbutton applica-

tion must start in the PUP1, PUP2 or PON state, but can

end in any state. If a valid HRST event is present in PON,

PDN2 or POFF, then the state machine will transition to the

PDN1 state and subsequently transition to the HR state

one second later.

In the HR state all supplies are disabled and the Power-

Path circuitry is placed in an ultralow quiescent state to

minimize battery drain. If no external charging supply

is present (WALL or VBUS) then the ideal diode is shut

down disconnecting VOUT from BAT. The ultralow power

consumption in the HR state makes it ideal for shipping

or long term storage, minimizing battery drain. In the HR

state the battery monitoring circuit wakes up the charger

every 150ms to sample the NTC thermistor for overtem-

perature battery condition. To sample the NTC thermistor,

the ideal diode is turned on charging VOUT up to VBAT.

As a consequence, any system load on VOUT will show up

as a load on VBAT. Figure 26 shows an optional circuit to

disconnect the system load from VOUT.

Power-Up via Pushbutton Timing

The timing diagram, Figure 19, shows the LTC3577 power-

ing up through application of the external pushbutton. For

this example the pushbutton circuitry starts in the POFF or

HR state with a battery connected and all buck disabled.

Pushbutton application (ON low) for 400ms transitions

the pushbutton circuitry into the PUP state which brings

WAKE Hi-Z for 5 seconds. WAKE going Hi-Z sequences

buck1-3 up in numerical order. WAKE will stay Hi-Z if

PWR_ON is driven high before the 5 seconds PUP period

is over. If PWR_ON is low or goes low after the 5 second

period, WAKE will go low and buck1-3 will be shut down

together. PG_DCDC is asserted once all enabled bucks are

within 8% of their regulation voltage for 230ms.

PBSTAT does not go low impedance with ON going low

during the power-up pushbutton application. PBSTAT will

go low impedance with ON on subsequent pushbutton

applications once in the PUP1, PUP2 or PON states.

The LDOs and LED backlight can be enabled and disabled

at any time via I2C once in the PUP1, PUP2 or PON states.

The PWR_ON input can be driven via a P/C or by one of

the buck outputs through a high impedance (100kΩ typ)

to keep the bucks enabled as described above.

BAT

PBSTAT

WAKE

400ms

230ms

1 2 3

BUCKS SEQUENCE UP

BUCK1-3

PG_DCDC

PWR_ON

STATE POFF/HR PUP2/PUP1 PON

3755 F19

VBUS

ON (PB)

5SEC

Figure 19. Power-Up via Pushbutton Timing

LTC3577/LTC3577-1

3577fa

OPERATION

Power-Up via External Power Timing

The timing diagram, Figure 20, shows the LTC3577 power-

ing up through application of the external power (VBUS or

WALL). For this example the pushbutton circuitry starts

in the POFF or HR state with a battery connected and all

buck disabled. 100ms after WALL or VBUS application the

WAKE output goes Hi-Z for 5 seconds. The 100ms delay

time allows the applied supply to settle. WAKE going

Hi-Z sequences buck1-3 up in numerical order. WAKE

will stay Hi-Z if the PWR_ON input is driven high before

the 5 seconds PUP period is over. If PWR_ON is low or

goes low after the 5 second period, WAKE will go low and

buck1-3 will be shut down together. PG_DCDC is asserted

once all enabled bucks are within 8% of their regulation

voltage for 230ms.

The LDOs and LED backlight can be enabled and disabled

via I2C any time after entering the PUP1, PUP2 or PON

state. The PWR_ON input can be driven via a P/C or one

of the buck outputs through a high impedance (100kΩ

typ) to keep the bucks enabled as described above.

Without a battery present initial power application causes

a power on reset which puts the pushbutton circuitry in

the PDN2 state and subsequently the HR state 1 second

later. In this case the pushbutton must be applied to enter

the PUP1 state after initial power application.

Power-Up via PWR_ON Timing

The timing diagram, Figure 21, shows the LTC3577

powering up by driving PWR_ON high. For this example

the pushbutton circuitry starts in the POFF or HR state

with a battery connected and all bucks disabled. 50ms

after PWR_ON goes high the WAKE output goes Hi-Z for

5 seconds. WAKE going Hi-Z sequences buck1-3 up in

numerical order. WAKE will stay Hi-Z as long as PWR_ON

is high at the end of the 5 second PUP period. If PWR_ON

is low or goes low after the 5 second period, WAKE will

go low and buck1-3 will be shut down together. PG_DCDC

is asserted once all enabled bucks are within 8% of their

regulation voltage for 230ms.

The LDOs and LED backlight can be enabled and disabled

via I2C any time after entering the PUP1, PUP2 or PON

state.

Powering up via PWR_ON is useful for applications

containing an always on C. This allows the C to power

the application up and down for house keeping and other

activities outside the user’s control.

BAT

PBSTAT

WAKE

100ms

230ms

1 2 3

BUCKS SEQUENCE UP

BUCK1-3

PG_DCDC

PWR_ON

STATE POFF/HR PUP2/PUP1 PON

3755 F20

VBUS

ON (PB)

5SEC

Figure 20. Power-Up via External Power Timing

PBSTAT

PWR_ON

WAKE

BUCK1-3

PG_DCDC

STATE POFF/HR PUP2/PUP1 PON

BAT

ON (PB)

230ms

3577 F21

1 2 3

BUCKS SEQUENCE UP

5Oms

5SEC

Figure 21. Power-Up via PWR_ON Timing

LTC3577/LTC3577-1

3577fa

OPERATION

Power-Down via Pushbutton Timing

The timing diagram, Figure 22, shows the LTC3577

powering down by C/P control. For this example the

pushbutton circuitry starts in the PON state with a bat-

tery connected and all bucks enabled. In this case the

pushbutton is applied (ON low) for at least 50ms, which

generates a low impedance on the PBSTAT output. After

receiving the PBSTAT the C/P will drive the PWR_ON

input low. 50ms after PWR_ON goes low the WAKE

output will go low and the pushbutton circuitry will enter

the PDN2 state. The bucks are disabled together at once

upon entering the PDN2 state. Once entering the PDN2

state a 1 second wait time is initiated before entering the

POFF state. During this 1 second time ON and PWR_ON

inputs as well as external power application are ignored

to allow all LTC3577 generated supplies to go low. Though

the above assumes a battery present, the same operation

would take place with a valid external supply (VBUS or

WALL) with or without a battery present.

Upon entering the PDN2 state the LDOs and LED backlight

I2C registers are cleared effectively disabling both. If this

is not desirable the LDOs and LED backlight should be

disabled via I2C prior to entering the PDN2 state.

Holding ON low through the 1 second power-down period

will not cause a power-up event at end of the 1 second

period. The ON input must be brought high following the

power-down event and then go low again to establish a

valid power-up event.

UVLO Minimum Off-Time Timing (Low Battery)

The timing diagram, Figure 23, assumes the battery is either

missing or at a voltage below the VOUT UVLO threshold

and the application is running via external power (VBUS

or WALL). A glitch on the external supply causes VOUT

to drop below the VOUT UVLO threshold temporarily. The

VOUT UVLO condition will cause the pushbutton circuitry

to transition from the PON state to the PDN2 state. Upon

entering the PDN2 state WAKE and PG_DCDC will go low

while the bucks, LDOs and LED backlight power down

together. If the external supply recovers after entering the

PND2 state such that VOUT is no longer in UVLO then the

LTC3577 will transition back into the PUP2 state once the

PDN2 one second delay is complete. Though not shown

in Figure 23, the pushbutton logic brieﬂ y visits the POFF

state when transitioning between PDN2 and PUP2. Enter-

ing the PUP2 state will cause the bucks to sequence up as

described previously in the power-up sections. The LDOs

and LED backlight must be re-enabled via I2C once device

is powered back up.

PBSTAT

PWR_ON

WAKE

BUCKS

PG_DCDC

STATE PON PDN2 PUP2 PON

VBUS/WALL

BAT

ON (PB)

3577 F23

1SEC

BUCKS SEQUENCE UP

1 2 3

230ms

5SEC

Figure 23. UVLO Minimum Off-Time

Figure 22. Power-Down via Pushbutton Timing

PBSTAT

PWR_ON

WAKE

BUCK1-3

PG_DCDC

STATE PON PDN2 POFF

VBUS/WALL

BAT

ON (PB)

3577 F22

1SEC

50ms

µC/µP CONTROL

50ms

ALL BUCKS LOW

LTC3577/LTC3577-1

3577fa

OPERATION

Hard Reset Timing

Hard reset provides an ultralow power-down state for

shipping or long-term storage as well as a way to power

down the application in case of a software lock-up. In the

case of software lock-up ON is brought low by the user

applying the pushbutton. If the user holds the pushbutton

for 5 seconds a hard reset event (HRST) will occur placing

the pushbutton circuitry in the PDN1 state. At this point

the bucks, LDOs and LED backlight will all be shut down

and WAKE and PG_DCDC will both go low. Following a 1

second power-down period the pushbutton circuitry will

enter the hard reset state (HR).

Holding ON low through the 1 second power-down period

will not cause a power-up event at end of the 1second period.

The ON must be brought high following the power-down

event and then go low for again for 400ms to establish a

valid power-up event as shown in Figure 24.

Power-Up Sequencing

Figure 25 shows the actual power-up sequencing of the

LTC3577. Buck1, buck2 and buck3 are all initially disabled

(0V). Once the pushbutton has been applied (ON low) for

400ms, WAKE goes high and buck1 is enabled. Buck1

slews up and enters regulation once enabled. The actual

slew rate is controlled by the soft-start function of buck1

in conjunction with output capacitance and load (see the

“Step-Down Switching Regulator Operation” section for

more information). When buck1 is within about 8% of ﬁ nal

regulation, buck2 is enabled and slews up into regulation.

Finally when buck2 is within about 8% of ﬁ nal regulation,

buck3 is enabled and slews up into regulation. 230ms

after buck3 is within 8% of ﬁ nal regulation the PG_DCDC

output will go high impedance (not shown in Figure 25).

The regulators in Figure 25 are slewing up with nominal

output capacitors and no load. Adding a load or increasing

output capacitance on any of the outputs will reduce the

slew rate and lengthen the time it takes the regulator to get

into regulation. Reducing the slew rate also pushes out the

time until the next regulator is enabled proportionally.

PBSTAT

WAKE

BUCKS

PWR_ON

PG_DCDC

STATE PON HR

1SEC

PDN1 PUP

BAT

ON (PB)

3577 F24

1 2 3

400ms

5SEC

Figure 24. Hard Reset Timing

50µs/DIV 3577 F23

WAKE

BUCK1

2V/DIV

BUCK2

1V/DIV

BUCK3

1V/DIV

Figure 25. Power-Up Sequencing

LTC3577/LTC3577-1

3577fa

OPERATION

LAYOUT AND THERMAL CONSIDERATIONS

Printed Circuit Board Power Dissipation

In order to be able to deliver maximum charge current

under all conditions, it is critical that the exposed ground

pad on the backside of the LTC3577 package is soldered

to a ground plane on the board. Correctly soldered to

2500mm2 ground plane on a double-sided 1oz. copper

board the LTC3577 has a thermal resistance (θJA) of ap-

proximately 45°C/W. Failure to make good thermal contact

between the Exposed Pad on the backside of the package

and a adequately sized ground plane will result in thermal

resistances far greater than 45°C/W.

The conditions that cause the LTC3577 to reduce charge

current due to the thermal protection feedback can be

approximated by considering the power dissipated in the

part. For high charge currents with a wall adapter applied to

VOUT, the LTC3577 power dissipation is approximately:

D = (VOUT – BAT) • IBAT + PDREGS

where, PD is the total power dissipated, VOUT is the sys-

tem supply voltage, BAT is the battery voltage, and IBAT

is the battery charge current. PDREGS is the sum of power

dissipated on-chip by the step-down switching, LDO and

LED boost regulators.

The power dissipated by a step-down switching regulator

can be estimated as follows:

PD(SWx) =BOUTx •IOUT

()

•100 –Eff

100

where BOUTx is the programmed output voltage, IOUT

is the load current and Eff is the % efﬁ ciency which can

be measured or looked up on an efﬁ ciency table for the

programmed output voltage.

The power dissipated on chip by a LDO regulator can be

estimated as follows:

DLDOx = (VINLDOx – LOUTx) • IOUT

where LOUTx is the programmed output voltage, VINLDOx

is the LDO supply voltage and IOUT is the LDO output load

current. Note that if the LDO supply is connected to one

of the buck output, then its supply current must be added

to the buck regulator load current for calculating the buck

power loss.

The power dissipated by the LED boost regulator can be

estimated as follows:

PDLED =ILED • 0.3V +RNSWON •I

LED •BOOST

VOUT –1

⎛

⎝

⎜⎞

⎠

⎟

where BOOST is the output voltage driving the top of

the LED string, RNSWON is the on-resistance of the SW

N-FET (typically 330mΩ), ILED is the LED programmed

current sink.

Thus the power dissipated by all regulators is:

PDREGS = PDSW1 + PDSW2 + PDSW3 + PDLDO1 + PDLDO2 + PDLED

It is not necessary to perform any worst-case power dis-

sipation scenarios because the LTC3577 will automatically

reduce the charge current to maintain the die temperature

at approximately 110°C. However, the approximate ambi-

ent temperature at which the thermal feedback begins to

protect the IC is:

A = 110°C – PD • θJA

Example: Consider the LTC3577 operating from a wall

adapter with 5V (VOUT) providing 1A (IBAT) to charge a

Li-Ion battery at 3.3V (BAT). Also assume PDREGS = 0.3W,

so the total power dissipation is:

D = (5V – 3.3V) • 1A + 0.3W = 2W

The ambient temperature above which the LTC3577 will

begin to reduce the 1A charge current, is approximately

A = 110°C – 2W • 45°C/W = 20°C

LTC3577/LTC3577-1

3577fa

OPERATION

The LTC3557 can be used above 20°C, but the charge

current will be reduced below 1A. The charge current at

a given ambient temperature can be approximated by:

PD=110°C–T

θJA

=VOUT – BAT

()

•IBAT +PD(REGS)

Thus:

IBAT =

(110°C−TA)

θJA

−PDREGS

VOUT – BAT

Consider the above example with an ambient temperature

of 55°C. The charge current will be reduced to approxi-

mately:

IBAT =

110°C–55°C

45°C/W −0.3W

5V – 3.3V

IBAT =1.22W – 0.3W

1.7V =542mA

If an external buck switching regulator controlled by the

LTC3577 VC pin is used instead of a 5V wall adapter we see

a signiﬁ cant reduction in power dissipated by the LTC3577.

This is because the external buck switching regulator will

drive the PowerPath output (VOUT) to about 3.6V with the

battery at 3.3V. If you go through the example above and

substitute 3.6V for VOUT we see that thermal regulation

does not kick in until about 83°C. Thus, the external high

voltage buck regulator not only allows higher charging

currents, but lower power dissipation means a cooler

running application.

Printed Circuit Board Layout

When laying out the printed circuit board, the following

list should be followed to ensure proper operation of the

LTC3577:

1. The Exposed Pad of the package (Pin 45) should connect

directly to a large ground plane to minimize thermal and

electrical impedance.

2. The step-down switching regulator input supply pins

(VIN12 and VIN3) and their respective decoupling ca-

pacitors should be kept as short as possible. The GND

side of these capacitors should connect directly to the

ground plane of the part. These capacitors provide the

AC current to the internal power MOSFETs and their

drivers. It’s important to minimizing inductance from

these capacitors to the pins of the LTC3577. Connect

VIN12 and VIN3 to VOUT through a short low impedance

trace.

3. The switching power traces connecting SW1, SW2, and

SW3 to their respective inductors should be minimized

to reduce radiated EMI and parasitic coupling. Due to

the large voltage swing of the switching nodes, sensitive

nodes such as the feedback nodes (FBx, LDOx_FB and

LED_OV) should be kept far away or shielded from the

switching nodes or poor performance could result.

4. Connections between the step-down switching regu-

lator inductors and their respective output capacitors

should be kept as short as possible. The GND side of

the output capacitors should connect directly to the

thermal ground plane of the part.

5. Keep the buck feedback pin traces (FB1, FB2, and FB3)

as short as possible. Minimize any parasitic capacitance

between the feedback traces and any switching node

(i.e. SW1, SW2, SW3, and logic signals). If necessary

shield the feedback nodes with a GND trace.

6. Connections between the LTC3577 PowerPath pins

(VBUS and VOUT) and their respective decoupling ca-

pacitors should be kept as short as possible. The GND

side of these capacitors should connect directly to the

ground plane of the part.

7. The boost converter switching power trace connect-

ing SW to the inductor should be minimized to reduce

radiated EMI and parasitic coupling. Due to the large

voltage swing of the SW node, sensitive nodes such

as the feedback nodes (FBx, LDOx_FB and LED_OV)

should be kept far away or shielded from this switching

node or poor performance could result.

LTC3577/LTC3577-1

3577fa

TYPICAL APPLICATIONS

WALL

Si2306BDSSi2333DS

5V WALL

ADAPTER

ACPRVC

OVGATE VINLDO2

42 4 41

VOUT 39

10µF

OVSENSE

VBUS

CLPROG

PROG

LDO1

LDO1_FB

LDO2

LDO2_FB

USB

DVCC

SDA

SCL

499k

WAKE

PBSTAT

PWR_ON

ILIM0

ILIM1

10µF

6.2k

OPTIONAL OVERVOLTAGE/

REVERSE VOLTAGE PROTECTION

LTC3577

GND

VIN3 6

2.2µF

VIN12

CHRG 37

IDGATE

BAT

SW 18,19,20

NTCBIAS 34

NTC 35

2.2µF

100k BAT

20µF

1µF

50V

VOUT1

3.3V

500mA

100k

Li-Ion

10µH

ZLLS400

6-LED BACKLIGHT

100k

NTC

Si2333DS

VOUT

SYSTEM

LOAD

Si2333DS

(OPT)

Si2306BDS

OPTIONAL SYSTEM

LOAD DISCONNECT

Si2333DS

499k

LED_OV 9

ILED 22

324k

LED_FS 3

PG_DCDC 21

SW1 33

FB1 26

VINLDO1 23

4.7µH

20k

2.1k

1.02M10pF 10µF

VOUT2

1.8V

500mA

649k

SW2 31

FB2 25

4.7µH

806k10pF 10µF1µF

1µF

VOUT3

1.2V

800mA

464k

470k

464k

PUSHBUTTON

SW3 5

FB3 7

3.3µH

232k10pF

232k

1.00M

VLDO2

2.5V

150mA

VLDO1

1.2V

75mA

10µF

3577 TA02

499k

DVCC

SDA

SCL

WAKE

PBSTAT

PWR_ON

ILIM0

ILIM1

µC/µP

RST

22nF

Figure 26. USB Plus 5V Adapter Input Charger, Multichannel Power Supply and PowerPath Controller

LTC3577/LTC3577-1

3577fa

TYPICAL APPLICATIONS

Figure 27. USB Plus HV Input Charger, Multichannel Power Supply and PowerPath Controller

WALL

Si2306BDS

ACPR

OVGATE

VINLDO2

441

VOUT 39

10µF

OVSENSE

VBUS

CLPROG

PROG

LDO1

LDO1_FB

LDO2

LDO2_FB

USB

DVCC

SDA

SCL

499k

WAKE

PBSTAT

PWR_ON

ILIM0

ILIM1

10µF

6.2k

OPTIONAL

OVERVOLTAGE

PROTECTION

LTC3577

GND

VIN3 6

2.2µF

VIN12

CHRG 37

IDGATE

BAT

SW 18,19,20

NTCBIAS 34

NTC 35

2.2µF

100k BAT

20µF

1µF

50V

VOUT1

3.3V

500mA

100k

Li-Ion

10µH

ZLLS400

10-LED BACKLIGHT

100k

NTC

Si2333DS

VOUT

SYSTEM

LOAD

Si2333DS

(OPT)

DFLS240L

6.8µH

499k

22µF

0.47µF

100k

OPTIONAL HIGH VOLTAGE

BUCK INPUT

150k

68nF

40.2k

LED_OV 9

ILED 22

10M

324k

LED_FS 3

PG_DCDC 21

SW1 33

FB1 26

VINLDO1 23

4.7µH

20k

2.1k

1.02M10pF 10µF

VOUT2

1.8V

500mA

649k

SW2 31

FB2 25

4.7µH

806k10pF 10µF1µF

1µF

VOUT3

1.2V

800mA

464k

470k

464k

PUSHBUTTON

SW3 5

FB3 7

3.3µH

232k10pF

232k

1.00M

VLDO2

2.5V

150mA

VLDO1

1.2V

75mA

10µF

3577 TA03

499k

DVCC

SDA

SCL

WAKE

PBSTAT

PWR_ON

ILIM0

ILIM1

µC/µP

RST

GND

PGNC FB

SYNC

10 RT

RUN/SS

VIN

BOOST

LT3480

4.7µF

HVIN

8V TO 38V

(TRANSIENTS

TO 60V)

22nF

LTC3577/LTC3577-1

3577fa

4.00 p0.10

5.60 REF

6.10 ±0.05

2.56 ±0.05

2.64 ±0.05

1.70 ±0.05

7.50 ±0.05

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

PIN 1

TOP MARK

(SEE NOTE 6)

BOTTOM VIEW—EXPOSED PAD

2.40 REF

3.10 ±0.05

4.50 ±0.05

7.00 p0.10 5.60 REF

0.75 p0.05

0.20 p0.05

(UFF44MA) QFN REF Ø 1107

0.40 BSC

0.98 ±0.10

0.200 REF

0.00 – 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

2.40 REF

2.64

±0.10

0.40 p0.10

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 NOTCH

R = 0.30 TYP

OR 0.35 s 45o

CHAMFER

2.56

±0.10

1.70

±0.10 2.76

±0.10

0.74 ±0.10

R = 0.10 TYP

R = 0.10

TYP

0.74 ±0.10

0.40 BSC

PACKAGE

OUTLINE

0.20 ±0.05

2.02 ±0.05

2.76 ±0.05 0.98 ±0.05

1.48 ±0.05

0.70 ±0.05

PACKAGE DESCRIPTION

UFF Package

Variation: UFFMA

44-Lead Plastic QFN (4mm × 7mm)

(Reference LTC DWG # 05-08-1762 Rev Ø)

LTC3577/LTC3577-1

3577fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A Nov 09 Changes to Features

Change to Absolute Maximum Ratings

Add Note 16

Text Changes to Pin Functions

Changes to Operation Section

Changes to Typical Application Circuits

50, 51

LTC3577/LTC3577-1

3577fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 1209 REV A • PRINTED IN USA

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Hot Swap is a trademark of Linear Technology Corporation.