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FEATURES
DESCRIPTION
NC − No internal connection
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND/HSINK
GND/HSINK
GND
NC
EN
IN
IN
NC
GND/HSINK
GND/HSINK
GND/HSINK
GND/HSINK
NC
NC
PG
FB/NC
OUT
OUT
GND/HSINK
GND/HSINK
PWP PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
GND
EN
IN
IN
PG
FB/NC
OUT
OUT
D PACKAGE
(TOP VIEW)
TA - Free-Air Temperature - °C
-40 0 20 120
103
-60 40 60 80 100
- Dropout Voltage - mV
VDO
TPS76833
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
102
101
100
10-1
10-2 -20 140
IO = 1 A
IO = 10 mA
IO = 0
Co = 10 µF
t - Time - µs
LOAD TRANSIENT RESPONSE
I - Output Current - A
OVO- Change in∆
Output Voltage - mV
1
0.5
300200100 400 500 700600 800 900 10000
Co = 10 µF
TA = 25°C
0
0
50
100
-50
-100
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS
•1 A Low-Dropout Voltage Regulator•Available in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V,3.0-V, 3.3-V, 5.0-V Fixed Output and Adjust-able Versions•Dropout Voltage Down to 230 mV at 1 A(TPS76850)
•Ultralow 85 µA Typical Quiescent Current•Fast Transient Response•2% Tolerance Over Specified Conditions forFixed-Output Versions•Open Drain Power Good (See TPS767xx forPower-On Reset With 200-ms Delay Option)•8-Pin SOIC and 20-Pin TSSOP (PWP) Package•Thermal Shutdown Protection
This device is designed to have a fast transientresponse and be stable with 10µF low ESR capaci-tors. This combination provides high performance at areasonable cost.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION (CONTINUED)
†See application information section for capacitor selection details.
PG
OUT
OUT
7
6
5
IN
IN
EN
GND
3
16
14
13
VI
0.1 µF
PG
VO
10 µF
+
TPS768xx
Co†
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 230 mV atan output current of 1 A for the TPS76850) and is directly proportional to the output current. Additionally, sincethe PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of outputloading (typically 85 µA over the full range of output current, 0 mA to 1 A). These two key specifications yield asignificant improvement in operating life for battery-powered systems. This LDO family also features a sleepmode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to lessthan 1 µA at T
J
= 25°C.
Power good (PG) is an active high output, which can be used to implement a power-on reset or a low-batteryindicator.
The TPS768xx is offered in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, and 5.0-V fixed-voltage versions andin an adjustable version (programmable over the range of 1.2 V to 5.5 V). Output voltage tolerance is specifiedas a maximum of 2% over line, load, and temperature ranges. The TPS768xx family is available in 8-pin SOICand 20-pin PWP packages.
AVAILABLE OPTIONS
OUTPUT VOLTAGE (V) PACKAGED DEVICES
(1)T
J
TYP TSSOP (PWP) SOIC (D)
5.0 TPS76850Q TPS76850Q3.3 TPS76833Q TPS76833Q3.0 TPS76830Q TPS76830Q2.8 TPS76828Q TPS76828Q40°C to 125°C 2.7 TPS76827Q TPS76827Q2.5 TPS76825Q TPS76825Q1.8 TPS76818Q TPS76818Q1.5 TPS76815Q TPS76815QAdjustable 1.2 V to 5.5 V TPS76801Q TPS76801Q
(1) The TPS76801 is programmable using an external resistor divider (see application information). The D and PWP packages are availabletaped and reeled. Add an R suffix to the device type (e.g., TPS76801QDR).
Figure 1. Typical Application Configuration (For Fixed Output Options)
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_
+
Vref = 1.1834 V
OUT
FB/NC
EN
GND
PG
_
+
IN
External to the device
R1
R2
_
+
Vref = 1.1834 V
OUT
EN
GND
R1
R2
_
+
IN
PG
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
FUNCTIONAL BLOCK DIAGRAM—Adjustable Version
FUNCTIONAL BLOCK DIAGRAM—Fixed-Voltage Version
3
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TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME NO.
SOIC PACKAGE
GND 1 Regulator groundEN 2 I Enable inputIN 3 I Input voltageIN 4 I Input voltageOUT 5 O Regulated output voltageOUT 6 O Regulated output voltageFB/NC 7 I Feedback input voltage for adjustable device (no connect for fixed options)PG 8 O PG output
PWP PACKAGE
GND/HSINK 1 Ground/heatsinkGND/HSINK 2 Ground/heatsinkGND 3 LDO groundNC 4 No connectEN 5 I Enable inputIN 6 I InputIN 7 I InputNC 8 No connectGND/HSINK 9 Ground/heatsinkGND/HSINK 10 Ground/heatsinkGND/HSINK 11 Ground/heatsinkGND/HSINK 12 Ground/heatsinkOut 13 O Regulated output voltageOut 14 O Regulated output voltageFB/NC 15 I Feedback input voltage for adjustable device (no connect for fixed options)PG 16 O PG outputNC 17 No connectNC 18 No connectGND/HSINK 19 Ground/heatsinkGND/HSINK 20 Ground/heatsink
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE 1 - FREE-AIR TEMPERATURES
DISSIPATION RATING TABLE 2 - FREE-AIR TEMPERATURES
RECOMMENDED OPERATING CONDITIONS
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates
over operating free-air temperature range (unless otherwise noted)
(1)
Input voltage range, V
I
(2)
-0.3 V to 13.5 VVoltage range at EN -0.3 V to V
I
+ 0.3 VMaximum PG voltage 16.5 VPeak output current Internally limitedContinuous total power dissipation See dissipation rating tablesOutput voltage, V
O
(OUT, FB) 7 VOperating junction temperature range, T
J
-40°C to 125°CStorage temperature range, T
stg
-65°C to 150°CESD rating, HBM 2 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network terminal ground.
T
A
< 25°C POWER DERATING FACTOR T
A
= 70°C POWER T
A
= 85°C POWERPACKAGE AIR FLOW (CFM)
RATING ABOVE T
A
= 25°C RATING RATING
0 568.18 mW 5.6818 mW/°C 312.5 mW 227.27 mWD
250 904.15 mW 9.0415 mW/°C 497.28 mW 361.66 mW
T
A
< 25°C POWER DERATING FACTOR T
A
= 70°C POWER T
A
= 85°C POWERPACKAGE AIR FLOW (CFM)
RATING ABOVE T
A
= 25°C RATING RATING
0 2.9 W 23.5 mW/°C 1.9 W 1.5 WPWP
(1)
300 4.3 W 34.6 mW/°C 2.8 W 2.2 W0 3 W 23.8 mW/°C 1.9 W 1.5 WPWP
(2)
300 7.2 W 57.9 mW/°C 4.6 W 3.8 W
(1) This parameter is measured with the recommended copper heat sink pattern on a 1-layer PCB, 5-in x 5-in PCB, 1 oz. copper, 2-in x 2-incoverage (4 in
2
).(2) This parameter is measured with the recommended copper heat sink pattern on an 8-layer PCB, 1.5-in x 2-in PCB, 1 oz. copper, withlayers 1, 2, 3, 4, 5, 7, and 8 at 5% coverage (0.9 in
2
) and layers 3 and 6 at 100% coverage (6 in
2
). For more information, refer to TItechnical brief SLMA002, available for download at www.ti.com.
MIN MAX UNIT
Input voltage, V
I
(1)
2.7 10 VOutput voltage range, V
O
1.2 5.5 VOutput current, I
O
(2)
0 1.0 AOperating junction temperature, T
J
(2)
40 125 °C
(1) To calculate the minimum input voltage for your maximum output current, use the following equation: V
I(min)
= V
O(max)
+ V
DO(max load)
.(2) Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that thedevice operate under conditions beyond those specified in this table for extended periods of time.
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(2) If V
O
≤1.8 V then V
Imax
= 10 V, V
Imin
= 2.7 V:
Line Reg. (mV) %VVOVImax 2.7 V
100 1000
If V
O
≥2.5 V then V
Imax
=
10 V, V
Imin
= V
O
+ 1 V:
Line Reg. (mV) %VVOVImax VO1 V
100 1000
ELECTRICAL CHARACTERISTICS
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
over recommended operating free-air temperature range, V
I
= V
O(typ)
+ 1 V, I
O
= 1 mA, EN = 0 V, C
o
= 10 µF (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
5.5 V ≥V
O
≥1.5 V, T
J
= 25°C V
OTPS76801
5.5 V ≥V
O
≥1.5 V, T
J
= -40°C to 125°C 0.98V
O
1.02V
O
T
J
= 25°C, 2.7 V < V
IN
< 10 V 1.5TPS76815
T
J
= -40°C to 125°C, 2.7 V < V
IN
< 10 V 1.470 1.530T
J
= 25°C, 2.8 V < V
IN
< 10 V 1.8TPS76818
T
J
= -40°C to 125°C, 2.8 V < V
IN
< 10 V 1.764 1.836T
J
= 25°C, 3.5 V < V
IN
< 10 V 2.5TPS76825
T
J
= -40°C to 125°C, 3.5 V < V
IN
< 10 V 2.450 2.550T
J
= 25°C, 3.7 V < V
IN
< 10 V 2.7Output voltage (10 µA to 1 A load)
(1)
TPS76827 VT
J
= -40°C to 125°C, 3.7 V < V
IN
< 10 V 2.646 2.754T
J
= 25°C, 3.8 V < V
IN
< 10 V 2.8TPS76828
T
J
= -40°C to 125°C, 3.8 V < V
IN
< 10 V 2.744 2.856T
J
= 25°C, 4 V < V
IN
< 10 V 3.0TPS76830
T
J
= -40°C to 125°C, 4 V < V
IN
< 10 V 2.940 3.060T
J
= 25°C, 4.3 V < V
IN
< 10 V 3.3TPS76833
T
J
= -40°C to 125°C, 4.3 V < V
IN
< 10 V 3.234 3.366T
J
= 25°C, 6 V < V
IN
< 10 V 5.0TPS76850
T
J
= -40°C to 125°C, 6 V < V
IN
< 10 V 4.900 5.10010 µA < I
O
< 1 A, T
J
= 25°C 85Quiescent current (GND current)EN = 0V
(1)
µAI
O
= 1 A, T
J
= -40°C to 125°C 125Output voltage line regulation (∆V
O
/V
O
)
(1) (2)
V
O
+ 1 V < V
I
≤10 V, T
J
= 25°C 0.01 %/VLoad regulation 3 mVBW = 200 Hz to 100 kHz, C
o
= 10 µF,Output noise voltage (TPS76818) 55 µVrmsI
C
= 1 A, T
J
= 25°COutput current limit V
O
= 0 V 1.2 1.7 2 AThermal shutdown junction temperature 150 °CEN = V
I
, T
J
= 25°C, 2.7 V < V
I
< 10 V 1 µAStandby current
EN = V
I
, T
J
= -40°C to 125°C, 2.7 V < V
I
< 10
10 µAVFB input current TPS76801 FB = 1.5 V 2 nAHigh level enable input voltage 1.7 VLow level enable input voltage 0.9 VPower supply ripple rejection
(1)
f = 1 KHz, C
o
= 10 µF, T
J
= 25°C 60 dBMinimum input voltage for valid PG I
O(PG)
= 300 µA 1.1 VTrip threshold voltage V
O
decreasing 92 98 %V
O
PG Hysteresis voltage Measured at V
O
0.5 %V
O
Output low voltage V
I
= 2.7 V, I
O(PG)
= 1 mA 0.15 .04 VLeakage current V
(PG)
= 5 V 1 µAEN = 0 V 1 0 1Input current (EN) µAEN = V
I
1 1
(1) Minimum IN operating voltage is 2.7 V or V
O(typ)
+ 1 V, whichever is greater. Maximum IN voltage 10 V.
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TABLE OF GRAPHS
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS (continued)over recommended operating free-air temperature range, V
I
= V
O(typ)
+ 1 V, I
O
= 1 mA, EN = 0 V, C
o
= 10 µF (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
O
= 1 A, T
J
= 25°C 500TPS76828
I
O
= 1 A, T
J
= -40°C to 125°C 825I
O
= 1 A, T
J
= 25°C 450TPS76830
I
O
= 1 A, T
J
= -40°C to 125°C 675Dropout voltage
(3)
mVI
O
= 1 A, T
J
= 25°C 350TPS76833
I
O
= 1 A, T
J
= -40°C to 125°C 575I
O
= 1 A, T
J
= 25°C 230TPS76850
I
O
= 1 A, T
J
= -40°C to 125°C 380
(3) IN voltage equals V
O
(typ) - 100 mV; TPS76801 output voltage set to 3.3 V nominal with external resistor divider. TPS76815, TPS76818,TPS76825, and TPS76827 dropout voltage limited by input voltage range limitations (i.e., TPS76830 input voltage needs to drop to 2.9V for purpose of this test).
FIGURE
vs Output current 2, 3, 4V
O
Output voltage
vs Free-air temperature 5, 6, 7Ground current vs Free-air temperature 8, 9Power supply ripple rejection vs Frequency 10Output spectral noise density vs Frequency 11Input voltage (min) vs Output voltage 12Z
o
Output impedance vs Frequency 13V
DO
Dropout voltage vs Free-air temperature 14Line transient response 15, 17Load transient response 16, 18V
O
Output voltage vs Time 19Dropout voltage vs Input voltage 20Equivalent series resistance (ESR) vs Output current 22 - 25
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TYPICAL CHARACTERISTICS
IO − Output Current − A
3.2830
3.2815
3.2800 0.1 0.3
3.2825
3.2820
3.2810
0.2 0.8 1
3.2835
0 0.9
− Output Voltage − V
VO
3.2805
0.4 0.5 0.6 0.7
VI = 4.3 V
TA = 25°C
IO − Output Current − A
1.4975
1.4960
1.4950
1.4970
1.4965
1.4955
1.4985
− Output Voltage − V
VO
1.4980
0.1 0.30.2 0.8 10 0.90.4 0.5 0.6 0.7
VI = 2.7 V
TA = 25°C
IO − Output Current − A
2.4955
2.4940
2.4920 0.1 0.3
2.4950
2.4945
2.4935
0.2 0.4 0.6
2.4960
0 0.5
− Output Voltage − V
VO
VI = 3.5 V
TA = 25°C
2.4930
2.4925
0.80.7 0.9 1
TA − Free-Air Temperature − °C
− Output Voltage − V
VO
3.31
3.28
3.25 −40 0
3.30
3.29
3.27
−20 100 140
3.32
−60 120
3.26
20 40 60 80
VI = 4.3 V
IO = 1 A IO = 1 mA
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
TPS76833 TPS76815OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 2. Figure 3.
TPS76825 TPS76833OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT FREE-AIR TEMPERATURE
Figure 4. Figure 5.
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TA − Free-Air Temperature − °C
− Output Voltage − V
VO
1.515
1.500
1.485 −40 0
1.510
1.505
1.495
−20 100−60 120
1.490
20 40 60 80
VI = 2.7 V
IO = 1 A
IO = 1 mA
140
TA − Free-Air Temperature − °C
− Output Voltage − V
VO
−40 0−20 100−60 12020 40 60 80
2.515
2.500
2.480
2.510
2.505
2.495
2.490
2.485
VI = 3.5 V
IO = 1 A
IO = 1 mA
TA − Free-Air Temperature − °C
Ground Current − Aµ
−40 0−20 100−60 12020 40 60 80 140
VI = 2.7 V
IO = 1 A
100
95
90
85
80
75
IO = 1 mA
IO = 500 mA
TA − Free-Air Temperature − °C
Ground Current − Aµ
92
84
72
90
88
82
80
78
76
74
86
−40 0−20 100−60 12020 40 60 80 140
VI = 4.3 V
IO = 500 mA
IO = 1 A
IO = 1 mA
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
TPS76815 TPS76825OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 6. Figure 7.
TPS76833 TPS76815GROUND CURRENT GROUND CURRENTvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 8. Figure 9.
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100k10k
PSRR − Power Supply Ripple Rejection − dB
f − Frequency − Hz
70
60
50
40
30
20
10
0
−10
90
80
1k10010 1M
VI = 4.3 V
Co = 10 µF
IO = 1 A
TA = 25°C
f − Frequency − Hz
102103104105
10−5
10−6
10−8
10−7
IO = 7 mA
IO = 1 A
VI = 4.3 V
Co = 10 µF
TA = 25°C
VHzOutput Spectral Noise Density − µ
3
2.7
21.5 1.75 2 2.25 2.5 2.75
− Input Voltage (Min) − V
4
33.25 3.5
TA = 25°C
VI
VO − Output Voltage − V
IO = 1 A
TA = 125°C
TA = −40°C
f − Frequency − kHz
− Output Impedance −ZoΩ
101102105106
0
10−1
10−2 104
103
IO = 1 mA
IO = 1 A
VI = 4.3 V
Co = 10 µF
TA = 25°C
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
TPS76833 TPS76833POWER SUPPLY RIPPLE REJECTION OUTPUT SPECTRAL NOISE DENSITYvs vsFREQUENCY FREQUENCY
Figure 10. Figure 11.
TPS76833INPUT VOLTAGE (MIN) OUTPUT IMPEDANCEvs vsOUTPUT VOLTAGE FREQUENCY
Figure 12. Figure 13.
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TA − Free-Air Temperature − °C
−40 0 20 120
103
−60 40 60 80 100
− Dropout Voltage − mV
VDO
102
101
100
10−1
10−2 −20 140
IO = 1 A
IO = 10 mA
IO = 0
Co = 10 µF
VO− Change in
10
0
3.7
2.7
VI
t − Time − µs
0604020 80 100 140120 160 180 200
− Input Voltage − V
∆
Output Voltage − mV
Co = 10 µF
TA = 25°C
−10
t − Time − µs
VO− Change in VI− Input Voltage − V
∆
Output Voltage − mV
5.3
604020 80 100 140120 160 180 200
Co = 10 µF
TA = 25°C
0
4.3
10
0
−10
t − Time − µs
I − Output Current − A
OVO− Change in∆
Output Voltage − mV
Co = 10 µF
TA = 25°C
1
0.5
0
0 300200100 400 500 700600 800 900 1000
0
50
100
−50
−100
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
TPS76833
DROPOUT VOLTAGE
vs TPS76815FREE-AIR TEMPERATURE LINE TRANSIENT RESPONSE
Figure 14. Figure 15.
TPS76815 TPS76833LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 16. Figure 17.
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t − Time − ms
3
2
0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 10
VO− Output V oltage − V
0
1
4
Enable Pulse − V
Co = 10 µF
IO = 1 A
TA = 25°C
t − Time − µs
I − Output Current − A
OVO− Change in∆
Output Voltage − mV
1
0.5
300200100 400 500 700600 800 900 10000
Co = 10 µF
TA = 25°C
0
0
50
100
−50
−100
VI − Input Voltage − V
600
300
03 4
500
400
200
3.52.5
− Dropout Voltage − mV
100
4.5 5
VDO
900
800
700
TA = 125°C
TA = −40°C
TA = 25°C
IO = 1 A
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
TPS76833
OUTPUT VOLTAGETPS76833 vsLOAD TRANSIENT RESPONSE TIME (AT START-UP)
Figure 18. Figure 19.
TPS76801
DROPOUT VOLTAGE
vsINPUT VOLTAGE
Figure 20.
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IN
EN
OUT
+
GND Co
ESR
RL
VITo Load
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
Figure 21. Test Circuit for Typical Regions of Stability (Figure 22 through Figure 25 )(Fixed Output Options)
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IO − Output Current − mA
ESR − Equivalent Series Resistance − Ω
0.1
0 200 400 600 800 1000
10
1
0.01
Region of Instability
VO = 3.3 V
Co = 4.7 µF
VI = 4.3 V
TJ = 125°C
Region of Stability
Region of Instability
ESR − Equivalent Series Resistance − Ω
0.1
0 200 400 600 800 1000
10
IO − Output Current − mA
1
0.01
Region of Instability
VO = 3.3 V
Co = 4.7 µF
VI = 4.3 V
TA = 25°CRegion of Stability
Region of Instability
ESR − Equivalent Series Resistance − Ω
0.1
0 200 400 600 800 1000
10
1
IO − Output Current − mA
0.01
Region of Instability
VO = 3.3 V
Co = 22 µF
VI = 4.3 V
TJ = 125°C
Region of Stability
Region of Instability
ESR − Equivalent Series Resistance − Ω
0.1
0 200 400 600 800 1000
10
IO − Output Current − mA
1
Region of Instability
Region of Stability
VO = 3.3 V
Co = 22 µF
VI = 4.3 V
TA = 25°C
0.01
Region of Instability
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, anyseries resistance added externally, and PWB trace resistance to C
O
.
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITYEQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 22. Figure 23.
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITYEQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 24. Figure 25.
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APPLICATION INFORMATION
DEVICE OPERATION
MINIMUM LOAD REQUIREMENTS
FB - PIN CONNECTION (ADJUSTABLE VERSION ONLY)
EXTERNAL CAPACITOR REQUIREMENTS
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
The TPS768xx family includes eight fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, 2.7 V, 2.8 V, 3.0 V, 3.3V, and 5.0 V), and offers an adjustable device, the TPS76801 (adjustable from 1.2 V to 5.5 V).
The TPS768xx features very low quiescent current, which remains virtually constant even with varying loads.Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to theload current through the regulator (I
B
= I
C
/β). The TPS768xx uses a PMOS transistor to pass current; becausethe gate of the PMOS is voltage driven, operating current is low and invariable over the full load range.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes intodropout. The resulting drop in βforces an increase in I
B
to maintain the load. During power up, this translates tolarge start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, itmeans rapid battery discharge when the voltage decays below the minimum required for regulation. TheTPS768xx quiescent current remains low even when the regulator drops out, eliminating both problems.
The TPS768xx family also features a shutdown mode that places the output in the high-impedance state(essentially equal to the feedback-divider resistance) and reduces quiescent current to 2 µA. If the shutdownfeature is not used, EN should be tied to ground.
The TPS768xx family is stable even at zero load; no minimum load is required for operation.
The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option. The outputvoltage is sensed through a resistor divider network to close the loop as shown in Figure 27 . Normally, thisconnection should be as short as possible; however, the connection can be made near a critical circuit toimprove performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier andnoise pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup isessential.
An input capacitor is not usually required; however, a ceramic bypass capacitor (0.047 µF or larger) improvesload transient response and noise rejection if the TPS768xx is located more than a few inches from the powersupply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) loadtransients with fast rise times are anticipated.
Like all low dropout regulators, the TPS768xx requires an output capacitor connected between OUT and GND tostabilize the internal control loop. The minimum recommended capacitance value is 10 µF and the ESR(equivalent series resistance) must be between 60 mΩand 1.5 Ω. Capacitor values 10 µF or larger areacceptable, provided the ESR is less than 1.5Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayerceramic capacitors are all suitable, provided they meet the requirements described above. Most of thecommercially available 10 µF surface-mount ceramic capacitors, including devices from Sprague and Kemet,meet the ESR requirements stated above.
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PG
OUT
OUT
7
6
5
IN
IN
EN
GND
3
16
14
13
VI
C1
0.1 µF
PG
VO
10 µF
+
TPS768xx
Co
250 kΩ
VOVref 1R1
R2
where:
Vref = 1.1834 V typ (the internal reference voltage)
(1)
R1 VO
Vref 1R2
(2)
OUTPUT
VOLTAGE R1 R2
2.5 V
3.3 V
3.6 V
4.75 V
UNIT
33.2
53.6
61.9
90.8
30.1
30.1
30.1
30.1
kΩ
kΩ
kΩ
kΩ
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VO
VIPG
OUT
FB / NC
R1
R2
GND
EN
IN
≤ 0.9 V
≥ 1.7 V
TPS76801
PG
0.1 µF250 kΩ
POWER-GOOD INDICATOR
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
APPLICATION INFORMATION (continued)
Figure 26. Typical Application Circuit (Fixed Versions)
The output voltage of the TPS76801 adjustable regulator is programmed using an external resistor divider asshown in Figure 27 . The output voltage is calculated using:
Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can beused but offer no inherent advantage and waste more power. Higher values should be avoided as leakagecurrents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩto set the divider current at 50 µA and then calculate R1 using:
Figure 27. TPS76801 Adjustable LDO Regulator Programming
The TPS768xx features a power-good (PG) output that can be used to monitor the status of the regulator. Theinternal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominalregulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pullupresistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or used as alow-battery indicator. PG does not assert itself when the regulated output voltage falls out of the specified 2%tolerance, but instead reports an output voltage low, relative to its nominal regulated value.
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REGULATOR PROTECTION
POWER DISSIPATION AND JUNCTION TEMPERATURE
PD(max)
TJmax TA
RJA
where:
TJmax is the maximum allowable junction temperature.
TA is the ambient temperature.
RθJA is the thermal resistance junction-to-ambient for the package, i.e., 172°C/W for the 8-terminal
SOIC and 32.6°C/W for the 20-terminal PWP with no airflow.
(3)
PDVIVOIO
(4)
TPS76815Q, TPS76818Q , TPS76825QTPS76827Q, TPS76828Q, TPS76830QTPS76833Q, TPS76850Q, TPS76801Q
SLVS211I – JUNE 1999 – REVISED JANUARY 2004
APPLICATION INFORMATION (continued)
The TPS768xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the inputvoltage drops below the output voltage (e.g., during power down). Current is conducted from the output to theinput and is not internally limited. When extended reverse voltage is anticipated, external limiting may beappropriate.
The TPS768xx also features internal current limiting and thermal protection. During normal operation, theTPS768xx limits output current to approximately 1.7 A. When current limiting engages, the output voltage scalesback linearly until the overcurrent condition ends. While current limiting is designed to prevent gross devicefailure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of thedevice exceeds 150°C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator operation resumes.
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperatureshould be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation theregulator can handle in any given application. To ensure the junction temperature is within acceptable limits,calculate the maximum allowable dissipation, P
D(max)
, and the actual dissipation, P
D
, which must be less than orequal to P
D(max)
.
The maximum-power-dissipation limit is determined using the following equation:
The regulator dissipation is calculated using:
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger thethermal protection circuit.
17
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