VIN
SW
BST
LM5010
VCC
SS
RON / SD
8V - 75V
Input
C1
RON
R2
R1 C2
VOUT
L1
C3
C4
D1
C6
RTN
ISEN
SGND
FB
SHUTDOWN
LM5010
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SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
High-Voltage 1-A Step-Down Switching Regulator
Check for Samples: LM5010
1FEATURES APPLICATIONS
2• Input Voltage Range: 8V to 75V • High Efficiency Point-Of-Load (POL) Regulator
• Valley Current Limit At 1.25A • Non-Isolated Telecommunications Buck
Regulator
• Switching Frequency Can Exceed 1 MHz • Secondary High Voltage Post Regulator
• Integrated N-Channel Buck Switch • Automotive Systems
• Integrated Startup Regulator
• No Loop Compensation Required DESCRIPTION
• Ultra-Fast Transient Response The LM5010 Step Down Switching Regulator features
• Operating Frequency Remains Constant With all the functions needed to implement a low cost,
Load and Line Variations efficient, buck bias regulator capable of supplying in
excess of 1A load current. This high voltage regulator
• Maximum Duty Cycle Limited During Startup contains an N-Channel Buck Switch, and is available
• Adjustable Output Voltage in thermally enhanced 10-pin WSON and 14-pin
• Precision 2.5V Feedback Reference HTSSOP packages. The hysteretic regulation
scheme requires no loop compensation, results in
• Thermal shutdown fast load transient response, and simplifies circuit
• Packages implementation. The operating frequency remains
– 10-Pin WSON (4 mm x 4 mm) constant with line and load variations due to the
– 14-Pin HTSSOP inverse relationship between the input voltage and
the on-time. The valley current limit detection is set at
– Both Packages Have Exposed Thermal Pad 1.25A. Additional features include: VCC under-voltage
For Improved Heat Dissipation lockout, thermal shutdown, gate drive under-voltage
lockout, and maximum duty cycle limiter.
DEVICE INFORMATION
Figure 1. Basic Step-Down Regulator
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Top View
14 Lead HTSSOP
SW
BST VCC
VIN
NC
NC NC
NC
RTN FB
SS
11
10
9
5
4
3
2
1
6
7 8
12
13
14
RON /SD
ISEN
SGND
SW
BST
RTN
VCC
FB
SS
VIN
Top View
10 Lead WSON
10
9
8
7
6
5
4
3
2
1
/SDRON
SGND
ISEN
LM5010
SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
www.ti.com
Connection Diagram
Pin Functions
Table 1. Pin Description
PIN NUMBER NAME DESCRIPTION APPLICATION INFORMATION
WSON- HTSSOP-
10 14
1 2 SW Switching Node Internally connected to the buck switch source. Connect to the
inductor, free-wheeling diode, and bootstrap capacitor.
2 3 BST Boost pin for bootstrap Connect a 0.022 µF capacitor from SW to this pin. The capacitor
capacitor is charged from VCC via an internal diode during each off-time.
3 4 ISEN Current sense The re-circulating current flows through the internal sense
resistor, and out of this pin to the free-wheeling diode. Current
limit is nominally set at 1.25A.
4 5 SGND Sense Ground Re-circulating current flows into this pin to the current sense
resistor.
5 6 RTN Circuit Ground Ground for all internal circuitry other than the current limit
detection.
6 9 FB Feedback input from the Internally connected to the regulation and over-voltage
regulated output comparators. The regulation level is 2.5V.
7 10 SS Softstart An internal 11.5 µA current source charges an external capacitor
to 2.5V, providing the soft start function.
8 11 RON/SD On-time control and shutdown An external resistor from VIN to this pin sets the buck switch on-
time. Grounding this pin shuts down the regulator.
9 12 VCC Output from the startup Nominally regulates at 7.0V. An external voltage (7.5V-14V) can
regulator be applied to this pin to reduce internal dissipation. An internal
diode connects VCC to VIN.
10 13 VIN Input supply voltage Nominal input range is 8.0V to 75V.
1, 7, 8, 14 NC No connection No internal connection.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
VIN to GND 76V
BST to GND 90V
SW to GND (Steady State) -1.5V
BST to VCC 76V
BST to SW 14V
VCC to GND 14V
SGND to RTN -0.3V to +0.3V
SS to RTN -0.3V to 4V
VIN to SW 76V
Current Out of ISEN See Text
All Other Inputs to GND -0.3 to 7V
ESD Rating, Human Body Model(2) 2kV
Storage Temperature Range -55°C to +150°C
Lead Temperature (Soldering 4 sec) (3) 260°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
(2) The human body model is a 100pF capacitor discharged through a 1.5kΩresistor into each pin.
(3) For detailed information on soldering plastic HTSSOP and WSON packages, refer to the Packaging Data Book.
Operating Ratings (1)
VIN 8V to 75V
Operating Junction Temperature −40°C to + 125°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
Electrical Characteristics
Specifications with standard typeface are for TJ= 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, RON = 200kΩ, unless otherwise stated (1) and (2).
Symbol Parameter Test Conditions Min Typ Max Unit
VCC Regulator
VCCReg VCC regulated output 6.6 77.4 Volts
VIN - VCC ICC = 0 mA, FS< 200 kHz, 1.3 V
7.5V ≤VIN ≤8.0V
VCC output impedance (0 mA ≤ICC ≤5 mA) VIN = 8.0V 140 Ω
VIN = 48V 2.5
VCC current limit(3) VCC = 0V 10 mA
UVLOVCC VCC under-voltage lockout threshold VCC increasing 5.8 V
UVLOVCC hysteresis VCC decreasing 145 mV
UVLOVCC filter delay 100 mV overdrive 3 µs
IIN operating current Non-switching, FB = 3V 650 850 µA
IIN shutdown current RON/SD = 0V 95 200 µA
(1) Typical specifications represent the most likely parametric norm at 25°C operation.
(2) All electrical characteristics having room temperature limits are tested during production with TA= 25°C. All hot and cold limits are
specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(3) VCC provides bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.
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SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
www.ti.com
Electrical Characteristics (continued)
Specifications with standard typeface are for TJ= 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, RON = 200kΩ, unless otherwise stated (1) and (2).
Symbol Parameter Test Conditions Min Typ Max Unit
Switch Characteristics
Rds(on) Buck Switch Rds(on) ITEST = 200 mA 0.35 0.80 Ω
UVLOGD Gate Drive UVLO VBST - VSW Increasing 3.0 4.3 5.0 V
UVLOGD hysteresis 440 mV
Softstart Pin
Pull-up voltage 2.5 V
Internal current source 11.5 µA
Current Limit
ILIM Threshold Current out of ISEN 11.25 1.5 A
Resistance from ISEN to SGND 130 mΩ
Response time 150 ns
On Timer, RON/SD Pin
tON - 1 On-time VIN = 10V, RON = 200 kΩ2.1 2.75 3.4 µs
tON - 2 On-time VIN = 75V, RON = 200 kΩ290 390 490 ns
Shutdown threshold Voltage at RON/SD rising 0.35 0.65 1.1 V
Threshold hysteresis Voltage at RON/SD falling 40 mV
Off Timer
tOFF Off-time 265 ns
Regulation and Over-Voltage Comparators (FB Pin)
VREF FB regulation threshold SS pin = steady state 2.445 2.5 2.550 V
FB over-voltage threshold 2.9 V
FB bias current 1 nA
Thermal Shutdown
TSD Thermal shutdown temperature 175 °C
Thermal shutdown hysteresis 20 °C
Thermal Resistance
θJA Junction to Ambient WSON-10 Package 40 °C/W
HTSSOP-14 Package 40
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FB
VCC
SW
RTN
DRIVER
BST
2.5V
62.5 mV
SS L1
C2
R1
R2
C4
C3
LM5010
D1
R3
10
8
7
3
4
1
2
9
7V START-UP
REGULATOR
RSENSE
+
-
C6
6
5
C1
C5
REGULATION
COMPARATOR
LEVEL
SHIFT
CURRENT LIMIT
COMPARATOR
ON TIMER
START
RON
LOGIC
Driver
Gate Drive
UVLO
COMPLETE
START
265 ns
OFF TIMER
2.9V
OVER-VOLTAGE
COMPARATOR
GND
11.5 PA
COMPLETE
50 m:
RON/SD
VCC
UVLO Thermal
Shutdown
0.7V
INPUT
VOUT2
VOUT1
VIN
ISEN
SGND
RCL
VIN
RON
LM5010
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SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
TYPICAL APPLICATION CIRCUIT AND BLOCK DIAGRAM
NOTE: Pin numbers are for the WSON-10 package.
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0 8 20 40 60 80
VIN (V)
4.0
3.0
2.0
1.0
0
RON/SD PIN VOLTAGE (V)
RON = 50k
301k
511k
115k
0 8 20 40 60 80
VIN (V)
IIN (PA)
0
100
200
300
400
500
600
700
800
FB = 3V
RON/SD = 0V
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
ICC INPUT CURRENT(mA)
78 9 10 11 12 13
EXTERNALLY APPLIED VCC (V)
14
FS = 200 kHz
FS = 550 kHz
FS = 100 kHz
300k
0 8 20 40 60 80
VIN (V)
100k
RON = 500k
0
1
2
3
4
5
6
7
8
9
ON-TIME (Ps)
0 2 4 6 8 10
0
1
2
3
4
5
6
7
8
VCC (V)
ICC (mA)
VIN = 48V
VIN = 8V
VIN = 9V
VCC Externally Loaded
FS = 100 kHz
LM5010
SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
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Typical Performance Characteristics
Figure 2. VCC vs VIN Figure 3. VCC vs ICC
Figure 4. ICC vs Externally Applied VCC Figure 5. On-Time vs VIN and RON
Figure 6. Voltage at RON/SD Pin Figure 7. IIN vs VIN
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UVLO
VIN
SW Pin
Inductor
Current
SS Pin
VOUT
2.5V
7.0V
VCC
t1 t2
LM5010
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SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
Typical Performance Characteristics (continued)
Figure 8. Startup Sequence
FUNCTIONAL DESCRIPTION
The LM5010 Step Down Switching Regulator features all the functions needed to implement a low cost, efficient
buck bias power converter capable of supplying in excess of 1A to the load. This high voltage regulator contains
an N-Channel buck switch, is easy to implement, and is available in the thermally enhanced WSON-10 and
HTSSOP-14 packages. The regulator’s operation is based on a hysteretic control scheme, and uses an on-time
which varies inversely with VIN. This feature results in the operating frequency remaining relatively constant with
load and input voltage variations. The switching frequency can range from 100 kHz to > 1.0 MHz. The hysteretic
control requires no loop compensation resulting in very fast load transient response. The valley current limit
detection circuit, internally set at 1.25A, holds the buck switch off until the high current level subsides. Typical
Application Circuit and Block Diagram shows the functional block diagram. The LM5010 can be applied in
numerous applications to efficiently regulate down higher voltages. This regulator is well suited for 48V telecom
applications, as well as the new 42V automotive power bus. Implemented as a Point-of-Load regulator following
a highly efficient intermediate bus converter can result in high overall system efficiency. Features include:
Thermal shutdown, VCC under-voltage lockout, gate drive under-voltage lockout, and maximum duty cycle limit.
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Product Folder Links: LM5010
FB
SW
L1
C2
R3
LM5010 R1
R2
VOUT2
FS = VOUT2 x L1 x 1.4 x 1020
RL x (RON)2
DC = tON
tON + tOFF
VOUT
VIN
=
FS = VOUT
1.18 x 10-10 x RON
LM5010
SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
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Hysteretic Control Circuit Overview
The LM5010 buck DC-DC regulator employs a control scheme based on a comparator and a one-shot on-timer,
with the output voltage feedback (FB) compared to an internal reference (2.5V). If the FB voltage is below the
reference the buck switch is turned on for a time period determined by the input voltage and a programming
resistor (RON). Following the on-time the switch remains off for 265 ns, or until the FB voltage falls below the
reference, whichever is longer. The buck switch then turns on for another on-time period. Typically when the load
current increases suddenly, the off-times are temporarily at the minimum of 265 ns. Once regulation is
established, the off-time resumes its normal value. The output voltage is set by two external resistors (R1, R2).
The regulated output voltage is calculated as follows:
VOUT = 2.5V x (R1 + R2) / R2 (1)
Output voltage regulation is based on ripple voltage at the feedback input, requiring a minimum amount of ESR
for the output capacitor C2. The LM5010 requires a minimum of 25 mV of ripple voltage at the FB pin. In cases
where the capacitor’s ESR is insufficient additional series resistance may be required (R3 in Typical Application
Circuit and Block Diagram).
When in regulation, the LM5010 operates in continuous conduction mode at heavy load currents and
discontinuous conduction mode at light load currents. In continuous conduction mode current always flows
through the inductor, never reaching zero during the off-time. In this mode the operating frequency remains
relatively constant with load and line variations. The minimum load current for continuous conduction mode is
one-half the inductor’s ripple current amplitude. The approximate operating frequency is calculated as follows:
(2)
The buck switch duty cycle is approximately equal to:
(3)
At low load current, the circuit operates in discontinuous conduction mode, during which the inductor current
ramps up from zero to a peak during the on-time, then ramps back to zero before the end of the off-time. The
next on-time period starts when the voltage at FB falls below the reference - until then the inductor current
remains zero, and the load current is supplied by the output capacitor (C2). In this mode the operating frequency
is lower than in continuous conduction mode, and varies with load current. Conversion efficiency is maintained at
light loads since the switching losses reduce with the reduction in load and frequency. The approximate
discontinuous operating frequency can be calculated as follows:
(4)
where RL= the load resistance.
For applications where lower output voltage ripple is required the output can be taken directly from a low ESR
output capacitor as shown in Figure 9. However, R3 slightly degrades the load regulation.
Figure 9. Low Ripple Output Configuration
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tON = 1.18 x 10-10 x (RON + 1.4k)
VIN - 1.4V + 67 ns
FB
SW
L1
C2
R1
R2
R3
BST
VCC
D2
C3
C4
D1
LM5010
VOUT2
VOUT1
SGND
ISEN
LM5010
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SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
Start-up Regulator (VCC)
The startup regulator is integral to the LM5010. The input pin (VIN) can be connected directly to line voltages up
to 75V. The VCC output is regulated at 7.0V, ±6%, and is current limited to 10 mA. Upon power up the regulator
sources current into the external capacitor at VCC (C3). With a 0.1 µF capacitor at VCC, approximately 58 µs are
required for the VCC voltage to reach the under-voltage lockout threshold (UVLO) of 5.8V (t1 in Figure 8), at
which time the buck switch is enabled, and the soft start pin is released to allow the soft start capacitor (C6) to
charge up. VOUT then increases to its regulated value as the soft start voltage increases (t2 in Figure 8).
The minimum input operating voltage is determined by the regulator’s dropout voltage, the VCC UVLO falling
threshold (≊5.65V), and the frequency. When VCC falls below the falling threshold the VCC UVLO activates to shut
off the buck switch and ground the soft start pin. If VCC is externally loaded, the minimum input voltage increases
since the output impedance at VCC is ≊140Ωat low VIN. See Figure 2 and Figure 3. In applications involving a
high value for VIN where power dissipation in the startup regulator is a concern, an auxiliary voltage can be diode
connected to the VCC pin (Figure 10). Setting the auxiliary voltage to between 7.5V and 14V shuts off the internal
regulator, reducing internal power dissipation. The current required into the VCC pin is shown in Figure 4.
Internally a diode connects VCC to VIN.
Figure 10. Self Biased Configuration
Regulation Comparator
The feedback voltage at FB is compared to the voltage at the Softstart pin (2.5V, ±2%). In normal operation (the
output voltage is regulated) an on-time period is initiated when the voltage at FB falls below 2.5V. The buck
switch stays on for the on-time causing the FB voltage to rise above 2.5V. After the on-time period the buck
switch stays off until the FB voltage falls below 2.5V. Bias current at the FB pin is less than 5 nA over
temperature.
Over-Voltage Comparator
The feedback voltage at FB is compared to an internal 2.9V reference. If the voltage at FB rises above 2.9V the
on-time is immediately terminated. This condition can occur if the input voltage, or the output load, change
suddenly. The buck switch will not turn on again until the voltage at FB falls below 2.5V.
ON-Time Control
The on-time of the internal switch (see Figure 5) is determined by the RON resistor and the input voltage (VIN),
calculated from the following:
(5)
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'I = (VIN - VOUT) x tON
L1
VIN
STOP
RON/SD
RON
Input
Voltage
LM5010
RUN
LM5010
SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
www.ti.com
The inverse relationship of tON vs. VIN results in a nearly constant frequency as VIN is varied. If the application
requires a high frequency the minimum value for tON, and consequently RON, is limited by the off-time (265 ns,
±15%) which limits the maximum duty cycle at minimum VIN. The tolerance for Equation 5 is ±25%. Frequencies
in excess of 1 MHz are possible with the LM5010.
Shutdown
The LM5010 can be remotely shut down by taking the RON/SD pin below 0.65V. See Figure 11. In this mode the
soft start pin is internally grounded, the on-timer is disabled, and the input current at VIN is reduced (Figure 7).
Releasing the RON/SD pin allows normal operation to resume. When the switch is open, the nominal voltage at
RON/SD is shown in Figure 6.
Figure 11. Shutdown Implementation
Current Limit
Current limit detection occurs during the off-time by monitoring the recirculating current through the free-wheeling
diode (D1). The detection threshold is 1.25A, ±0.25A. Referring to Typical Application Circuit and Block Diagram,
when the buck switch is off the inductor current flows through the load, into SGND, through the sense resistor, out
of ISEN and through D1. If that current exceeds the threshold the current limit comparator output switches to delay
the start of the next on-time period. The next on-time starts when the current out of ISEN is below the threshold
and the voltage at FB is below 2.5V. If the overload condition persists causing the inductor current to exceed the
threshold during each on-time, that is detected at the beginning of each off-time. The operating frequency is
lower due to longer-than-normal off-times.
Figure 12 illustrates the inductor current waveform. During normal operation the load current is IO, the average of
the ripple waveform. When the load resistance decreases the current ratchets up until the lower peak attempts to
exceed the threshold. During the Current Limited portion of Figure 12, the current ramps down to the threshold
during each off-time, initiating the next on-time (assuming the voltage at FB is < 2.5V). During each on-time the
current ramps up an amount equal to:
(6)
During this time the LM5010 is in a constant current mode, with an average load current (IOCL) equal to the
threshold + ΔI/2.
The “valley current limit” technique allows the load current to exceed the current limit threshold as long as the
lower peak of the inductor current is less than the threshold.
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Threshold
IPK
'I
IOCL
IO
Inductor Current
Load Current
Increases
Normal Operation Current Limited
LM5010
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SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
Figure 12. Inductor Current - Current Limit Operation
The current limit threshold can be increased by connecting an external resistor (RCL) between SGND and ISEN. The
external resistor typically is less than 1Ω, and its calculation is explained in the Applications Information section.
The peak current out of SW and ISEN must not exceed 3.5A. The average current out of SW must be less than
3A, and the average current out of ISEN must be less than 2A.
N-Channel Buck Switch and Driver
The LM5010 integrates an N-Channel buck switch and associated floating high voltage gate driver. The peak
current through the buck switch must not be allowed to exceed 3.5A, and the average current must be less than
3A. The gate driver circuit is powered by the external bootstrap capacitor between BST and SW (C4). During
each off-time, the SW pin is at approximately -1V, and C4 is re-charged from VCC through the internal high
voltage diode. The minimum off-time of 265 ns ensures a minimum time each cycle to recharge the bootstrap
capacitor. A 0.022 µF ceramic capacitor is recommended for C4.
Soft Start
The soft start feature allows the converter to gradually reach a steady state operating point, thereby reducing
startup stresses and current surges. Upon turn-on, after VCC reaches the under-voltage threshold (t1 in Figure 8),
an internal 11.5 µA current source charges the external capacitor at the Softstart pin to 2.5V (t2 in Figure 8). The
ramping voltage at SS (and at the non-inverting input of the regulation comparator) ramps up the output voltage
in a controlled manner. This feature keeps the load current from going to current limit during startup, thereby
reducing inrush currents.
An internal switch grounds the Softstart pin if VCC is below the under-voltage lockout threshold, if a thermal
shutdown occurs, or if the circuit is shutdown using the RON/SD pin.
Thermal Shutdown
The LM5010 should be operated so the junction temperature does not exceed 125°C. If the junction temperature
increases above that, an internal Thermal Shutdown circuit activates (typically) at 175°C, taking the controller to
a low power reset state by disabling the buck switch and the on-timer, and grounding the Softstart pin. This
feature helps prevent catastrophic failures from accidental device overheating. When the junction temperature
reduces below 155°C (typical hysteresis = 20°C), the Softstart pin is released and normal operation resumes.
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Product Folder Links: LM5010
L1 = 0.30A x 463 kHz x 75V
10V x (75V - 10V) = 63 PH
L1 = IOR x FS(min) x VIN(max)
VOUT1 x (VIN(max) - VOUT1)
L1 Current
0 mA
IOR
1/Fs
IPK+
IO
IPK-
RON = 10V
1.18 x 10-10 x 625 kHz= 136 k:
LM5010
SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
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APPLICATIONS INFORMATION
EXTERNAL COMPONENTS
The procedure for calculating the external components is illustrated with a design example. The circuit in Typical
Application Circuit and Block Diagram is to be configured for the following specifications:
• VOUT = 10V
• VIN = 15V to 75V
• FS= 625 kHz
• Minimum load current = 150 mA
• Maximum load current = 1.0A
• Softstart time = 5 ms
R1 and R2: The ratio of these resistors is calculated from:
R1/R2 = (VOUT/2.5V) - 1 (7)
R1/R2 calculates to 3.0. The resistors should be chosen from standard value resistors in the range of 1.0 kΩ- 10
kΩ. Values of 3.0 kΩfor R1, and 1.0 kΩfor R2 will be used.
RON, FS:RON sets the on-time, and can be chosen using Equation 2 to set a nominal frequency, or from
Equation 5 if the on-time at a particular VIN is important. A higher frequency generally means a smaller inductor
and capacitors (value, size and cost), but higher switching losses. A lower frequency means a higher efficiency,
but with larger components. If PC board space is tight, a higher frequency is better. The resulting on-time and
frequency have a ±25% tolerance. Re-arranging Equation 2,
(8)
The next larger standard value (137 kΩ) is chosen for RON, yielding a nominal frequency of 618 kHz.
L1: The inductor value is determined based on the load current, ripple current, and the minimum and maximum
input voltage (VIN(min), VIN(max)). Refer to Figure 13.
Figure 13. Inductor Current
To keep the circuit in continuous conduction mode, the maximum allowed ripple current is twice the minimum
load current, or 300 mAp-p. Using this value of ripple current, the inductor (L1) is calculated using the following:
(9)
where FS(min) is the minimum frequency (FS- 25%).
(10)
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ESR(min) = R2 x IOR(min)
25 mV x (R1 + R2) = 2.8:
IOR(min) = L1MAX x FS(max) x VIN(min)
VOUT1 x (VIN(min) - VOUT1)
120 PH x 772 kHz x 15V
10V x (15V - 10V) = 36 mA
=
IOR(max) = 80 PH x 463 kHz x 75V
10V x (75V - 10V) = 234 mAp-p
IOR(max) = L1MIN x FS(min) x VIN(max)
VOUT1 x (VIN(max) - VOUT1)
LM5010
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SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
This provides a minimum value for L1 - the next higher standard value (100 µH) will be used. L1 must be rated
for the peak current (IPK+) to prevent saturation. The peak current occurs at maximum load current with maximum
ripple. The maximum ripple is calculated by re-arranging Equation 9 using VIN(max), FS(min), and the minimum
inductor value, based on the manufacturer’s tolerance. Assume, for this exercise, the inductor’s tolerance is
±20%.
(11)
(12)
IPK+ = 1.0A + 0.234A / 2 = 1.117A (13)
RCL:Since it is obvious that the lower peak of the inductor current waveform does not exceed 1.0A at maximum
load current (see Figure 13), it is not necessary to increase the current limit threshold. Therefore RCL is not
needed for this exercise. For applications where the lower peak exceeds 1.0A, see the section below on
increasing the current limit threshold.
C2 and R3: Since the LM5010 requires a minimum of 25 mVp-p of ripple at the FB pin for proper operation, the
required ripple at VOUT1 is increased by R1 and R2. This necessary ripple is created by the inductor ripple current
acting on C2’s ESR + R3. First, the minimum ripple current is determined.
(14)
The minimum ESR for C2 is then equal to:
(15)
If the capacitor used for C2 does not have sufficient ESR, R3 is added in series as shown in Typical Application
Circuit and Block Diagram. C2 should generally be no smaller than 3.3 µF, although that is dependent on the
frequency and the allowable ripple amplitude at VOUT1. Experimentation is usually necessary to determine the
minimum value for C2, as the nature of the load may require a larger value. A load which creates significant
transients requires a larger value for C2 than a non-varying load.
D1: The important parameters are reverse recovery time and forward voltage drop. The reverse recovery time
determines how long the current surge lasts each time the buck switch is turned on. The forward voltage drop is
significant in the event the output is short-circuited as it is mainly this diode’s voltage (plus the voltage across the
current limit sense resistor) which forces the inductor current to decrease during the off-time. For this reason, a
higher voltage is better, although that affects efficiency. A reverse recovery time of ≊30 ns, and a forward voltage
drop of ≊0.75V are preferred. The reverse leakage specification is important as that can significantly affect
efficiency. Other types of diodes may have a lower forward voltage drop, but may have longer recovery times, or
greater reverse leakage. D1 should be rated for the maximum VIN, and for the peak current when in current limit
(IPK in Figure 11) which is equal to:
IPK = 1.5A + IOR(max) = 1.734A (16)
where 1.5A is the maximum guaranteed current limit threshold, and the maximum ripple current was previously
calculated as 234 mAp-p. Note that this calculation is valid only when RCL is not required.
C1: Assuming the voltage supply feeding VIN has a source impedance greater than zero, this capacitor limits the
ripple voltage at VIN while supplying most of the switch current during the on-time. At maximum load current,
when the buck switch turns on, the current into VIN increases to the lower peak of the output current waveform,
ramps up to the peak value, then drops to zero at turn-off. The average current into VIN during this on-time is the
load current. For a worst case calculation, C1 must supply this average load current during the maximum on-
time. The maximum on-time is calculated using Equation 5, with a 25% tolerance added:
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM5010
SGND
VIN
SW
FB
BST
LM5010
SHUTDOWN
VCC
SS
RON / SD
15 - 75V
Input
137k
C1
2.2 PF
RON
R2
1.0k
R1
3.0k R3
2.8
GND
C2
15 PF
VOUT
10V
L1
100 PH
C3
0.1 PF
C4
0.022 PF
D1
C5
0.1 PF
C6
0.022 PF
RTN
ISEN
tSS = 11.5 PA
C6 x 2.5V
C1 = 'V
IO x tON = 1.57 PF
1V
1.0A x 1.57 Ps
=
tON(max) = 15V - 1.4V
1.18 x 10-10 x (137k + 1.4k) x 1.25 + 67 ns = 1.57 Ps
LM5010
SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
www.ti.com
(17)
C1 is calculated from:
(18)
where IOis the load current, and ΔV is the allowable ripple voltage at VIN (1V for this example). Quality ceramic
capacitors with a low ESR should be used for C1. To allow for capacitor tolerances and voltage effects, a 2.2 µF
capacitor will be used
C3: The capacitor at the VCC pin provides not only noise filtering and stability, but also prevents false triggering of
the VCC UVLO at the buck switch on/off transitions. For this reason, C3 should be no smaller than 0.1 µF, and
should be a good quality, low ESR, ceramic capacitor. This capacitor also determines the initial startup delay (t1
in Figure 8).
C4: The recommended value for C4 is 0.022 µF. A high quality ceramic capacitor with low ESR is recommended
as C4 supplies the surge current to charge the buck switch gate at turn-on. A low ESR also ensures a complete
recharge during each off-time.
C5: This capacitor suppresses transients and ringing due to long lead inductance at VIN. A low ESR, 0.1 µF
ceramic chip capacitor is recommended, located physically close to the LM5010.
C6: The capacitor at the SS pin determines the soft start time, i.e. the time for the reference voltage at the
regulation comparator, and the output voltage, to reach their final value. The time is determined from the
following:
(19)
For a 5 ms soft start time, C6 calculates to 0.022 µF.
FINAL CIRCUIT
The final circuit is shown in Figure 14, and its performance is shown in Figure 15 to Figure 18.
Figure 14. LM5010 Example Circuit
14 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LM5010
020 40 60 80
VIN (V)
0
50
100
150
200
250
300
350
OUTPUT RIPPLE (mVp-p)
FREQUENCY (kHz)
020 40 60 80
VIN (V)
700
600
500
400
300
0 200 400 600 800 _1000
0
20
40
60
80
_
100
EFFICIENCY (%)
LOAD CURRENT (mA)
VIN = 15V 24V
48V
75V
IOUT = 300mA
VIN (V)
0 20 40 60 80
EFFICIENCY (%)
0
20
40
60
80
100
LM5010
www.ti.com
SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
Table 2. Bill of Materials
Item Description Part No. Package Value
C1 Ceramic Capacitor TDK C4532X7R2A225M 1812 2.2 µF, 100V
C2 Ceramic Capacitor TDK C4532X7R1E156M 1812 15 µF, 25V
C3 Ceramic Capacitor Kemet C0805C104K4RAC 0805 0.1 µF, 16V
C4, C6 Ceramic Capacitor Kemet C0805C223K4RAC 0805 0.022 µF, 16V
C5 Ceramic Capacitor TDK C2012X7R2A104M 0805 0.1 µF, 100V
D1 Ultra fast diode Central Semi CMR2U-01 SMB 100V, 2A
L1 Inductor TDK SLF10145 10.1 x 10.1 100 µH
R1 Resistor Vishay CRCW08053001F 0805 3.0 kΩ
R2 Resistor Vishay CRCW08051001F 0805 1.0 kΩ
R3 Resistor Vishay CRCW08052R80F 0805 2.8 Ω
RON Resistor Vishay CRCW08051373F 0805 137 kΩ
U1 Switching regulator LM5010
Figure 15. Efficiency vs VIN Figure 16. Efficiency vs Load Current and VIN
Circuit of Figure 14 Circuit of Figure 14
Figure 17. Output Voltage Ripple vs VIN Figure 18. Frequency vs VIN
Circuit of Figure 14 Circuit of Figure 14
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM5010
IPK+(CL) = RCL
1.5A x (150 m: + RCL)+ IOR(MAX)
IPK+ = IO(max) + 2
IOR(max)
IAVE = (RCL + 0.11:x VIN(max)
IO(max) x RCL x (VIN(max) - VOUT)
RCL = 1.0A x 0.11:
IPK- - 1.0A
IPK- = IO(max) - 2
IOR(min)
LM5010
SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
www.ti.com
INCREASING THE CURRENT LIMIT THRESHOLD
The current limit threshold is nominally 1.25A, with a minimum guaranteed value of 1.0A. If, at maximum load
current, the lower peak of the inductor current (IPK-in Figure 13) exceeds 1.0A, resistor RCL must be added
between SGND and ISEN to increase the current limit threshold to equal or exceed that lower peak current. This
resistor diverts some of the recirculating current from the internal sense resistor so that a higher current level is
needed to switch the internal current limit comparator. IPK-is calculated from:
(20)
where IO(max) is the maximum load current, and IOR(min) is the minimum ripple current calculated using
Equation 14. RCL is calculated from:
(21)
where 0.11Ωis the minimum value of the internal resistance from SGND to ISEN. The next smaller standard value
resistor should be used for RCL. With the addition of RCL it is necessary to check the average and peak current
values to ensure they do not exceed the LM5010 limits. At maximum load current the average current through
the internal sense resistor is:
(22)
If IAVE is less than 2.0A no changes are necessary. If it exceeds 2.0A, RCL must be reduced. The upper peak of
the inductor current (IPK+), at maximum load current, is calculated using the following:
(23)
where IOR(max) is calculated using Equation 11. If IPK+ exceeds 3.5A , the inductor value must be increased to
reduce the ripple amplitude. This will necessitate recalculation of IOR(min), IPK-, and RCL.
When the circuit is in current limit, the upper peak current out of the SW pin is
(24)
The inductor L1 and diode D1 must be rated for this current.
PC BOARD LAYOUT
The LM5010 regulation, over-voltage, and current limit comparators are very fast, and will respond to short
duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout must be
as neat and compact as possible, and all the components must be as close as possible to their associated pins.
The current loop formed by D1, L1, C2, and the SGND and ISEN pins should be as small as possible. The ground
connection from C2 to C1 should be as short and direct as possible. If it is expected that the internal dissipation
of the LM5010 will produce high junction temperatures during normal operation, good use of the PC board’s
ground plane can help considerably to dissipate heat. The exposed pad on the IC package bottom can be
soldered to a ground plane, and that plane should both extend from beneath the IC, and be connected to
exposed ground plane on the board’s other side using as many vias as possible. The exposed pad is internally
connected to the IC substrate.
The use of wide PC board traces at the pins, where possible, can help conduct heat away from the IC. The four
No Connect pins on the HTSSOP package are not electrically connected to any part of the IC, and may be
connected to ground plane to help dissipate heat from the package. Judicious positioning of the PC board within
the end product, along with the use of any available air flow (forced or natural convection) can help reduce the
junction temperature.
16 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LM5010
LM5010
www.ti.com
SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013
REVISION HISTORY
Changes from Revision E (February 2013) to Revision F Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 16
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM5010
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5010MH NRND HTSSOP PWP 14 94 TBD Call TI Call TI -40 to 125 L5010
MH
LM5010MH/NOPB ACTIVE HTSSOP PWP 14 94 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5010
MH
LM5010MHX/NOPB ACTIVE HTSSOP PWP 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5010
MH
LM5010SD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L00057B
LM5010SDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L00057B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5010MHX/NOPB HTSSOP PWP 14 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1
LM5010SD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5010SDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5010MHX/NOPB HTSSOP PWP 14 2500 367.0 367.0 35.0
LM5010SD/NOPB WSON DPR 10 1000 210.0 185.0 35.0
LM5010SDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Oct-2013
Pack Materials-Page 2
MECHANICAL DATA
PWP0014A
www.ti.com
MXA14A (Rev A)
MECHANICAL DATA
DPR0010A
www.ti.com
SDC10A (Rev A)
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