MOTOROLA Freescale Semiconductor, Inc. Order this document by: DSP56001A/D, Rev. 1 SEMICONDUCTOR TECHNICAL DATA DSP56001A Product Preview Freescale Semiconductor, Inc... 24-BIT DIGITAL SIGNAL PROCESSOR The DSP56001A is an MPU-style general purpose Digital Signal Processor (DSP) composed of an efficient 24-bit DSP core, program and data memories, various peripherals, and support circuitry. The DSP56000 core is fed by on-chip Program RAM, two independent data RAMs, and two data ROMs containing sine, A-law, and -law tables. The DSP56001A contains a Serial Communication Interface (SCI), a Synchronous Serial Interface (SSI), and a parallel Host Interface (HI). This combination of features, illustrated in Figure 1, makes the DSP56001A a cost-effective, high-performance solution for high-precision general purpose digital signal processing. The DSP56001A is intended as a replacement for the DSP56001. The DSP56002 should be considered for new designs. 6 3 15 Sync. Serial (SSI) or I/O Serial Comm. (SCI) or I/O Host Interface (HI) or I/O 24-bit 56000 DSP Core 16-bit Bus 24-bit Bus Program Memory 512 x 24 RAM 64 x 24 ROM X Data Memory 256 x 24 RAM 256 x 24 ROM Y Data Memory 256 x 24 RAM 256 x 24 ROM (boot) (A-law/-law) (sine) PAB Address Generation Unit XAB YAB External Address Bus Switch Address 16 GDB Internal Data Bus Switch Clock Generator PDB XDB YDB Interrupt Control 2 Program Decode Controller Program Address Generator Data ALU 24 x 24 + 56 56-bit MAC Two 56-bit Accumulators External Data Bus Switch Bus Control Data 24 Control 7 Program Control Unit 2 AA0884 IRQ Figure 1 DSP56001A Block Diagram (c)1997 MOTOROLA, INC. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... TABLE OF CONTENTS SECTION 1 SIGNAL/PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SECTION 2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 SECTION 3 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 SECTION 4 DESIGN CONSIDERATIONS (INCLUDES NOTES FOR DSP56001 TO DSP56001A DESIGN CONVERSION) . . . . 4-1 SECTION 5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 SECTION A ROM TABLE LISTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 FOR TECHNICAL ASSISTANCE: Telephone: 1 (800) 521-6274 Email: dsphelp@dsp.sps.mot.com Internet: http://www.motorola-dsp.com Data Sheet Conventions This data sheet uses the following conventions: OVERBAR Used to indicate a signal that is active when pulled low; for example, the RESET pin is active when low "asserted" Means that a high true (active high) signal is high or that a low true (active low) signal is low "deasserted" Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Note: ii Signal/Symbol Logic State Signal State Voltage PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A DSP56001A Features DSP56001A FEATURES Freescale Semiconductor, Inc... Digital Signal Processing Core * Efficient, object code compatible, 24-bit 56000 family DSP engine * Up to 16.5 Million Instructions Per Second (MIPS)--60.6 ns instruction cycle at 33 MHz * Up to 99 Million Operations Per Second (MOPS) at 33 MHz * Executes a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks * Highly parallel instruction set with unique DSP addressing modes * Two 56-bit accumulators including extension byte * Parallel 24 x 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) * Double precision 48 x 48-bit multiply with 96-bit result in 6 instruction cycles * 56-bit addition/subtraction in 1 instruction cycle * Fractional arithmetic with support for multiprecision arithmetic * Hardware support for block-floating point FFT * Hardware nested DO loops * Zero-overhead fast interrupts (2 instruction cycles) * Four 24-bit internal data buses and three 16-bit internal address buses for maximum information transfer on-chip Memory * On-chip modified Harvard architecture permitting simultaneous accesses to program and two data memories * 512 x 24-bit on-chip Program RAM and 64 x 24-bit bootstrap ROM * Two 256 x 24-bit on-chip data RAMs * Two 256 x 24-bit on-chip data ROMs containing sine, A-law and -law tables * External memory expansion with 16-bit address and 24-bit data buses * Bootstrap loading from external data bus or Host Interface MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com iii Freescale Semiconductor, Inc. DSP56001A Product Documentation Freescale Semiconductor, Inc... Peripheral and Support Circuits * Byte-wide Host Interface (HI) with Direct Memory Access (DMA) support * Synchronous Serial Interface (SSI) to communicate with codecs and synchronous serial devices - 8-, 12-, 16-, and 24-bit word sizes - Up to 32 software-selectable time slots in Network mode * Serial Communication Interface (SCI) for full-duplex asynchronous communications * On-chip peripheral registers memory mapped in data memory space * Double-buffered peripherals * Up to twenty-four General Purpose I/O (GPIO) pins * Two external interrupt request pins Miscellaneous Features * Power-saving Wait and Stop modes * Fully static, HCMOS design for operating frequencies from 33 MHz down to 4 MHz * 88-pin Ceramic Pin Grid Array (PGA) package; 13 x 13 array * 132-pin Plastic Quad Flat Pack (PQFP) surface-mount package; 24 x 24 x 4 mm * 132-pin Ceramic Quad Flat Pack (CQFP) surface-mount package; 22 x 22 x 4 mm * 5 V power supply PRODUCT DOCUMENTATION The three documents listed in Table 1 are required for a complete description of the DSP56001A and are necessary to design properly with the part. Documentation is available from one of the following locations (see back cover for detailed information): iv * A local Motorola distributor * A Motorola semiconductor sales office * A Motorola Literature Distribution Center * The World Wide Web (WWW) DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Product Documentation Table 1 DSP56001A Documentation Freescale Semiconductor, Inc... Topic Description Order Number DSP56001 User's Manual Detailed description of the 56001 architecture, 24-bit DSP, memory, peripherals, and instruction set DSP56001UM/AD DSP56001A Data Sheet Pin and package descriptions, and electrical and timing specifications DSP56001A/D Related Documentation Table 2 lists additional documentation relevant to the DSP56001A. Table 2 DSP56001A Related Documentation Document Name Description Order Number Digital Sine-Wave Synthesis Application Report; uses the DSP56001 look-up table APR1/D Digital Stereo 10-band Graphic Equalizer Application Report; includes code and circuitry; features the DSP56001 APR2/D Fractional and Integer Arithmetic Application Report; includes code APR3/D Implementation of Fast Fourier Transforms Application Report; comprehensive FFT algorithms and code for DSP56001, DSP56156, and DSP96002 APR4/D Implementation of PID Controllers Application Report; PWM using the SCI timer and three phase output using modulo addressing APR5/D Convolutional Encoding and Viterbi Decoding with a V.32 Modem Trellis Example Application Report; theory and code; features the DSP56001 APR6/D Implementing IIR/FIR Filters Application Report; comprehensive example using the DSP56001 APR7/D Principles of Sigma-Delta Modulation for A-to-D Converters Application Report; features the DSP56ADC16; improving resolution with half-band filters APR8/D Full-Duplex 32-kbit/s CCITT ADPCM Speech Coding Application Report; features the DSP56001 APR9/D DSP56001 Interface Techniques and Examples Application Report; interfaces for pseudo Static RAM, Dynamic RAM, ISA bus, Host Interface APR11/D MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com v Freescale Semiconductor, Inc. DSP56001A Product Documentation Freescale Semiconductor, Inc... Table 2 DSP56001A Related Documentation (Continued) Document Name Description Twin CODEC Expansion Board for the DSP56000 ADS Application Report; circuit, code, FIR filter design for two voice band codecs connecting to the SSI APR12/D Conference Bridging in the Digital Telecommunications Environment Application Report; theory and code; features the DSP56001/002 APR14/D Implementation of Adaptive Controllers Application Report; adaptive control using reference models; generalized predictive control; includes code APR15/D Calculating Timing Requirements of External SRAM Application Report; determination of SRAM speed for optimum performance APR16/D Low Cost Controller for DSP56001 Application Report; circuit and code to connect two DSP56001s to an MC68008 APR402/D G.722 Audio Processing Application Report; theory and code using SB-ADPCM APR404/D Minimal Logic DRAM Interface Application Report; 1M x 480 ns DRAM, 1 PAL, code APR405/D Logarithmic/Linear Conversion Routines Application Report; -law and A-law companding routines for PCM monocircuits ANE408/D Third Party Compendium Brochures from companies selling hardware and software that supports Motorola DSPs DSP3RDPTYPAK/D University Support Program Flyer; Motorola's program supporting Universities in DSP research and education BR382/D Technical Training Schedule Technical Training Schedule BR348AD/D Audio Course Information Audio Course Information BR928/D Real Time Signal Processing Applications with Motorola's DSP56000 Family Textbook by Mohamed El-Sharkawy; 398+ pages. (This is a charge item.) Prentice-Hall, 1990; ISBN 0-13767138-5 vi DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com Order Number MOTOROLA Freescale Semiconductor, Inc. SECTION 1 SIGNAL/PIN DESCRIPTIONS Freescale Semiconductor, Inc... INTRODUCTION DSP56001A signals are organized into twelve functional groups as summarized in Table 1-1. Table 1-1 Signal Functional Group Allocations Number of Signals Detailed Description Power (VCCX) 5 Table 1-2 Ground (GNDX) 7 Table 1-3 Clock 2 Table 1-4 Address Bus 16 Table 1-5 24 Table 1-6 Bus Control 7 Table 1-7 Interrupt and Mode Control 3 Table 1-8 15 Table 1-9 3 Table 1-10 6 Table 1-11 Functional Group Port A1 Data Bus Port B2 Host Interface (HI) Port Serial Communications Interface (SCI) Port Port C3 Synchronous Serial Interface (SSI) Port Note: 1. 2. 3. Port A signals define the External Memory Interface port. Port B signals are GPIO signals multiplexed on the external pins also used with the HI signals. Port C signals are GPIO signals multiplexed on the external pins also used by the SCI and SSI ports. Figure 1-1 is a diagram of DSP56001A signals by functional group. MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 1-1 Freescale Semiconductor, Inc. DSP56001A Introduction DSP56001A Freescale Semiconductor, Inc... VCCCK VCCQ VCCA VCCD VCCC VCCH VCCS GNDCK GNDQ GNDA GNDD GNDC GNDH GNDS 4 3 3 2 4 5 6 4 2 EXTAL XTAL A0-A15 D0-D23 PS DS X/Y BR/WT BG/BS RD WR Note: 1. 2. 3. Power Inputs: Clock Output Internal Logic Address Bus Data Bus Bus Control HI SSI/SCI Grounds: Clock Internal Logic Address Bus Data Bus Bus Control HI SSI/SCI 24 Host Interface (HI) Port1 Interrupt mode IRQA IRQB Host Interface H0-H7 HA0-HA2 HR/W HEN HREQ HACK Port B GPIO PB0-PB7 PB8-PB10 PB11 PB12 PB13 PB14 SCI Port Port C GPIO PC0 PC1 PC2 RXD TXD RCLK SSI Port External Address Bus External Data Bus 8 3 Serial Communications Interface (SCI) Port2 Clock 16 Interrupt/ Mode Control Reset mode MODA MODB RESET Synchronous Serial Interface (SSI) Port2 3 SC0-SC2 SCK SRD STD Port C GPIO PC3-PC5 PC6 PC7 PC8 External Bus Control The Host Interface port signals are multiplexed with the Port B GPIO signals (PB0-PB15). The SCI and SSI signals are multiplexed with the Port C GPIO signals (PC0-PC8). Power and ground lines are indicated for the 144-pin TQFP package. AA0885 Figure 1-1 Signals Identified by Functional Group 1-2 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Power POWER Table 1-2 Power Connections Freescale Semiconductor, Inc... Power Names Description VCCQ (2) Internal Logic Power--These lines supply a quiet power source to the oscillator circuits and the mode control and interrupt lines. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the VCC power rail. Use a 0.1 F bypass capacitor located as close as possible to the chip package to connect between the VCCQ lines and the GNDQ lines. VCCA (3) Address Bus Power--These lines supply power to the address bus. VCCD (3) Data Bus Power--These lines supply power to the data bus. VCCC Bus Control Power--This line supplies power to the bus control logic. VCCH (2) Host Interface Power--These lines supply power to the Host Interface logic. VCCS Serial Interface Power--This line supplies power to the serial interface logic (SCI and SSI). GROUND Table 1-3 Ground Connections Ground Names Description GNDQ (2) Internal Logic Ground--These lines supply a quiet ground connection for the oscillator circuits and the mode control and interrupt lines. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 F bypass capacitor located as close as possible to the chip package to connect between the VCCQ line and the GNDQ line. GNDA (2) Address Bus Ground--These lines connect system ground to the address bus. GNDD (2) Data Bus Ground--These lines connect system ground to the data bus. GND (1) Host Interface Ground--These lines supply ground connections for the Host Interface logic. MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 1-3 Freescale Semiconductor, Inc. DSP56001A Clock CLOCK Table 1-4 Clock Signals Signal Name EXTAL Freescale Semiconductor, Inc... XTAL Signal Type State during Reset Input Input External Clock/Crystal Input--This input should be connected to an external crystal or to an external oscillator. Output Chipdriven Crystal Output--This output connects the internal crystal oscillator output to an external crystal. If an external oscillator is used, XTAL should be left unconnected. Signal Description ADDRESS BUS Table 1-5 Address Bus Signals Signal Names Signal Type A0-A15 Output State during Reset Tristated Signal Description Address Bus--These signals specify the address for external program and data memory accesses. If there is no external bus activity, A0-A15 remain at their previous values to reduce power consumption. A0-A15 are tri-stated when the bus grant signal is asserted. DATA BUS Table 1-6 Data Bus Signals Signal Names Signal Type D0-D23 Input/ Output 1-4 State during Reset Tristated Signal Description Data Bus--These signals provide the bidirectional data bus for external program and data memory accesses. D0-D23 are tri-stated when the BG or RESET signal is asserted. DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Bus Control BUS CONTROL Table 1-7 Bus Control Signals Freescale Semiconductor, Inc... Signal Name Signal Type State during Reset Signal Description PS Output Tri-stated Program Memory Select--PS is asserted low for external program memory access. PS is tri-stated when the BG or RESET signal is asserted. DS Output Tri-stated Data Memory Select--DS is asserted low for external data memory access. DS is tri-stated when the BG or RESET signal is asserted. X/Y Output Tri-stated X/Y External Memory Select--This output is driven low during external Y data memory accesses. It is also driven low during external exception vector fetches when operating in the Development mode. X/Y is tri-stated when the BG or RESET signal is asserted. BR Input/ Tri-stated Bus Request/Wait--The bus request input BR allows another device such Output as a processor or DMA controller to become master of the external data bus D0-D23 and external address bus a0-a15. When operating mode register (OMR) bit 7 is clear and BR is asserted, the DSP56001A will always release the external data bus D0-D23, address bus A0-A15, and bus control signals PS, DS, X/Y, RD, and WR (i.e. Port A), by tri-stating these pins after execution of the current instruction has been completed. WT If OMR bit 7 is set, this pin is an input that allows an external device to force wait states during an external Port A operation for as long as WT is asserted. Note: BG To prevent erroneous operation, pull up the BR/WT signal when it is not in use. Input/ Tri-stated Bus Grant/Bus Select--If OMR Bit 7 is clear, this output is asserted to Output acknowledge an external bus request after Port A has been released. BS If OMR Bit 7 is set, this signal is bus strobe, and is asserted when the DSP accesses Port A. WR Output Tri-stated Write Enable--WR is asserted during external memory write cycles. WR is tri-stated when the BG or RESET signal is asserted. RD Output Tri-stated Read Enable--RD is asserted during external memory read cycles. RD is tri-stated when the BG or RESET signal is asserted. MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 1-5 Freescale Semiconductor, Inc. DSP56001A Interrupt and Mode Control INTERRUPT AND MODE CONTROL Freescale Semiconductor, Inc... Table 1-8 Interrupt and Mode Control Signals Signal Name Signal Type State during Reset MODA Input Input Signal Description Mode Select A/External Interrupt Request A--This input has two functions: 1. to select the initial chip operating mode, and 2. IRQA after synchronization, to allow an external device to request a DSP interrupt. MODA is read and internally latched in the DSP on exit from Reset. MODA and MODB select the initial chip operating mode. After leaving the Reset state, the MODA signal changes to external interrupt request IRQA. The chip operating mode can be changed by software after reset. The IRQA input is a synchronized external interrupt request that indicates that an external device is requesting service. It may be programmed to be level-sensitive or negative-edge-triggered. If level-sensitive triggering is selected, an external pull up resistor is required for wired-OR operation. If the processor is in the Stop state and IRQA is asserted, the processor will exit the Stop state. MODB Input Input Mode Select B/External Interrupt Request B--This input has two functions: 1. to select the initial chip operating mode, and 2. IRQB after internal synchronization, to allow an external device to request a DSP interrupt. MODB is read and internally latched in the DSP on exit from Reset. MODA and MODB select the initial chip operating mode. After leaving the Reset state, the MODB signal changes to external interrupt request IRQB. After reset, the chip operating mode can be changed by software. The IRQB input is an external interrupt request that indicates that an external device is requesting service. It may be programmed to be level sensitive or negative-edgetriggered. If level-sensitive triggering is selected, an external pull up resistor is required for wired-OR operation. RESET 1-6 Input Input Reset--This input is a direct hardware reset on the processor. When RESET is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET signal is deasserted, the initial chip operating mode is latched from MODA and MODB. The internal reset signal is deasserted synchronously with the internal clocks. DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Interrupt and Mode Control CAUTION Freescale Semiconductor, Inc... DO NOT APPLY 10 VOLTS TO ANY PIN OF THE DSP56001A (including MODB)! Subjecting any pin of the DSP56001A to voltages in excess of the specified TTL/CMOS levels will permanently damage the device. MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 1-7 Freescale Semiconductor, Inc. DSP56001A Host Interface (HI) Port HOST INTERFACE (HI) PORT Table 1-9 HI Signals Freescale Semiconductor, Inc... Signal Name Signal Type H0-H7 Input/ Output PB0-PB7 Input or Output State during Reset Signal Description Tri-stated Host Data Bus (H0-H7)--This data bus transfers data between the host processor and the DSP56001A. When configured as a Host Interface port, the H0-H7 signals are tri-stated as long as HEN is deasserted. The signals are inputs unless HR/W is high and HEN is asserted, in which case H0-H7 become outputs, allowing the host processor to read the DSP56001A data. H0-H7 become outputs when HACK is asserted during HREQ assertion. Port B GPIO 0-7 (PB0-PB7)--These signals are GPIO signals (PB0- PB7) when the Host Interface is not selected. After reset, the default state for these signals is GPIO input. HA0-HA2 Input PB8-PB10 Input or Output Tri-stated Host Address 0 - Host Address 2 (HA0-HA2)--These inputs provide the address selection for each Host Interface register. Port B GPIO 8-10 (PB8-PB10)--These signals are GPIO signals (PB8- PB10) when the Host Interface is not selected. After reset, the default state for these signals is GPIO input. HR/W PB11 Input Input or Output Tri-stated Host Read/Write--This input selects the direction of data transfer for each host processor access. If HR/W is high and HEN is asserted, H0- H7 are outputs and DSP data is transferred to the host processor. If HR/W is low and HEN is asserted, H0-H7 are inputs and host data is transferred to the DSP. HR/W must be stable when HEN is asserted. Port B GPIO 11 (PB11)--This signal is a GPIO signal called PB11 when the Host Interface is not being used. After reset, the default state for this signal is GPIO input. 1-8 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Host Interface (HI) Port Table 1-9 HI Signals (Continued) Freescale Semiconductor, Inc... Signal Name Signal Type HEN Input PB12 Input or Output State during Reset Signal Description Tri-stated Host Enable--This input enables a data transfer on the host data bus. When HEN is asserted and HR/W is high, H0-H7 become outputs and the host processor may read DSP56001A data. When HEN is asserted and HR/W is low, H0-H7 become inputs. Host data is latched in the DSP on the rising edge of HEN. Normally, a chip select signal derived from host address decoding and an enable strobe are used to generate HEN. Port B GPIO 12 (PB12)--This signal is aGPIO signal called PB12 when the Host Interface is not being used. After reset, the default state for this signal is GPIO input. HREQ Open drain Output Tri-stated Host Request--This signal is used by the Host Interface to request service from the host processor, DMA controller, or a simple external controller. Note: HREQ should always be pulled high when it is not in use. PB13 Input or Output Port B GPIO 13 (PB13)--This signal is a GPIO (not open-drain) signal (PB13) when the Host Interface is not selected. After reset, the default state for this signal is GPIO input. HACK Input PB14 Tri-stated Host Acknowledge--This input has two functions. It provides a host acknowledge handshake signal for DMA transfers and it receives a host interrupt acknowledge compatible with MC68000 family processors. Note: Input or Output HACK should always be pulled high when it is not in use. Port B GPIO 14 (PB14)--This signal is a GPIO signal (PB14) when the Host Interface is not selected, and may be programmed as a GPIO signal when the Host Interface is selected. After reset, the default state for this signal is GPIO input. MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 1-9 Freescale Semiconductor, Inc. DSP56001A Serial Communications Interface Port SERIAL COMMUNICATIONS INTERFACE PORT Freescale Semiconductor, Inc... Table 1-10 Serial Communications Interface (SCI) Signals Signal Name Signal Type RXD Input PC0 Input or Output State during Reset Signal Description Tri-stated Receive Data (RXD)--This input receives byte-oriented data and transfers the data to the SCI receive shift register. Input data can be sampled on either the positive edge or on the negative edge of the receive clock, depending on how the SCI control register is programmed. Port C GPIO 0 (PC0)--This signal is a GPIO signal called PC0 when the SCI RXD function is not being used. After reset, the default state is GPIO input. TXD Output Tri-stated Transmit Data (TXD)--This output transmits serial data from the SCI transmit shift register. In the default configuration, the data changes on the positive clock edge and is valid on the negative clock edge. The user can reverse this clock polarity by programming the SCI control register appropriately. PC1 Input or Output Port C GPIO 1 (PC1)--This signal is a GPIO signal called PC1 when the SCI TXD function is not being used. After reset, the default state is GPIO input. SCLK Input/ Output PC2 Input or Output Tri-stated SCI Clock (SCLK)--This signal provides an input or output clock from which the transmit/receive baud rate is derived in the Asynchronous mode, and from which data is transferred in the Synchronous mode. The direction and function of the signal is defined by the RCM bit in the SCI Clock Control Register (SCCR). Port C GPIO 2 (PC2)--This signal is a GPIO signal called PC2 when the SCI TCLK function is not being used. After reset, the default state is GPIO input. 1-10 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Synchronous Serial Interface Port SYNCHRONOUS SERIAL INTERFACE PORT Table 1-11 Synchronous Serial Interface (SSI) Signals Signal Type Signal Name SC0 State during Reset Signal Description Input or Tri-stated Serial Clock 0 (SC0)--This signal's function is determined by Output whether the SCLK is in Synchronous or Asynchronous mode. Freescale Semiconductor, Inc... * PC3 Input or Output In Synchronous mode, this signal is used as a serial I/O flag. * In Asynchronous mode, this signal receives clock I/O. Port C GPIO 3 (PC3)--This signal is GPIO signal PC3 when not configured as SCI signal SC0. After reset, the default state is GPIO input. SC1 Input or Tri-stated Serial Clock 1 (SC1)--The SSI uses this bidirectional signal to Output control flag or frame synchronization. This signal's function is determined by whether the SCLK is in Synchronous or Asynchronous mode. * In Asynchronous mode, this signal is frame sync I/O. * For Synchronous mode with continuous clock, this signal is a serial I/O flag and operates like the SC0. SC0 and SC1 are independent serial I/O flags, but may be used together for multiple serial device selection. PC4 Input or Output Port C GPIO 4 (PC4)--This signal is GPIO signal PC4 when not configured as SSI function SC1. After reset, the default state is GPIO input. SC2 Input or Tri-stated Serial Clock 2 (SC2)--The SSI uses this bidirectional signal to Output control frame synchronization only. As with SC0 and SC1, its function is defined by the SSI operating mode. PC5 Input or Output Port C GPIO 5 (PC5)--This signal is GPIO signal PC5 when not configured as SSI function SC1. After reset, the default state is GPIO input. SCK Input or Tri-stated SSI Serial Receive Clock--This bidirectional signal provides the Output serial bit rate clock for the SSI when only one clock is being used. PC6 Input or Output Port C GPIO 6 (PC6)--This signal is GPIO signal PC6 when the SSI function is not being used. After reset, the default state is GPIO input. MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 1-11 Freescale Semiconductor, Inc. DSP56001A Synchronous Serial Interface Port Table 1-11 Synchronous Serial Interface (SSI) Signals (Continued) Signal Name Signal Type SRD Input PC7 Input or Output State during Reset Signal Description Tri-stated SSI Receive Data--This input signal receives serial data and transfers the data to the SSI Receive Shift Register. Port C GPIO 7 (PC7)--This signal is GPIO signal PC7 when the SSI SRD function is not being used. Freescale Semiconductor, Inc... After reset, the default state is GPIO input. STD Output Tri-stated SSI Transmit Data (STD)--This output signal transmits serial data from the SSI Transmitter Shift Register. PC8 Input or Output Port C GPIO 8 (PC8)--This signal is GPIO signal PC8 when the SSI STD function is not being used. After reset, the default state is GPIO input. 1-12 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 2 SPECIFICATIONS Freescale Semiconductor, Inc... GENERAL CHARACTERISTICS The DSP56001A is fabricated in high-density HCMOS with TTL compatible inputs and outputs. Table 2-1 Absolute Maximum Ratings (GND = 0 V) Rating Symbol Value Unit Supply Voltage VCC -0.3 to +7.0 V All Input Voltages VIN (GND - 0.5) to (VCC + 0.5) V I 10 mA Tstg -55 to +150 C Current Drain per Pin excluding VCC and GND Storage Temperature Note: This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Table 2-2 Recommended Operating Conditions Rating Supply Voltage Operating Temperature Range (See Note 1) Symbol Value Unit VCC 4.5 to 5.5 V TA -40 to +105 C Table 2-3 Thermal Characteristics for 88-pin PGA Package Thermal Resistance Symbol Value Rating Junction to Ambient (See Note 2) RJA 27 C/W Junction to Case (estimated) (See Note 3) RJC 6.5 C/W MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-1 Freescale Semiconductor, Inc. DSP56001A General Characteristics Table 2-4 Thermal Characteristics for 132-pin CQFP/PQFP Packages Thermal Resistance Symbol Value Rating Junction to Ambient RJA 40 (CQFP) 47 (PQFP) C/W Junction to Case (estimated) RJC 7.0 (CQFP) 13.0 (PQFP) C/W Freescale Semiconductor, Inc... Note: 1. 2. 3. 2-2 See discussion under Design Considerations, Heat Dissipation, page 4-1. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided Printed Circuit Board per SEMI G38-87 in natural convection. SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Road, Mountain View, CA 94043, (415) 964-5111. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88 with the exception that the cold plate temperature is used for the case temperature. DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A DC Electrical Characteristics DC ELECTRICAL CHARACTERISTICS Table 2-5 DC Electrical Characteristics Characteristics Symbol Min Typ Max Units VCC 4.5 4.75 5.0 5.0 5.5 5.25 V V Input High Voltage *EXTAL *RESET * MODA, MODB * All other inputs VIHC VIHR VIHM VIH 4.0 2.5 3.5 2.0 -- -- -- -- VCC VCC VCC VCC V V V V Input Low Voltage * EXTAL * MODA, MODB * All other inputs VILC VILM VIL -0.5 -0.5 -0.5 -- -- -- 0.6 2.0 0.8 V V V Input Leakage Current EXTAL, RESET, MODA/IRQA, MODB/IRQB, DR, BR/WT IIN -1 -- 1 A Tri-state (Off-state) Input Current (@ 2.4 V/0.4 V) ITSI -10 -- 10 A Output High Voltage (IOH = -0.4 mA) VOH 2.4 -- -- V Output Low Voltage (IOL = 1.6 mA) HREQ IOL = 6.7 mA, TXD IOL = 6.7 mA VOL -- -- 0.4 V Internal Supply Current at 33 MHz (Note 1) * In Wait mode (Note 2) * In Stop mode (Note 2) ICCI ICCW ICCS -- -- -- 80 10 2 115 25 2000 mA mA A Input Capacitance (Note 3) CIN -- 10 -- pF Freescale Semiconductor, Inc... Supply Voltage Note: 1. 2. 3. MOTOROLA 27 MHz 33 MHz Section 4 Design Considerations describes how to calculate the external supply current. In order to obtain these results all inputs must be terminated (i.e., not allowed to float). Periodically sampled and not 100% tested DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-3 Freescale Semiconductor, Inc. DSP56001A AC Electrical Characteristics AC ELECTRICAL CHARACTERISTICS Freescale Semiconductor, Inc... The timing waveforms in the AC Electrical Characteristics are tested with a VIL maximum of 0.5 V and a VIH minimum of 2.4 V for all pins, except EXTAL, RESET, MODA, and MODB. These pins are tested using the input levels set forth in the DC electrical characteristics. AC timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal's transition. DSP56001A output levels are measured with the production test machine VOL and VOH reference levels set at 0.8 V and 2.0 V, respectively. Pulse Width Low VIH Input Signal 90% 50% 10% Midpoint1 VIL Fall Time Note: High Rise Time The midpoint is VIL + (VIH - VIL)/2. AA0179 Figure 2-1 Signal Measurement Reference INTERNAL CLOCKS For each occurrence of TH, TL, TC or ICYC, substitute with the numbers in Table 2-6. Table 2-6 Internal Clocks Characteristics Symbol Internal Operation Frequency f Internal Clock High Period TH ETH Internal Clock Low Period TL ETL Internal Clock Cycle Time TC ETC ICYC 2 x TC Instruction Cycle Time 2-4 Expression DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A External Clock (EXTAL Pin) EXTERNAL CLOCK (EXTAL PIN) The DSP56001A system clock may be derived from the on-chip crystal oscillator as shown in Figure 2-2, or it may be externally supplied. An externally supplied square wave voltage source should be connected to EXTAL, leaving XTAL physically unconnected to the board or socket. The rise and fall times of this external clock should be 4 ns maximum. XTAL EXTAL EXTAL XTAL R R1 R2 Freescale Semiconductor, Inc... C3 XTAL1 C C C2 Fundamental Frequency Crystal Oscillator C3 3rd Overtone Crystal Oscillator Suggested Component Values R = 680 k 10% C = 20 pf 20% Note: XTAL11 L1 Suggested Component Values R1 = 470 k 10% R2 = 330 10% C1 = 0.1 f 20% C2 = 26 pf 20% C3 = 20 pf 10% L1 = 2.37 H 10% XTAL = 33 MHz, AT cut, 20 pf load, 50 max series resistance 1. The suggested crystal source is ICM, # 433163 - 4.00 (4 MHz fundamental, 20 pf load) or # 436163 - 30.00 (30 MHz fundamental, 20 pf load) 2. To reduce system cost, a ceramic resonator may be used instead of the crystal. Suggested source: Murata-Erie #CST4.00MGW040 (4 MHz with built-in load capacitors) Note: 1. 3rd overtone crystal 2. The suggested crystal source is ICM, # 471163 - 33.00 (33 MHz 3rd overtone, 20 pf load) 3. R2 limits crystal current 4. Reference Benjamin Parzen, The Design of Crystal and Other Harmonic Oscillators, John Wiley & Sons, 1983 AA0886 Figure 2-2 Crystal Oscillator Circuits MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-5 Freescale Semiconductor, Inc. DSP56001A External Clock (EXTAL Pin) VILC Midpoint VIHC EXTAL ETH ETL 1 2 3 ETC Freescale Semiconductor, Inc... 4 NOTE: The midpoint is VILC + 0.5 (VIHC - VILC). AA0360 Figure 2-3 External Clock Timing Table 2-7 Clock Operation 27 MHz No Characteristics Frequency of Operation (EXTAL Pin) Unit Min Max Min Max Ef 4 27 4 33 MHz 1 Clock Input High (46.7% - 53.3% duty cycle) ETH 17 150 13.5 150 ns 2 Clock Input Low (46.7% - 53.3% duty cycle) ETL 17 150 13.5 150 ns 3 Clock Cycle Time ETC 37 250 30 250 ns 4 Instruction Cycle Time = ICYC = 2 x TC ICYC 74 500 60 500 ns Note: 2-6 33 MHz Symbol External Clock Input High and External Clock Input Low are reserved at 50% of the input transition. DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A RESET, Stop, Mode Select, and Interrupt Timing RESET, STOP, MODE SELECT, AND INTERRUPT TIMING VCC = 5.0 V 10% for 27 MHz; VCC = 5.0 V 5% for 33 MHz TJ = -40 to +105 C; CL = 50 pF + 1 TTL loads WS = number of wait states programmed into the external bus access using BCR (WS = 0-15) Table 2-8 Reset, Stop, Mode Select, and Interrupt Timing (27/33 MHz) 27 MHz Freescale Semiconductor, Inc... Num 33 MHz Characteristics Unit Min Max Min Max -- 38 -- 31 ns 75000 x TC 25 x TC -- -- 75000 x TC 25 x TC -- -- ns ns 8 x TC 9 x TC + 31 8 x TC 9 x TC + 25 ns 15 TC - 8 13 TC - 7 ns 8 x TC + 5 8 x TC + 23 8 x TC + 5 8 x TC + 19 ns 14 Mode Select Setup Time 77 -- 62 -- ns 15 Mode Select Hold Time 0 -- 0 -- ns 16 Minimum Edge-Triggered Interrupt Request Assertion Width 17 -- 16 -- ns 16a Minimum Edge-Triggered Interrupt Request Deassertion Width 10 -- 10 -- ns 9 Delay from RESET Assertion to Address High Impedance (periodically sampled and not 100% tested) 10 Minimum Stabilization Duration * Internal Oscillator (See Note 1) * External clock (See Note 2) 11 Delay from Asynchronous RESET Deassertion to First External Address Output (Internal Reset Deassertion) 12 Synchronous Reset Setup Time from RESET Deassertion to first CKOUT transition 13 Synchronous Reset Delay Time from the first CKOUT transition to the First External Address Output MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-7 Freescale Semiconductor, Inc. DSP56001A RESET, Stop, Mode Select, and Interrupt Timing Table 2-8 Reset, Stop, Mode Select, and Interrupt Timing (27/33 MHz) (Continued) 27 MHz Num Unit Freescale Semiconductor, Inc... 17 Delay from IRQA, IRQB Assertion to External Memory Access Address Out Valid * Caused by First Interrupt Instruction Fetch * Caused by First Interrupt Instruction Execution 18 Delay from IRQA, IRQB Assertion to General Purpose Transfer Output Valid caused by First Interrupt Instruction Execution 19 Delay from Address Output Valid caused by First Interrupt Instruction Execute to Interrupt Request Deassertion for LevelSensitive Fast Interrupts (See Note 3) 20 Delay from RD Assertion to Interrupt Request Deassertion for Level-Sensitive Fast Interrupts (See Note 3) 21 Delay from WR Assertion to Interrupt Request Deassertion for Level-Sensitive Fast Interrupts (See Note 3) * WS = 0 * 2-8 33 MHz Characteristics WS > 0 Min Max Min Max 5 x TC + TH -- 5 x TC + TH -- ns 9 x TC + TH -- 9 x TC + TH -- ns 11 x TC + TH -- 11 x TC + TH -- ns -- 2 x TC + TL + (TC x WS) - 34 -- 2 x TC + TL + (TC x WS) - 27 ns -- 2 x TC + (TC x WS) - 31 -- 2 x TC + (TC x WS) - 25 ns -- 2 x TC - 31 -- 2 x TC - 25 ns -- TC + TL + (TC x WS) - 31 -- TC + TL + (TC x WS) - 25 ns DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A RESET, Stop, Mode Select, and Interrupt Timing Table 2-8 Reset, Stop, Mode Select, and Interrupt Timing (27/33 MHz) (Continued) 27 MHz Freescale Semiconductor, Inc... Num 33 MHz Characteristics Unit 22 Delay from General-Purpose Output Valid to Interrupt Request Deassertion for LevelSensitive Fast Interrupts (See Note 3)--If Second Interrupt Instruction is: * Single Cycle * Two Cycles 23 Synchronous Interrupt Setup Time from IRQA, IRQB Assertion to the second CKOUT transition 24 Synchronous Interrupt Delay Time from the second CKOUT transition to the First External Address Output Valid caused by the First Instruction Fetch after coming out of Wait State 25 Duration for IRQA Assertion to Recover from Stop State 26 Delay from IRQA Assertion to Fetch of First Interrupt Instruction (when exiting `Stop') (See Note 1) * Internal Crystal Oscillator Clock, OMR Bit 6 = 0 * Stable External Clock, OMR Bit 6 = 1 27 Duration of Level-Sensitive IRQA Assertion to ensure interrupt service (when exiting `Stop') (See Note 1) * Internal Crystal Oscillator Clock, OMR Bit 6 = 0 * Stable External Clock, OMR Bit 6 = 1 MOTOROLA Min Max Min Max -- TL - 46 -- TL - 37 ns -- 2 x TC + TL - 46 -- 2 x TC + TL - 37 ns 19 TC - 8 16 TC - 6 ns 13 x TC + TH + 6 13 x TC + TH + 23 13 x TC + TH + 5 13 x TC + TH + 19 ns 19 -- 16 -- ns 65548 x TC -- 65548 x TC -- ns -- ns 20 x TC -- 20 x TC 65534 x TC + TL -- 65534 x TC + TL -- ns 6 x TC + TL -- 6 x TC + TL -- ns DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-9 Freescale Semiconductor, Inc. DSP56001A RESET, Stop, Mode Select, and Interrupt Timing Table 2-8 Reset, Stop, Mode Select, and Interrupt Timing (27/33 MHz) (Continued) 27 MHz Freescale Semiconductor, Inc... Num Unit 28 Delay from Level-Sensitive IRQA Assertion to Fetch of First Interrupt Instruction (when exiting `Stop') (See Note 1) * Internal Crystal Oscillator Clock, OMR Bit 6 = 0 * Stable External Clock, OMR Bit 6 = 1 Note: 1. 2. 3. 2-10 33 MHz Characteristics Min Max Min Max 65548 x TC -- 65548 x TC -- ns 20 x TC -- 20 x TC -- ns A clock stabilization delay is required when using the on-chip crystal oscillator in two cases: * after power-on reset, and * when recovering from Stop mode. During this stabilization period, TC, TH, and TL will not be constant. Since this stabilization period varies, a delay of 75,000 x TC is typically allowed to assure that the oscillator is stable before executing programs. While it is possible to set OMR Bit 6 = 1 when using the internal crystal oscillator, it is not recommended and these specifications do not guaraantee timings for that case. Circuit stabilization delay is required during reset when using an external clock in two cases: * after power-on reset, and * when recovering from Stop mode. When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19 through 22 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-Triggered mode is recommended when using fast interrupt. Long interrupts are recommended when using Level-Sensitive mode. DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A RESET, Stop, Mode Select, and Interrupt Timing VIHR RESET 10 11 9 A0-A15 First Fetch AA0356 Freescale Semiconductor, Inc... Figure 2-4 Reset Timing EXTAL 12 RESET 13 A0-A15, DS, PS, X/Y AA0887 Figure 2-5 Synchronous Reset Timing VIHR RESET 14 VIHM MODA, MODB VILM 15 VIH VIL IRQA, IRQB AA0888 Figure 2-6 Operating Mode Select Timing MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-11 Freescale Semiconductor, Inc. DSP56001A RESET, Stop, Mode Select, and Interrupt Timing First Interrupt Instruction Execution/Fetch A0-A15 RD 20 WR Freescale Semiconductor, Inc... 21 IRQA, IRQB 17 19 a) First Interrupt Instruction Execution General Purpose I/O 18 22 IRQA, IRQB b) General Purpose I/O AA0889 Figure 2-7 External Level-Sensitive Fast Interrupt Timing IRQA, IRQB 16 IRQA, IRQB 16A AA0890 Figure 2-8 External Interrupt Timing (Negative Edge-Triggered) 2-12 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A RESET, Stop, Mode Select, and Interrupt Timing T0, T2 CKOUT T1, T3 23 IRQA, IRQB 24 A0-A15, DS, PS, X/Y Freescale Semiconductor, Inc... AA0891 Figure 2-9 Synchronous Interrupt from Wait State Timing 25 IRQA 26 A0-A15, DS, PS, X/Y First Instruction Fetch AA0363 Figure 2-10 Recovery from Stop State Using IRQA 27 IRQA 28 A0-A15, DS, PS, X/Y First IRQA Interrupt Instruction Fetch AA0364 Figure 2-11 Recovery from Stop State Using IRQA Interrupt Service MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-13 Freescale Semiconductor, Inc. DSP56001A Host I/O (HI) Timing HOST I/O (HI) TIMING VCC = 5.0 V 10% for 27 MHz; 5.0 V 5% for 33 MHz; TJ =-40 to 105 C; CL = 50 pF + 1 TTL loads Note: Active low lines should be pulled up in a manner consistent with the AC and DC specifications. Table 2-9 Host I/O Timing (27/33 MHz) Freescale Semiconductor, Inc... 27 MHz Num 33 MHz Characteristics Min Max Min Max Unit TL TC + TL TL TC + TL ns TC + 46 -- TC + 37 -- ns 39 19 -- -- 31 16 -- -- ns ns 19 -- 16 -- ns 2 x TC + 46 -- 2 x TC + 37 -- ns 2 x TC + 46 -- 2 x TC + 37 -- ns 4 -- 4 -- ns 4 -- 4 -- ns 0 -- 0 -- ns -- 39 -- 31 ns 37 HEN/HACK Deassertion to Output Data High Impedance (See Note 6) -- 27 -- 22 ns 38 Output Data Hold Time After HEN/HACK Deassertion (See Note 7) 4 -- 4 -- ns 30 Host Synchronization Delay (see Note 1) 31 HEN/HACK Assertion Width (See Note 2) * CVR, ICR, ISR, RXL Read * IVR, RXH/M Read * Write 32 HEN/HACK Deassertion Width (See Note 2) * Between Two TXL Writes (See Note 3) * Between Two CVR, ICR, ISR, RXL Reads (See Note 4) 33 Host Data Input Setup Time Before HEN/HACK Deassertion 34 Host Data Input Hold Time After HEN/HACK Deassertion 35 HEN/HACK Assertion to Output Data Active from High Impedance 36 HEN/HACK Assertion to Output Data Valid 2-14 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Host I/O (HI) Timing Table 2-9 Host I/O Timing (Continued)(27/33 MHz) (Continued) 27 MHz Freescale Semiconductor, Inc... Num 33 MHz Characteristics Min Max Min Max Unit 39 HR/W Low Setup Time Before HEN Assertion 0 -- 0 -- ns 40 HR/W Low Hold Time After HEN Deassertion 4 -- 4 -- ns 41 HR/W High Setup Time to HEN Assertion 0 -- 0 -- ns 42 HR/W High Hold Time After HEN/HACK Deassertion 4 -- 4 -- ns 43 HA0-HA2 Setup Time Before HEN Assertion 0 -- 0 -- ns 44 HA0-HA2 Hold Time After HEN Deassertion 4 -- 4 -- ns 45 DMA HACK Assertion to HREQ Deassertion (See Note 5) 4 46 4 46 ns -- tHSDL + TC + TH + 4 tHSDL + TC + 4 4 -- ns -- ns -- ns 46 DMA HACK Deassertion to HREQ Assertion (See Notes 5, 6) * for DMA RXL Read tHSDL + TC + TH + 4 * for DMA TXL Write tHSDL + TC + 4 * all other cases 4 -- -- 47 Delay from HEN Deassertion to tHSDL + TC + HREQ Assertion for RXL Read TH + 4 (See Notes 5, 6) -- tHSDL + TC + TH + 4 -- ns 48 Delay from HEN Deassertion to tHSDL + TC + HREQ Assertion for TXL Write 4 (See Notes 5, 6) -- tHSDL + TC + 4 -- ns 70 4 65 ns 49 Delay from HEN Assertion to HREQDeassertion for RXL Read, TXL Write (See Notes 5, 6) Note: 1. 2. 3. 4. 5. 6. 7. 4 Host synchronization delay (tHSDL) is the time period required for the DSP56001 to sample any external asynchronous input signal, determine whether it is high or low, and synchronize it to the DSP56001 internal clock. See Host Port Considerations in the section on Design Considerations. This timing must be adhered to only if two consecutive writes to the TXL are executed without polling TXDE or HREQ. This timing must be adhered to only if two consecutive reads from one of these registers are executed without polling the corresponding status bits or HREQ. HREQ is pulled up by a 1 k resistor. Specifications are periodically sampled and not 100% tested. May decrease to 0 ns for future versions. MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-15 Freescale Semiconductor, Inc. DSP56001A Host I/O (HI) Timing HREQ (Output) 31 32 HACK (Input) 41 42 Freescale Semiconductor, Inc... HR/W (Input) 36 37 38 35 H0-H7 (Output) Data Valid AA0223 Figure 2-12 Host Interrupt Vector Register (IVR) Read HREQ (Output) 49 RXM Read RXH Read HEN (Input) RXL Read 32 31 43 HA2-HA0 (Input) 47 44 Address Valid Address Valid Address Valid 42 41 HR/W (Input) 36 37 35 H0-H7 (Output) 38 Data Valid Data Valid Data Valid AA0224 Figure 2-13 Host Read Cycle (Non-DMA Mode) 2-16 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Host I/O (HI) Timing HREQ (Output) 49 TXM Write TXH Write HEN (Input) 31 Freescale Semiconductor, Inc... TXL Write 32 43 HA2-HA0 (Input) 48 44 Address Valid Address Valid 39 Address Valid 40 HR/W (Input) 34 33 H0-H7 (Input) Data Valid Data Valid Data Valid AA0225 Figure 2-14 Host Write Cycle (Non-DMA Mode) HREQ (Output) 45 HEN (Input) 31 32 46 46 RXH Read RXM Read 36 46 RXL Read 37 35 38 H0-H7 (Output) Data Valid Data Valid Data Valid AA0230 Figure 2-15 Host DMA Read Cycle HREQ (Output) 45 HEN (Input) 31 32 46 46 TXH Write TXM Write 46 TXL Write 33 34 H0-H7 (Input) Data Valid Data Valid Data Valid AA0231 Figure 2-16 Host DMA Write Cycle MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-17 Freescale Semiconductor, Inc. DSP56001A Serial Communication Interface (SCI) Timing SERIAL COMMUNICATION INTERFACE (SCI) TIMING VCC = 5.0 V 10% for 27 MHz; 5.0 V 5% for 33 MHz; TJ =-40 to 105 C; CL = 50 pF + 1 TTL loads tSCC = Synchronous Clock Cycle Time (For internal clock, tSCC is determined by the SCI Clock Control Register and TC.) The minimum tSCC value is 8 x TC. Table 2-10 SCI Synchronous Mode Timing (27/33 MHz) 27 MHz Freescale Semiconductor, Inc... Num 33 MHz Characteristics Unit Min Max Min Max 8 x TC -- 8 x TC -- ns 55 Synchronous Clock Cycle--tSCC 56 Clock Low Period 4 x TC- 15 -- 4 x TC- 13 -- ns 57 Clock High Period 4 x TC- 15 -- 4 x TC- 13 -- ns 58 < intentionally blank > -- -- -- -- -- 59 Output Data Setup to Clock Falling Edge (Internal Clock) 2 x TC + TL - 39 -- 2 x TC + TL - 31 -- ns 60 Output Data Hold After Clock Rising Edge (Internal Clock) 2 x TC - TL - 11 -- 2 x TC - TL - 9 -- ns 61 Input Data Setup Time Before Clock Rising Edge (Internal Clock) 2 x TC + TL + 35 -- 2 x TC + TL + 28 -- ns 62 Input Data Not Valid Before Clock Rising Edge (Internal Clock) -- 2 x TC + TL - 8 -- 2 x TC + TL - 6 ns 63 Clock Falling Edge to Output Data Valid (External Clock) -- 48 -- 39 ns 64 Output Data Hold After Clock Rising Edge (External Clock) TC + 9 -- TC + 8 -- ns 65 Input Data Setup Time Before Clock Rising Edge (External Clock) 23 -- 19 -- ns 66 Input Data Hold Time After Clock Rising Edge (External Clock) 31 -- 25 -- ns 2-18 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Serial Communication Interface (SCI) Timing Table 2-11 SCI Asynchronous Mode Timing -- 1X Clock 27 MHz Freescale Semiconductor, Inc... Num 33 MHz Characteristics Unit Min Max Min Max 64 x TC -- 64 x TC -- ns 67 Asynchronous Clock Cycle-- tACC 68 Clock Low Period 32 x TC - 15 -- 32 x TC - 13 -- ns 69 Clock High Period 32 x TC - 15 -- 32 x TC - 13 -- ns 70 < intentionally blank > -- -- -- -- -- 71 Output Data Setup to Clock Rising Edge (Internal Clock) 32 x TC - 77 -- 32 x TC - 61 -- ns 72 Output Data Hold After Clock Rising Edge (Internal Clock) 32 x TC - 77 -- 32 x TC - 61 -- ns MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-19 Freescale Semiconductor, Inc. DSP56001A Serial Communication Interface (SCI) Timing 55 57 56 SCLK (Output) 59 60 TXD Data Valid 61 Freescale Semiconductor, Inc... 62 Data Valid RXD a) Internal Clock 55 57 56 SCLK (Input) 63 64 TXD Data Valid 65 66 RXD Data Valid b) External Clock AA0892 Figure 2-17 SCI Synchronous Mode Timing 67 69 68 1X SCLK (Output) 71 TXD Note: 72 Data Valid In the Wired-OR mode, TXD can be pulled up by 1 k. AA0893 Figure 2-18 SCI Asynchronous Mode Timing 2-20 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Synchronous Serial Interface (SSI) Timing Freescale Semiconductor, Inc... SYNCHRONOUS SERIAL INTERFACE (SSI) TIMING VCC = 5.0 V 10% for 27 MHz; VCC = 5.0 V 5% for 33 MHz; TJ = -40 to 105 C; CL = 50 pF + 2 TTL loads tSSICC = SSI clock cycle time TXC (SCK Pin) = Transmit Clock RXC (SC0 or SCK Pin) = Receive Clock FST (SC2 Pin) = Transmit Frame Sync FSR (SC1 or SC2 Pin) = Receive Frame Sync i ck = Internal Clock x ck = External Clock g ck = Gated Clock i ck a = Internal Clock, Asynchronous mode (Asynchronous implies that STD and SRD are two different clocks) i ck s = Internal Clock, Synchronous mode (Synchronous implies that STD and SRD are the same clock) bl = bit length wl = word length Table 2-12 SSI Timing 27 MHz Num 33 MHz Characteristics Case Unit Min Max Min Max 4 x TC -- 4 x TC -- -- ns 80 Clock Cycle--tSSICC (See Note 1) 81 Clock High Period 4 x TC - 15 -- 4 x TC - 13 -- -- ns 82 Clock Low Period 4 x TC - 15 -- 4 x TC - 13 -- -- ns 84 SRD Rising Edge to FSR Out (bl) High -- -- 61 38 -- -- 48 31 x ck i ck a ns ns 85 SRD Rising Edge to FSR Out (bl) Low -- -- 54 31 -- -- 43 25 xck i ck a ns ns 86 SRD Rising Edge to FSR Out (wl) High -- -- 54 31 -- -- 43 25 x ck i ck a ns ns 87 RXC Rising Edge to FSR Out (wl) Low -- -- 54 31 -- -- 43 25 x ck i ck a ns ns 88 Data In Setup Time Before RXC (SCK in Synchronous Mode) Falling Edge 12 27 -- -- 10 22 -- -- x ck i ck a ns ns 19 -- 16 -- i ck s ns MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-21 Freescale Semiconductor, Inc. DSP56001A Synchronous Serial Interface (SSI) Timing Table 2-12 SSI Timing (Continued) 27 MHz Freescale Semiconductor, Inc... Num 33 MHz Characteristics Min Max Min Max Case Unit 89 Data In Hold Time After RXC Falling Edge 27 4 -- -- 22 4 -- -- x ck i ck ns ns 90 FSR Input (bl) High Before RXC Falling Edge 12 27 -- -- 10 23 -- -- x ck i ck a ns ns 91 FSR Input (wl) High Before RXC Falling Edge 15 42 -- -- 13 34 -- -- x ck i ck a ns ns 92 FSR Input Hold Time After RXC Falling Edge 27 4 -- -- 22 4 -- -- x ck i ck ns ns 93 Flags Input Setup Before RXC Falling Edge 23 39 -- -- 19 31 -- -- x ck i ck s ns ns 94 Flags Input Hold Time After RXC Falling Edge 27 4 -- -- 22 4 -- -- x ck i ck s ns ns 95 TXC Rising Edge to FST Out (bl) High -- -- 54 23 -- -- 43 19 x ck i ck ns ns 96 TXC Rising Edge to FST Out (bl) Low -- -- 50 27 -- -- 40 22 x ck i ck ns ns 97 TXC Rising Edge to FST Out (wl) High -- -- 50 27 -- -- 40 22 x ck i ck ns ns 98 TXC Rising Edge to FST Out (wl) Low -- -- 50 27 -- -- 40 22 x ck i ck ns ns 99 TXC Rising Edge to Data Out Enable from High Impedance -- 50 31 -- 40 25 x ck i ck ns ns -- 50 31 -- 40 25 x ck i ck ns ns TXC Rising Edge to Data Out High Impedance (See Note 2) -- -- 54 31 -- -- 43 25 x ck i ck ns ns 101A TXC Falling Edge to Data Out High Impedance (See Note 2) -- TC + TH -- TC + TH g ck ns 100 101 2-22 TXC Rising Edge to Data Out Valid DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Synchronous Serial Interface (SSI) Timing Table 2-12 SSI Timing (Continued) 27 MHz Num Case Unit x ck i ck ns ns Min Max Min Max FST Input (bl) Setup Time Before TXC Falling Edge 12 27 -- 10 23 -- 103 FST Input (wl) to Data Out Enable from High Impedance -- 46 -- 37 104 FST Input (wl) Setup Time Before TXC Falling Edge 15 42 -- -- 13 34 -- -- x ck i ck ns ns 105 FST Input Hold Time After TXC Falling Edge 27 4 -- -- 22 4 -- -- x ck i ck ns ns 106 Flag Output Valid After TXC Rising Edge -- -- 54 31 -- -- 43 25 x ck i ck ns ns 102 Freescale Semiconductor, Inc... 33 MHz Characteristics Note: 1. 2. ns For internal clock, External Clock Cycle is defined by Icyc and SSI control register. Periodically sampled and not 100% tested MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-23 Freescale Semiconductor, Inc. DSP56001A Synchronous Serial Interface (SSI) Timing 80 81 82 TXC (Input/ Output) 95 96 FST (Bit) Out Freescale Semiconductor, Inc... 97 98 FST (Word) Out 100 101A 100 99 101 Data Out First Bit Last Bit 102 105 FST (Bit) In 103 104 105 FST (Word) In 106 See Note Flags Out Note: In the Network mode, output flag transitions can occur at the start of each time slot within the frame. In the Normal mode, the output flag state is asserted for the entire frame period. AA0894 Figure 2-19 SSI Transmitter Timing 2-24 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Synchronous Serial Interface (SSI) Timing 80 81 82 SRD (Input/Output) 84 85 FSR (Bit) Out Freescale Semiconductor, Inc... 86 87 FSR (Word) Out 88 Data Out 89 First Bit Last Bit 90 92 FSR (Bit) In 91 92 FSR (Word) In 93 94 See Note Flags Out Note: In the Network mode, output flag transitions can occur at the start of each time slot within the frame. In the Normal mode, the output flag state is asserted for the entire frame period. AA0895 Figure 2-20 SSI Receiver Timing MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-25 Freescale Semiconductor, Inc. DSP56001A External Bus Asynchronous Timing EXTERNAL BUS ASYNCHRONOUS TIMING Freescale Semiconductor, Inc... VCC = 5.0 V 10% for 27 MHz;VCC = 5.0 V 5% for 33 MHz; TJ = -40 to 105 C; CL = 50 pF + 1 TTL loads WS = Number of Wait States, as determined by BCR (WS = 0 to 15) Capacitance Derating: The DSP56001A external bus timing specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the external bus pins (A0-A15, D0-D23, PS, DS, RD, WR, X/Y) derates linearly at 1 ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins (HI, SCI, SSI) derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250 pF of loading. Active low lines should be pulled up in a manner consistent with the AC and DC specifications. Table 2-13 External Bus Asynchronous Timing 27 MHz No. Characteristics Unit 115 Delay from BR Assertion to BG Assertion * With no external access from the DSP Min Max Min Max 2 x TC + TH 4 x TC + TH + 15 2 x TC + TH 4 x TC + TH + 13 ns * During external read or write access TC + TH 4 x TC + TH + TC x WS + 15 TC + TH 4 x TC + TH + TC x WS + 13 ns * During external readmodify-write access TC + TH 6 x TC + TH + 2 x TC x WS + 15 TC + TH 6 x TC + TH + 2 x TC x WS + 13 ns * During Stop mode-- external bus will not be released and BG will not go low -- -- -- -- ns * During Wait mode TH + 3 TC + TH + 23 TH + 3 TC + TH + 19 ns 2 x TC 4 x TC + 15 2 x TC 4 x TC + 13 ns 2 x TC + TH - 8 -- 2 x TC + TH - 6 -- ns 0 -- 0 -- ns 116 Delay from BR Deassertion to BG Deassertion 117 BG Deassertion Duration 118 Delay from Address, Data, and Control Bus High Impedance to BG Assertion 2-26 33 MHz DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A External Bus Asynchronous Timing Table 2-13 External Bus Asynchronous Timing (Continued) 27 MHz No. Unit Min Max Min Max 0 TH-8 0 TH-6 ns TL - 7 TL + 5 TL - 5.5 TL + 5 ns TC - 7 TC + 5 TC - 5.5 TC + 5 ns TC - 7 -- TC - 5 -- ns WS > 0 WS x TC + TL -7 -- WS x TC + TL -5 -- ns 122 WR Deassertion to Address Not Valid TH - 9 -- TH - 7.5 -- ns TH - 7 TH + 8 TH - 5.5 TH + 6.5 ns 0 8 0 6.5 ns TH - 7 TH + 6 TH - 5.5 TH + 4.5 ns TL - 5 -- TL - 5 -- ns WS x TC + TL -5 -- WS x TC + TL -5 -- ns TH - 7 -- TH - 5.5 -- ns TC + TL - 6 -- TC + TL - 6 -- ns (WS + 1) x TC + TL - 6 (WS + 1) x TC + TL - 6 -- ns -- 119 Delay from BG Deassertion to Address and Control Bus Enabled 120 Address Valid to WR Assertion * WS = 0 Freescale Semiconductor, Inc... 33 MHz Characteristics * WS > 0 121 WR Assertion Width * WS = 0 * 123 WR Assertion to Data Out Active From High Impedance * WS = 0 * WS > 0 124 Data Out Hold Time from WR Deassertion (the maximum specification is periodically sampled, and not 100% tested) 125 Data Out Setup Time to WR Deassertion * WS = 0 * WS > 0 126 RD Deassertion to Address Not Valid 127 Address Valid to RD Deassertion * WS = 0 * WS > 0 MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-27 Freescale Semiconductor, Inc. DSP56001A External Bus Asynchronous Timing Table 2-13 External Bus Asynchronous Timing (Continued) 27 MHz No. Unit Min Max Min Max 0 -- 0 -- ns TC - 7 -- TC - 5.5 -- ns (WS + 1) x TC -7 -- (WS + 1) x TC - 5.5 -- ns -- TC + TL - 14 -- TC + TL - 11 ns -- (WS + 1) x TC + TL - 14 -- (WS + 1) x TC + TL - 11 ns TL - 7 TL + 5 TL - 5.5 TL + 5 ns -- TC - 11 -- TC - 9 ns -- (WS + 1) x TC - 11 -- (WS + 1) x TC -9 ns 133 WR Deassertion to RD Assertion TC - 12 -- TC - 10 -- ns 134 RD Deassertion to RD Assertion TC - 8 -- TC - 6.5 -- ns 135 WR Deassertion to WR Assertion * WS = 0 TC - 12 -- TC - 10 -- ns TC + TH - 12 -- TC + TH - 10 -- ns TC - 8 -- TC - 6.5 -- ns TC + TH - 8 -- TC + TH - 6.5 -- ns 128 Input Data Hold Time to RD Deassertion 129 RD Assertion Width * WS = 0 * Freescale Semiconductor, Inc... 33 MHz Characteristics WS > 0 130 Address Valid to Input Data Valid * WS = 0 * WS > 0 131 Address Valid to RD Assertion 132 RD Assertion to Input Data Valid * WS = 0 * * WS > 0 WS > 0 136 RD Deassertion to WR Assertion * WS = 0 * 2-28 WS > 0 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A External Bus Asynchronous Timing BR 115 116 BG 117 119 Freescale Semiconductor, Inc... 118 A0-A15, PS DS, X/Y, RD, WR D0-D23 AA0896 Figure 2-21 Bus Request / Bus Grant Timing A0-A15, DS, PS, X/Y (See Note) 126 127 131 129 134 RD (See Note) 120 135 122 121 133 136 WR 132 123 130 125 D0-D23 Note: 128 124 Data Out Data In During Read-Modify-Write instructions, the address lines do not change state. AA0393 Figure 2-22 External Bus Asynchronous Timing MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-29 Freescale Semiconductor, Inc. DSP56001A External Bus Synchronous Timing EXTERNAL BUS SYNCHRONOUS TIMING VCC = 5.0 V 10% for 27 MHz, VCC = 5.0 Vdc 5% for 33 MHz, TJ = -40 to +105 C, CL = 50 pF + 1 TTL loads Freescale Semiconductor, Inc... Capacitance Derating: The DSP56001A external bus timing specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the external bus pins (A0-A15, D0-D23, PS, DS, RD, WR, X/Y) derates linearly at 1 ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins (HI, SCI, SSI) derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250 pF of loading. Active-low lines should be pulled up in a manner consistent with the AC and DC specifications. Table 2-14 External Bus Synchronous Timing 27 MHz Num 33 MHz Characteristics Unit 140 Clk Low transition to Address Valid 141 Clk High transition to WR Assertion(See Note 1, 2) * WS=0 * WS>0 Min Max Min Max -- 19 -- 19 ns 0 17 0 17 ns 0 TH + 17 0 TH + 17 ns 142 Clk High transition to WR Deassertion 5 16 5 13 ns 143 Clk High transition to RD Assertion 0 16 0 16 ns 144 Clk High transition to RD Deassertion 3 13 3 10.5 ns 145 Clk Low transition to DataOut Valid -- 19 -- 19 ns 146 Clk Low transition to DataOut Invalid (See Note 3) 4 -- 3.5 -- ns 147 Data-In Valid to Clk High transition (Setup) 4 -- 4 -- ns 148 Clk High transition to Data-In Invalid (Hold) 12 -- 12 -- ns 149 Clk Low transition to Address Invalid (See Note 3) 2 -- 2 -- ns 2-30 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A External Bus Synchronous Timing Table 2-14 External Bus Synchronous Timing (Continued) 27 MHz Num Unit Min Note: 1. 2. 3. 4. Freescale Semiconductor, Inc... 33 MHz Characteristics Max Min Max AC timing specifications which are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal's transition. WS are wait state values specified in the BCR. Clk Low transition to data-out invalid (specification # T146) and Clk Low transition to address invalid (specification # T149) indicate the time after which data/address are no longer guaranteed to be valid. Timings are given from Clk midpoint to VOL or VOH of the corresponding signal(s). T0 T1 T2 T3 T0 T1 T2 T3 T0 CKOUT A0-A15, DS, PS, X/Y 140 143 144 149 RD 141 142 WR 147 D0-D23 Data Out 145 Note: 148 Data In 146 During Read-Modify-Write Instructions, the address lines do not change states. AA0395 Figure 2-23 Synchronous Bus Timing MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-31 Freescale Semiconductor, Inc. DSP56001A Bus Strobe / Wait Timing BUS STROBE / WAIT TIMING VCC = 5.0 V 10% for 27 MHz; VCC = 5.0 V 5% for 33 MHz; TJ = -40 to 105 C; CL = 50 pF + 2 TTL loads Table 2-15 Bus Strobe / Wait Timing 27 MHz Freescale Semiconductor, Inc... No. 33 MHz Characteristics Unit Min Max Min Max 150 First CKOUT transition to BS Assertion 3 19 2.5 19 ns 151 WT Assertion to first CKOUT transition (setup time) 3 -- 2.5 -- ns 152 First CKOUT transition to WT Deassertion for Minimum Timing 11 TC - 6 12 TC - 5 ns 153 WT Deassertion to first CKOUT transition for Maximum Timing (2 wait states) 6 -- 5 -- ns 154 Second CKOUT transition to BS Deassertion 3 20 3 19 ns 155 BS Assertion to Address Valid -2 8 -2 6.5 ns 156 BS Assertion to WT Assertion (See Note 1) 0 TC - 11 0 TC - 10 ns TC 2 x TC - 11 TC + 4 2 x TC - 10 ns 157 BS Assertion to WT Deassertion (See Note 1 and Note 3) * WS < 2 * (WS - 1) x TC WS x TC - 11 (WS - 1) x TC WS x TC - 10 +4 WS > 2 ns TC + TL 2 x TC + TL + 17 TC + TL 2 x TC + TL + 15 ns 159 Minimum BS Deassertion Width for Consecutive External Accesses TH - 6 -- TH - 4.5 -- ns 160 BS Deassertion to Address Invalid (See Note 2) TH - 8 TH - 6.5 -- ns 158 WT Deassertion to BS Deassertion 2-32 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Bus Strobe / Wait Timing Table 2-15 Bus Strobe / Wait Timing (Continued) 27 MHz No. Unit 161 Data-In Valid to RD Deassertion (Set Up) Note: 1. 2. Freescale Semiconductor, Inc... 33 MHz Characteristics 3. 4. Min Max Min Max 12 -- 10 -- ns If wait states are also inserted using the BCR and if the number of wait states is greater than two, then specification numbers T156 and T157 can be increased accordingly. BS deassertion to address invalid indicates the time after which the address are no longer guaranteed to be valid. The minimum number of wait states when using BS/WT is two (2). For read-modify-write instructions, the address lines will not change states between the read and the write cycle. However, BS will deassert before asserting again for the write cycle. If wait states are desired for each of the read and write cycle, the WT pin must be asserted once for each cycle. A0-A15, PS, DS, X/Y 155 160 BS 157 159 156 158 WT 131 126 RD 161 128 D0-D23 Data In 120 122 WR 123 D0-D23 Note: 125 124 Data Out During Read-Modify-Write instructions, the address lines do not change state. However, BS will deassert before asserting again for the write cycle. AA0398 Figure 2-24 Asynchronous BS / WT Timings MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 2-33 Freescale Semiconductor, Inc. DSP56001A Bus Strobe / Wait Timing T0 T1 T2 Tw T2 Tw T2 T3 T0 CKOUT 140 149 A0-A15, PS, DS, X/Y 150 154 BS Freescale Semiconductor, Inc... 152 151 153 WT 143 144 RD 147 148 Data In D0-D23 141 142 WR 145 D0-D23 Note: 146 Data Out During Read-Modify-Write Instructions, the address lines do not change state. However, BS will deassert before asserting again for the write cycle. AA0397 Figure 2-25 Synchronous BS / WT Timings 2-34 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 3 PACKAGING Freescale Semiconductor, Inc... PIN-OUT AND PACKAGE INFORMATION This section supplies information about the packages which are available for this product. Diagrams of the pinouts of each package are included, and tables describing the pins allocated to each of the signals described in Table 3-1 through Table 3-5. The DSP56001A is available in 3 packages: * 132-pin plastic quad flat pack (PQFP), type `FC' * 132-pin ceramic quad flat pack (CQFP), type `FE' * 88-pin Pin Grid Array (PGA), type `RC' Top and bottom views of the each package are shown, together with their pin-outs. MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 3-1 Freescale Semiconductor, Inc. DSP56001A 117 1 18 Orientation Mark (chamfered edge) (Top View) 84 51 nc H3/PB3 H2/PB2 nc H1/PB1 GNDH GNDH H0/PB0 nc RXD/PC0 TXD/PC1 SCLK/PC2 nc SC0/PC3 SCK/PC6 GNDQ GNDQ VCCQ VCCQ SC2/PC5 nc STD/PC8 SC1/PC4 nc SRD/PC7 BG/BS nc BR/WT WR RD X/Y DS nc nc D20 D19 D18 GNDD GNDD nc D17 D16 nc D15 D14 D13 nc D12 VCCD VCCD D11 nc D10 D9 nc D8 D7 D6 GNDD GNDD nc D5 D4 D3 D2 nc nc PS A0 A1 GNDN GNDN A2 A3 nc A4 A5 nc VCCN VCCN A6 nc A7 A8 nc A9 A10 nc GNDN GNDN A11 A12 A13 nc A14 A15 D0 D1 nc Freescale Semiconductor, Inc... nc H4/PB4 H5/PB5 H6/PB6 VCCH VCCH H7/PB7 HREQ/PB13 HR/W/PB11 HEN/PB12 nc HACK/PB14 HA0/PB8 nc nc HA1/PB9 HA2/PB10 nc GNDQ GNDQ VCCQ VCCQ EXTAL XTAL nc RESET MODA/IRQA nc MODB/IRQB D23 D22 D21 nc Pin-out and Package Information Note: 1. "nc" are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 3. To simplify locating the pins, each fifth pin is shaded in the illustration. AA0898 Figure 3-1 Top View of the 132-pin Plastic (FC) Quad Flat Package 3-2 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A 18 1 117 Orientation Mark (chamfered edge on Top side) (Bottom View) 84 51 nc PS A0 A1 GNDN GNDN A2 A3 nc A4 A5 nc VCCN VCCN A6 nc A7 A8 nc A9 A10 nc GNDN GNDN A11 A12 A13 nc A14 A15 D0 D1 nc nc H3/PB3 H2/PB2 nc H1/PB1 GNDH GNDH H0/PB0 nc RXD/PC0 TXD/PC1 SCLK/PC2 nc SC0/PC3 SCK/PC6 GNDQ GNDQ VCCQ VCCQ SC2/PC5 nc STD/PC8 SC1/PC4 nc SRD/PC7 BG/BS nc BR/WT WR RD X/Y DS nc nc D2 D3 D4 D5 nc GNDD GNDD D6 D7 D8 nc D9 D10 nc D11 VCCD VCCD D12 nc D13 D14 D15 nc D16 D17 nc GNDD GNDD D18 D19 D20 nc Freescale Semiconductor, Inc... nc D21 D22 D23 MODB/IRQB nc MODA/IRQA RESET nc XTAL EXTAL VCCQ VCCQ GNDQ GNDQ nc HA2/PB10 HA1/PB9 nc nc HA0/PB8 HACK/PB14 nc HEN/PB12 HR/W/PB11 HREQ/PB13 H7/PB7 VCCH VCCH H6/PB6 H5/PB5 H4/PB4 nc Pin-out and Package Information Note: 1. "nc" are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 3. To simplify locating the pins, each fifth pin is shaded in the illustration. AA0899 Figure 3-2 Bottom View of the 132-pin Plastic (FC) Quad Flat Package MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 3-3 Freescale Semiconductor, Inc. DSP56001A 117 1 18 Orientation Mark (Top View) 84 51 nc H3/PB3 H2/PB2 nc H1/PB1 GNDH GNDH H0/PB0 nc RXD/PC0 TXD/PC1 SCLK/PC2 nc SC0/PC3 SCK/PC6 GNDQ GNDQ VCCQ VCCQ SC2/PC5 nc STD/PC8 SC1/PC4 nc SRD/PC7 BG/BS nc BR/WT WR RD X/Y DS nc nc D20 D19 D18 GNDD GNDD nc D17 D16 nc D15 D14 D13 nc D12 VCCD VCCD D11 nc D10 D9 nc D8 D7 D6 GNDD GNDD nc D5 D4 D3 D2 nc nc PS A0 A1 GNDN GNDN A2 A3 nc A4 A5 nc VCCN VCCN A6 nc A7 A8 nc A9 A10 nc GNDN GNDN A11 A12 A13 nc A14 A15 D0 D1 nc Freescale Semiconductor, Inc... nc H4/PB4 H5/PB5 H6/PB6 VCCH VCCH H7/PB7 HREQ/PB13 HR/W/PB11 HEN/PB12 nc HACK/PB14 HA0/PB8 nc nc HA1/PB9 HA2/PB10 nc GNDQ GNDQ VCCQ VCCQ EXTAL XTAL nc RESET MODA/IRQA nc MODB/IRQB D23 D22 D21 nc Pin-out and Package Information Note: 1. "nc" are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 3. To simplify locating the pins, each fifth pin is shaded in the illustration. AA0900 Figure 3-3 Top View of the 132-pin Ceramic (FE) Quad Flat Package 3-4 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A 1 117 18 Orientation Mark (On Top Side) (Bottom View) 84 51 nc PS A0 A1 GNDN GNDN A2 A3 nc A4 A5 nc VCCN VCCN A6 nc A7 A8 nc A9 A10 nc GNDN GNDN A11 A12 A13 nc A14 A15 D0 D1 nc nc H3/PB3 H2/PB2 nc H1/PB1 GNDH GNDH H0/PB0 nc RXD/PC0 TXD/PC1 SCLK/PC2 nc SC0/PC3 SCK/PC6 GNDQ GNDQ VCCQ VCCQ SC2/PC5 nc STD/PC8 SC1/PC4 nc SRD/PC7 BG/BS nc BR/WT WR RD X/Y DS nc nc D2 D3 D4 D5 nc GNDD GNDD D6 D7 D8 nc D9 D10 nc D11 VCCD VCCD D12 nc D13 D14 D15 nc D16 D17 nc GNDD GNDD D18 D19 D20 nc Freescale Semiconductor, Inc... nc D21 D22 D23 MODB/IRQB nc MODA/IRQA RESET nc XTAL EXTAL VCCQ VCCQ GNDQ GNDQ nc HA2/PB10 HA1/PB9 nc nc HA0/PB8 HACK/PB14 nc HEN/PB12 HR/W/PB11 HREQ/PB13 H7/PB7 VCCH VCCH H6/PB6 H5/PB5 H4/PB4 nc Pin-out and Package Information Note: 1. "nc" are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 3. To simplify locating the pins, each fifth pin is shaded in the illustration. AA0901 Figure 3-4 Bottom View of the 132-pin Ceramic (FE) Quad Flat Package MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 3-5 Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Orientation Mark 1 2 3 4 5 6 7 8 9 10 11 12 13 D19 D21 HA2 HA1 HACK HEN HR/W H6 H5 D17 D20 D23 MODA/ EXTAL GNDQ HA0 IRQA HREQ H7 H4 H3 D15 D18 VCCQ H2 H1 D14 D16 H0 RXD A D22 MODB/ RESET XTAL IRQB B Freescale Semiconductor, Inc... C D E F G GNDD D13 D11 GNDH D12 D10 TXD SC0 VCCD SCLK GNDQ VCCQ SCK (Top View) H D9 J D8 D7 K D6 D5 L D4 D2 M D3 D1 A15 N D0 A14 A13 Note: VCCH SC2 GNDD SRD STD BG/BS SC1 GNDN A12 A11 A9 A10 A8 VCCN GNDN A7 A5 A3 A6 A4 A2 RD BR/WT A0 DS WR A1 PS X/Y 1. "nc" are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 3. To simplify locating the pins, each fifth pin is shaded in the illustration. AA0902 Figure 3-5 Top View of the 88-pin Ceramic (RC) Pin Grid Array Package 3-6 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Orientation Mark (on Top side) 13 12 11 H5 H6 HR/W H3 H4 H7 H1 H2 RXD H0 10 9 8 7 HA1 HA2 6 5 4 3 2 1 A HEN HACK XTAL RESET MODB/ D22 IRQB D21 D19 HA0 GNDQ EXTAL MODA/ D23 IRQA D20 D17 VCCQ D18 D15 D16 D14 B HREQ Freescale Semiconductor, Inc... C VCCH D E F G H J K TXD GNDD GNDH SCLK SC0 SCK VCCQ GNDQ D12 VCCD STD D11 D10 (Bottom View) SC2 D9 SRD GNDD D7 D8 D5 D6 D2 D4 A15 D1 D3 A13 A14 D0 SC1 BG/BS L BR/WT RD M WR DS A0 N X/Y PS A1 Note: D13 GNDN VCCN A2 A3 A5 A4 A6 GNDN A7 A9 A11 A8 A10 A12 1. "nc" are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 3. To simplify locating the pins, each fifth pin is shaded in the illustration. AA0903 Figure 3-6 Bottom View of the 88-pin Ceramic (RC) Pin Grid Array Package MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 3-7 Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information The DSP56001A signals that may be programmed as General Purpose I/O are listed with their primary function in Table 3-1. Freescale Semiconductor, Inc... Table 3-1 DSP56001A General Purpose I/O Pin Identification 3-8 Pin Number 132 pin "FC" PQFP "FE" CQFP Pin Number 88 pin "RC" PGA Primary Function 25 D12 H0 PB0 22 C13 H1 PB1 20 C12 H2 PB2 19 B13 H3 PB3 16 B12 H4 PB4 15 A13 H5 PB5 14 A12 H6 PB6 11 B11 H7 5 B8 HA0 PB8 2 A8 HA1 PB9 1 A7 HA2 PB10 9 A11 HR/W PB11 8 A10 HEN PB12 10 B10 HREQ PB13 6 A9 HACK PB14 Port B DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com GPIO ID PB7 MOTOROLA Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Freescale Semiconductor, Inc... Table 3-1 DSP56001A General Purpose I/O Pin Identification Pin Number 132 pin "FC" PQFP "FE" CQFP Pin Number 88 pin "RC" PGA Primary Function 27 D13 RXD PC0 28 E13 TXD PC1 29 F13 SCLK PC2 31 F12 SC0 PC3 40 K13 SC1 37 H13 SC2 PC5 32 G13 SCK PC6 42 J12 SRD PC7 39 J13 STD PC8 Port C GPIO ID PC4 Table 3-2 DSP56001A Signal Identification by Pin Number -- PGA Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name A1 D19 D1 D14 L6 GNDN A2 D21 D2 D16 L8 VCCN A3 D22 D3 GNDD L9 GNDN A4 MODB/IRQB D12 H0/PB0 L12 RD A5 RESET D13 RXD/PC0 L13 BR/WT A6 XTAL E1 D13 M1 D3 A7 HA2/PB10 E11 GNDH M2 D1 A8 HA1/PB9 E13 TXD/PC1 M3 A15 A9 HACK/PB14 F1 D11 M5 A11 A10 HEN/PB12 F2 D12 M6 A9 A11 HR/W/PB11 F12 SC0/PC3 M8 A5 MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 3-9 Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Freescale Semiconductor, Inc... Table 3-2 DSP56001A Signal Identification by Pin Number -- PGA 3-10 Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name A12 H6/PB6 F13 SCLK/PC2 M9 A3 A13 H5/PB5 G1 D10 M11 A0 B1 D17 G3 VCCD M12 DS B2 D20 G11 GNDQ M13 WR B4 D23 G12 VCCQ N1 D0 B5 MODA/IRQA G13 SCK/PC6 N2 A14 B6 EXTAL H1 D9 N3 A13 B7 GNDQ H13 SC2/PC5 N4 A12 B8 HA0/PB8 J1 D8 N5 A10 B10 HREQ/PB13 J2 D7 N6 A8 B11 H7/PB7 J3 GNDD N7 A7 B12 H4/PB4 J12 SRD/PC7 N8 A6 B13 H3/PB3 J13 STD/PC8 N9 A4 C1 D15 K1 D6 N10 A2 C2 D18 K2 D5 N11 A1 C6 VCCQ K12 BG/BS N12 PS C9 VCCH K13 SC1/PC4 N13 X/Y C12 H2/PB2 L1 D4 -- -- C13 H1/PB1 L2 D2 -- -- DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Freescale Semiconductor, Inc... Table 3-3 DSP56001A Signal Identification by Pin Number --PQFP & CQFP Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 1 HA2/PB10 26 nc 51 nc 2 HA1/PB9 27 RXD/PC0 52 PS 3 nc 28 TXD/PC1 53 A0 4 nc 29 SCLK/PC2 54 A1 5 HA0/PB8 30 nc 55 GNDN 6 HACK/PB14 31 SC0/PC3 56 GNDN 7 nc 32 SCK/PC6 57 A2 8 HEN/PB12 33 GNDQ 58 A3 9 HR/W/PB11 34 GNDQ 59 nc 10 HREQ/PB13 35 VCCQ 60 A4 11 H7/PB7 36 VCCQ 61 A5 12 VCCH 37 SC2/PC5 62 nc 13 VCCH 38 nc 63 VCCN 14 H6/PB6 39 STD/PC8 64 VCCN 15 H5/PB5 40 SC1/PC4 65 A6 16 H4/PB4 41 nc 66 nc 17 nc 42 SRD/PC7 67 A7 18 nc 43 BG/BS 68 A8 19 H3/PB3 44 nc 69 nc 20 H2/PB2 45 BR/WT 70 A9 21 nc 46 WR 71 A10 22 H1/PB1 47 RD 72 nc 23 GNDH 48 X/Y 73 GNDN 24 GNDH 49 DS 74 GNDN 25 H0/PB0 50 nc 75 A11 MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 3-11 Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Freescale Semiconductor, Inc... Table 3-3 DSP56001A Signal Identification by Pin Number --PQFP & CQFP Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 76 A12 95 nc 114 D19 77 A13 96 D9 115 D20 78 nc 97 D10 116 nc 79 A14 98 nc 117 nc 80 A15 99 D11 118 D21 81 D0 100 VCCD 119 D22 82 D1 101 VCCD 120 D23 83 nc 102 D12 121 MODB/IRQB 84 nc 103 nc 122 nc 85 D2 104 D13 123 MODA/IRQA 86 D3 105 D14 124 RESET 87 D4 106 D15 125 nc 88 D5 107 nc 126 XTAL 89 nc 108 D16 127 EXTAL 90 GNDD 109 D17 128 VCCQ 91 GNDD 110 nc 129 VCCQ 92 D6 111 GNDD 130 GNDQ 93 D7 112 GNDD 131 GNDQ 94 D8 113 D18 132 nc Note: 1. 2. 3-12 "nc" are no connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Freescale Semiconductor, Inc... Table 3-4 DSP56001A Identification by Signal Name Signal Name 132 pin "FC" PQFP or "FE" CQFP Pin No. 88 pin "RC" PGA Pin No. Signal Name 132 pin "FC" PQFP or "FE" CQFP Pin No. 88 pin "RC" PGA Pin No. A0 53 M11 D8 94 J1 A1 54 N11 D9 96 H1 A2 57 N10 D10 97 G1 A3 58 M9 D11 99 F1 A4 60 N9 D12 102 F2 A5 61 M8 D13 104 E1 A6 65 N8 D14 105 D1 A7 67 N7 D15 106 C1 A8 68 N6 D16 108 D2 A9 70 M6 D17 109 B1 A10 71 N5 D18 113 C2 A11 75 M5 D19 114 A1 A12 76 N4 D20 115 B2 A13 77 N3 D21 118 A2 A14 79 N2 D22 119 A3 A15 80 M3 D23 120 B4 BG 43 K12 DS 49 M12 BR 45 L13 EXTAL 127 B6 BS 43 K12 GNDD 90 D3 D0 81 N1 GNDD 91 J3 D1 82 M2 GNDD 111 D2 85 L2 GNDD 112 D3 86 M1 GNDH 23 D4 87 L1 GNDH 24 MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com E11 3-13 Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Freescale Semiconductor, Inc... Table 3-4 DSP56001A Identification by Signal Name (Continued) Signal Name 132 pin "FC" PQFP or "FE" CQFP Pin No. 88 pin "RC" PGA Pin No. Signal Name 132 pin "FC" PQFP or "FE" CQFP Pin No. 88 pin "RC" PGA Pin No. D5 88 K2 GNDN 55 L6 D6 92 K1 GNDN 56 L9 D7 93 J2 GNDN 73 GNDN 74 PB2 20 C12 GNDQ 33 B7 PB3 19 B13 GNDQ 34 G11 PB4 16 B12 GNDQ 130 PB5 15 A13 GNDQ 131 PB6 14 A12 H0 25 D12 PB7 11 B11 H1 22 C13 PB8 5 B8 H2 20 C12 PB9 2 A8 H3 19 B13 PB10 1 A7 H4 16 B12 PB11 9 A11 H5 15 A13 PB12 8 A10 H6 14 A12 PB13 10 B10 H7 11 B11 PB14 6 A9 HA0 5 B8 PC0 27 D13 HA1 2 A8 PC1 28 E13 HA2 1 A7 PC2 29 F13 HACK 6 A9 PC3 31 F12 HEN 8 A10 PC4 40 K13 HR/W 9 A11 PC5 37 H13 HREQ 10 B10 PC6 32 G13 IRQA 123 B5 PC7 42 J12 3-14 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Freescale Semiconductor, Inc... Table 3-4 DSP56001A Identification by Signal Name (Continued) Signal Name 132 pin "FC" PQFP or "FE" CQFP Pin No. 88 pin "RC" PGA Pin No. Signal Name 132 pin "FC" PQFP or "FE" CQFP Pin No. 88 pin "RC" PGA Pin No. IRQB 121 A4 PC8 39 J13 MODA 123 B5 PS 52 N12 MODB 121 A4 RD 47 L12 NMI none none RESET 124 A5 PB0 25 D12 RXD 27 D13 PB1 22 C13 SC0 31 F12 SC1 40 K13 nc 26 SC2 37 H13 nc 30 SCK 32 G13 nc 38 SCLK 29 F13 nc 41 SRD 42 J12 nc 44 STD 39 J13 nc 50 TXD 28 E13 nc 51 VCCD 100 G3 nc 59 VCCD 101 nc 62 VCCH 12 nc 66 VCCH 13 nc 69 VCCN 63 nc 72 VCCN 64 nc 78 VCCQ 35 C6 nc 83 VCCQ 36 G12 nc 84 VCCQ 128 nc 89 VCCQ 129 nc 95 WR 46 nc 98 MOTOROLA C9 L8 M13 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 3-15 Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Freescale Semiconductor, Inc... Table 3-4 DSP56001A Identification by Signal Name (Continued) Signal Name 132 pin "FC" PQFP or "FE" CQFP Pin No. 88 pin "RC" PGA Pin No. Signal Name 132 pin "FC" PQFP or "FE" CQFP Pin No. WT 45 L13 nc 103 X/Y 48 N13 nc 107 XTAL 126 A6 nc 110 nc 3 nc 116 nc 4 nc 117 nc 7 nc 122 nc 17 nc 125 nc 18 nc 132 nc 21 88 pin "RC" PGA Pin No. Power and ground pins have special considerations for noise immunity. See the section Design Considerations. Table 3-5 DSP56001A Power Supply Pins 132 pin "FC" PQFP or "FE" CQFP Pin No. 88 pin "RC" PGA Pin No. 63 L8 Power Supply Circuit Supplied VCCN 64 55 L6 56 L9 Address Bus Buffers GNDN 73 74 3-16 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Table 3-5 DSP56001A Power Supply Pins (Continued) 132 pin "FC" PQFP or "FE" CQFP Pin No. 88 pin "RC" PGA Pin No. 100 G3 Power Supply Circuit Supplied VCCD 101 90 D3 91 J3 Data Bus Buffers Freescale Semiconductor, Inc... GNDD 111 112 35 C6 36 G12 VCCQ 128 129 33 B7 34 G11 Internal Logic GNDQ 130 131 12 C9 VCCH 13 Peripherals 23 E11 GNDH 24 MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 3-17 Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information A 128X A1 AC AC S G X X=L, M, OR N S1 J J1 1 N 17 Freescale Semiconductor, Inc... VIEW AB 117 18 116 CL VIEW AB B1 V1 PIN 1 IDENT M P B V BASE METAL AA L E P1 (D) AA 50 84 E1 D2 51 83 0.016 H L-M N 0.010 T L-M N 0.012 H L-M N 0.002 N 0.002 L-M PLATING 2X SECTION AC-AC 4X 4X 33 TIPS 4X 2X 0.004 T C C2 132X SEATING PLANE C1 T 132X D1 0.008 M T L-M N R R1 H K1 GAGE PLANE U K 132X D W NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1982. 2. DIMENSIONS IN INCHES. 3. DIMENSIONS A, B, J, AND P DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION FOR DIMENSIONS A AND B IS 0.007, FOR DIMENSIONS J AND P IS 0.010. 4. DATUM PLANE H IS LOCATED AT THE UNDERSIDE OF LEADSWHERE LEADS EXIT PACKAGE BODY. 5. DATUMS L, M, AND N TO BE DETERMINEDWHERECENTERLEADS EXIT PACKAGE BODY AT DATUM H. 6. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 7. DIMENSIONS A, B, J, AND P TO BE DETERMINED AT DATUM PLANE H. 8. DIMENSION F DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.019. 0.008 M T L-M N SECTION AA-AA DIM A A1 B B1 C C1 C2 D D1 D2 E E1 F G J J1 K K1 P P1 R1 S S1 U V V1 W INCHES MIN MAX 1.100 BSC 0.550 BSC 1.100 BSC 0.550 BSC 0.160 0.180 0.020 0.040 0.135 0.145 0.008 0.012 0.012 0.016 0.008 0.011 0.006 0.008 0.005 0.007 0.014 0.014 0.025 BSC 0.950 BSC 0.475 BSC 0.034 0.044 0.010 BSC 0.950 BSC 0.475 BSC 0.013 REF 1.080 BSC 0.540 BSC 0.025 REF 1.080 BSC 0.540 BSC 0.006 0.008 0 8 Figure 3-7 132-pin Plastic Quad Flat Pack (PQFP) Mechanical Information 3-18 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information J1 S 1 U J1 17 117 18 G VIEW AC 3 PLACES 116 Y PIN 1 IDENT L N X X=L, M OR N B V VIEW AC Freescale Semiconductor, Inc... F 50 PLATING 84 J 51 Z 83 M BASE METAL A D 0.008 M T L-N M 4X 33 TIPS 0.005 M T L-N M 0.10 T L-N M E SECTION AD VIEW AE 132 PLACES NOTES: C SEATING PLANE 1. W T 2. 3. 0.004 T 132X 4. 5. (AB) ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y14.5M, 1994. DIMENSIONS IN INCHES. DATUMS L, M AND N TO BE DETERMINED AT THE SEATING PLANE, DATUM T DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T DIMENSIONS A AND B DEFINE MAXIMUM CERAMIC BODYDIMENSIONSINCLUDINGGLASSPROTRUSION AND TOP AND BOTTOM MISMATCH. () (R) (R) K (AA) VIEW AE DIM A B C D E F G J K R S U V W Y Z AA AB INCHES MIN MAX 0.860 0.900 0.860 0.900 0.155 0.170 0.008 0.011 0.116 0.146 0.007 0.011 0.025 BSC 0.005 0.007 0.020 0.030 0.008 REF 1.080 BSC 0.540 BSC 1.080 BSC 0.025 0.035 1.080 BSC 0.004 0.005 0.100 REF 0.030 REF 0 8 Figure 3-8 132-pin Ceramic Quad Flat Pack (CQFP) Mechanical Information MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 3-19 Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information SEATING PLANE -T- -XK G N M L K J H G F E D C B A Freescale Semiconductor, Inc... -A- G NOTES: 1. DIMENSIONINGANDTOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. PIN DIAMETER DOES NOT INCLUDE SOLDER DIP OR CUSTOM FINISHES. DIM A B C D G K 1 2 3 4 5 6 7 8 9 10 11 12 13 -B- D C INCHES MIN MAX 1.340 1.380 1.340 1.380 0.085 0.120 0.017 0.020 0.100 BSC 0.165 0.200 88 PL 0.003 M T A S B S 0.010 M X PINS MATRIX Figure 3-9 88-pin Pin Grid Array (PGA) Mechanical Information Orientation Marks Top View 2x7 AA0617 Figure 3-10 PGA Shipping Tray 3-20 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information Freescale Semiconductor, Inc... Orientation Marks Top View 4x9 AA1132 Figure 3-11 PQFP Shipping Tray Orientation Marks Top View 4x9 AA0897 Figure 3-12 CQFP Shipping Tray MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 3-21 Freescale Semiconductor, Inc. DSP56001A Freescale Semiconductor, Inc... Pin-out and Package Information 3-22 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 4 DESIGN CONSIDERATIONS Freescale Semiconductor, Inc... SUBSTITUTING THE DSP56001A FOR THE DSP56001 This section highlights the differences between the DSP56001 and DSP56001A that need to be taken into consideration when substituting the DSP56001A for the DSP56001. New designs should use the DSP56002 due to its enhanced features and speed. Hardware Considerations NON-MASKABLE INTERRUPT (NMI) A Non-Maskable Interrupt (NMI) function was previously accessible on the DSP56001 by applying 10 volts to the MODB/IRQB pin. The DSP56001A does not support a non-maskable interrupt (NMI). CAUTION DO NOT APPLY 10 VOLTS TO ANY PIN OF THE DSP56001A (including MODB)! Subjecting any pin of the DSP56001A to voltages in excess of the specified TTL/CMOS levels will permanently damage the device. AC ELECTRICAL CHARACTERISTICS The DSP56001A die utilizes a faster technology than the DSP56001. As a result, many DSP56001A signals exhibit faster rise and fall times than the same signals on the DSP56001. These faster edges may generate more radiated noise and EMI, and may require more attention to these issues (e.g., the DSP56001A based circuit may require better decoupling). MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 4-1 Freescale Semiconductor, Inc. DSP56001A Substituting the DSP56001A for the DSP56001 Software/Application Considerations Software written for the DSP56001 will generally run unmodified on the DSP56001A. There are, however, certain differences which should be noted. Users should consider the impact these differences may have on each application. Freescale Semiconductor, Inc... AGU MODIFY REGISTERS Numbers between $8000 and $FFFE (inclusive) are not valid values for loading into the modify registers (M0-M7) of the address generation unit on the DSP56001. Certain values within this range, however, enable wrap-around addressing modes on the DSP56001A that are not supported, and inadvertent enabling of these addressing modes may yield unexpected results. Do not load the modify registers of the DSP56001A with values from $8000 to $FFFE. RESERVED MEMORY LOCATIONS Certain memory locations are designated as reserved on the DSP56001. Accesses to these memory locations on the DSP56001A will result in unpredictable processor behavior including the possibility of halting the processor completely. In particular, writes to the following X memory locations should be avoided on the DSP56001A: X:$FFDE, X:$FFDF, X:$FFFC, X:$FFFD MOVEP TO RN/NN/MN REGISTERS On the DSP56001 there is a pipeline delay when using the MOVEP instruction to change the contents of an address register (Mn, Nn, or Rn). The new contents of the destination address register will not be available for use during the following instruction (i.e, there is a single instruction cycle delay). On the DSP56001A this pipeline delay has been removed. If an address register (Mn, Nn, or Rn) is directly changed with a MOVEP instruction, the updated contents will be available for use during the following instruction. DSP56001 software that depends on this pipeline delay must be modified when moved onto the DSP56001A. MOVEP TO/FROM DATA ALU REGISTERS MOVEP instructions to/from Data ALU registers take 2 instruction cycles on the DSP56001. On the DSP56001A, these instructions take only 1 instruction cycle. DSP56001 software which is dependent on the timing of this form of the MOVEP instruction must be modified when ported to the DSP56001A. 4-2 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Substituting the DSP56001A for the DSP56001 Table 4-1 Illegal Instructions Freescale Semiconductor, Inc... Instruction Symbol Instruction Name DEBUG--DO NOT USE Enter Debug mode DEBUGcc--DO NOT USE Enter Debug mode conditionally DEC Decrement by one INC Increment by one MAC #iiii Signed multiply-accumulate immediate MPY #iiii Signed multiply immediate MACR #iiii Signed multiply-accumulate and round immediate MPYR #iiii Signed multiply and round immediate MOVEP IMMEDIATE MOVEP Immediate instructions take 3 instruction cycles on the DSP56001. On the DSP56001A, these instructions take only 2 instruction cycles. DSP56001 software that is dependent on the timing of this form of the MOVEP instruction must be modified when ported to the DSP56001A. ILLEGAL INSTRUCTIONS The instructions listed in Table 4-1 will not generate an illegal instruction interrupt on the DSP56001A. None of these instructions are tested on the DSP56001A and should not be used. Note: The DEBUG and DEBUGcc instructions are microcoded on the DSP56001A, but the peripherals necessary to make use of this instruction are not available. Any use of the DEBUG or DEBUGcc instructions will completely halt the processor. The processor will exit this state only on reset. STOP/WAIT TIMING Wake-up from the Stop and Wait operating modes with IRQA and IRQB is longer on the DSP56001A by one Tc period. SCI/SSI INITIALIZATION TIMING On the DSP56001A, the SCI and SSI clocks are stopped when the peripherals are not enabled in order to save power. As a result, the initialization time of the SCI and SSI is longer on the DSP56001A than on the DSP56001. MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 4-3 Freescale Semiconductor, Inc. DSP56001A Substituting the DSP56001A for the DSP56001 CONTROL REGISTERS The OMR and the Status Register on the DSP56001A have been altered from those on the DSP56001. Refer to Table 4-2 for details of these alterations. Table 4-2 Summary of Control Register Differences REGISTER DSP56001 DEFINITION DSP56001A DEFINITION EXPLAINATION OF DIFFERENCE 7 Reserved-- Read/Written as zero. Reserved-- Read as don't care. On the 001A this bit may be read as 0 or 1. The user should not rely on this bit being a given value. 14 Reserved-- Read/Written as zero. Reserved-- Write as zero only, read as don't care. If this bit is set on the 56001A, the operations performed by the Data ALU change, and 56001 code will yield erroneous results. Write this bit only as zero. Operating Mode Register 3 Reserved-- Read/.Written as zero Reserved-- Write as zero only, read as don't care. If this bit is set, memory reads may be from incorrect locations. Write this bit only as zero. Port B Control Register 1 Reserved-- Written as zero. Reserved-- Written as zero. Writing this bit as a 1 will result in behavior differences between the 001 and the 001A. Status Register Freescale Semiconductor, Inc... BIT HOST COMMAND VECTOR REGISTER The DSP56001A's Host Command Vector Register (CVR) also differs from that of the DSP56001 (see Table 4-3). Table 4-3 Summary of Host Command Vector Register Differences REGISTER BIT Host Command Vector Register (CVR) 5 4-4 DSP56001 DEFINITION Reserved-- Read as zero. DSP56001A DEFINITION EXPLAINATION OF DIFFERENCE Reserved--Read as don't care. This bit should be written with only a zero on the 56001A. DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Heat Dissipation HEAT DISSIPATION The average chip junction temperature, TJ, in C, can be obtained from: Freescale Semiconductor, Inc... Equation 1: TJ = TA + (PD x JA) Where: TA = JA = PD = PINT = PI/O = ambient temperature, C package thermal resistance, junction-to-ambient, C/W PINT + PI/O ICC x VCC watt--chip internal power power dissipation on input and output pins--user determined For most applications PI/O < PINT and PI/O can be neglected. An appropriate relationship between PD and TJ (if PI/O is neglected) is: Equation 2: PD = K / (TJ + 273) Solving equations (1) and (2) for K gives: Equation 3: K = PD x (TA + 273) + PD x JA Where: K is a constant pertaining to the particular package K can be determined from equation (2) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. The total thermal resistance of a package (JA) can be separated into two components, JC and CA, representing the barrier to heat flow from the semiconductor junction to the package (case) surface (JC) and from the case to the outside ambient (CA). These terms are related by the equation: Equation 4: JA = JC + CA JC is device-related and cannot be influenced by the user. However, CA is user-dependent and can be minimized by thermal management techniques such as heat sinks, ambient air cooling, and thermal convection. Thus, good thermal management can significantly reduce CA so that JA approximately equals JC. Values for thermal resistance presented in this document, unless estimated, were derived using the procedure described in Motorola Reliability Report 7843, "Thermal Resistance Measurement Method for MC68XX Microcomponent Devices", and are provided for design purposes only. Thermal measurements are complex and dependent on procedure and setup. User-derived values for thermal resistance may differ. MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 4-5 Freescale Semiconductor, Inc. DSP56001A Electrical Design Considerations ELECTRICAL DESIGN CONSIDERATIONS Freescale Semiconductor, Inc... CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Use the following list of recommendations to assure correct DSP operation: 4-6 * Provide a low-impedance path from the board power supply to each VCC pin on the DSP, and from the board ground to each GND pin. * Use at least four 0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. * Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 0.5 inch per capacitor lead. * Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VCC and GND. * Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the RD, WR, IRQA, IRQB, NMI, HEN, and HACK pins. * Consider all device loads, as well as parasitic capacitance due to PCB traces, when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. * All inputs must be terminated (i.e., not allowed to float) using CMOS levels. DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Power Consumption POWER CONSUMPTION Power dissipation is a key issue in portable DSP applications. The following describes some factors that affect current consumption. Current consumption is described by the formula: Equation 5: I = C x V x f Freescale Semiconductor, Inc... where : C = V = f = node/pin capacitance voltage swing frequency of node/pin toggle For example, for an address pin loaded with a 50 pF capacitance and operating at 5.5V with a 33 MHz clock, toggling at its maximum possible rate (which is 8.25 MHz), the current consumption is: Equation 6: I = 50 x 10-12x 5.5x8.25 x 106= 227 mA The maximum internal current value (ICCI - max), reflects the maximum possible switching of the internal buses, which is not necessarily a real application case. The typical internal current value (ICCI - typ) reflects the average switching of the internal buses. The following steps are recommended for applications requiring very low current consumption: 1. Minimize external memory accesses; use internal memory accesses instead. 2. Minimize the number of pins that are switching. 3. Minimize the capacitive load on the pins. 4. Connect the unused inputs to pull-up or pull-down resistors. HOST PORT CONSIDERATIONS Careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected. The situation exists in the Host Interface. The following paragraphs present considerations for proper operation. MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 4-7 Freescale Semiconductor, Inc. DSP56001A Host Port Considerations Host Programming Considerations UNSYNCHRONIZED READING OF RECEIVE BYTE REGISTERS When reading receive byte registers, RXH or RXL, the host program should use interrupts or poll the RXDF flag, which indicates that data is available. This assures that the data in the receive byte registers will be stable. OVERWRITING TRANSMIT BYTE REGISTERS Freescale Semiconductor, Inc... The host program should not write to the transmit byte registers, TXH or TXL, unless the TXDE bit is set, indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers will transfer valid data to the HRX register. SYNCHRONIZATION OF STATUS BITS FROM DSP TO HOST HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host processor (refer to the User's Manual for descriptions of these status bits). The host can read these status bits very quickly without regard to the clock rate used by the DSP, but the state of the bit could be changing during the read operation. Generally, this is not a system problem, since the bit will be read correctly in the next pass of any host polling routine. However, if the host asserts HEN for more than timing number 31, with a minimum cycle time of timing number 31 + 32, then these status bits are guaranteed to be stable. Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has significance, the host could read the wrong combination. Therefore, read the bits twice and check for consensus. OVERWRITING THE HOST VECTOR The host program should change the Host Vector register only when the Host Command bit (HC) is clear. This change will guarantee that the DSP interrupt control logic will receive a stable vector. CANCELLING A PENDING HOST COMMAND EXCEPTION The host processor may elect to clear the HC bit to cancel the host command exception request at any time before it is recognized by the DSP. Because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the DSP may execute the host command exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the same time that the HC bit is cleared. VARIANCE IN THE HOST INTERFACE TIMING The Host Interface (HI) may vary. Therefore, a host which attempts to load (bootstrap) the DSP should first make sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together with the INIT and then polling INIT, ISR, and the HREQ pin). 4-8 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Host Port Considerations DSP Programming Considerations SYNCHRONIZATION OF STATUS BITS FROM HOST TO DSP DMA, HF1, HF0, and HCP, HTDE, and HRDF status bits are set or cleared by the host processor side of the interface. These bits are individually synchronized to the DSP clock. (Refer to the User's Manual for descriptions of these status bits.) Freescale Semiconductor, Inc... READING HF0 AND HF1 AS AN ENCODED PAIR Care must be exercised when reading status bits HF0 and HF1 as an encoded pair, because the four combinations (00, 01, 10, and 11) each have significance. A very small probability exists that the DSP will read the status bits during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus. MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 4-9 Freescale Semiconductor, Inc. DSP56001A Application Examples APPLICATION EXAMPLES Freescale Semiconductor, Inc... The lowest cost DSP56001A-based system is shown in Figure 4-1. It uses no run time external memory and requires only two chips, the DSP56001A and a low cost EPROM. The EPROM read access time should be less than 780 nanoseconds when the DSP56001A is operating at a clock rate of 20.5 MHz. +5 V DSP56001A D23 BR HACK From Open Collector Buffer 2716 MODA/IRQA CE PS A0-A10 From Reset Function RESET D0-D7 11 8 A0-A10 D0-D7 MBD301* From Open Collector Buffer Note: MODB/IRQB 1. *These diodes must be Schottky diodes. 2. All resistors are 15 K unless noted otherwise. 3. When in Reset, IRQA and IRQB must be deasserted by external peripherals. AA0904 Figure 4-1 No Glue Logic, Low Cost Memory Port Bootstrap--Mode 1 4-10 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Application Examples A system with external data RAM memory requires no glue logic to select the external EPROM from Bootstrap mode. PS is used to enable the EPROM and DS is used to enable the high speed data memories, as shown in Figure 4-2. +5 V Freescale Semiconductor, Inc... DSP56001A RD WR BR HACK DS X/Y A0-A10 PS 11 10 A0-A9 A10 CS WE OE IRQB MODB/ IRQB IRQA MODA/ IRQA RESET RESET CE A0-A10 2716 D0-D7 8 2018-55 (3) D0-D23 24 +5 V D0-D23 D23 Note: 1. All resistors are 15 K unless noted otherwise. 2. When in Reset, IRQA and IRQB must be deasserted by external peripherals. AA0905 Figure 4-2 Port A Bootstrap with External Data RAM--Mode 1 MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 4-11 Freescale Semiconductor, Inc. DSP56001A Application Examples Figure 4-3 shows the DSP56001A bootstrapping via the Host Port from an MC68000. +5 V MC68000 12.5 MHz DSP56001A Freescale Semiconductor, Inc... HEN BR HACK LDS F32 Address Decode A4-A23 F32 AS +5 V 1K DTACK LS09 IRQB IRQA RESET MODB/ IRQB HR/W F32 F32 MODA/ IRQA HA0-HA2 R/W A1-A3 3 RESET H0-H7 D0-D7 8 D23 Note: 1. All resistors are 15 K unless noted otherwise. 2. When in Reset, IRQA and IRQB must be deasserted by external peripherals. AA0906 Figure 4-3 DSP56001A Host Bootstrap Example--Mode 5 4-12 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Application Examples In Figure 4-4, the DSP56001A is operated in Mode 3 with external program memory and the reset vector at location $0000. The programmer can overlay the high-speed on-chip Program RAM with DSP algorithms by using the MOVEM instruction. +5 V Freescale Semiconductor, Inc... DSP56001A RD BR HACK PS A0-A14 15 A0-A14 IRQB MODB/ IRQB IRQA MODA/ IRQA CS OE 2756-30 (3) RESET RESET D0-D23 24 D0-D23 D23 Note: 1. All resistors are 15 K unless noted otherwise. 2. When in Reset, IRQA and IRQB must be deasserted by external peripherals. AA0907 Figure 4-4 32K Words of External Program ROM--Mode 3 MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 4-13 Freescale Semiconductor, Inc. DSP56001A Application Examples Freescale Semiconductor, Inc... Figure 4-5 shows a circuit that waits until VCC on the DSP56001A is at least 4.5 V before initiating a 75,000 x TC oscillator stabilization delay required for the on-chip oscillator (only 25 x TC is required for an external oscillator). This insures that the DSP is operational and stable before releasing the reset signal. +5V R 2 (2) RESET 1 (1) CDLY MC34064 MC33064 + - 1.2 VREF 3 (4) Logic Reset Note: U1 tDLY = RCDLY In 1- 1 VTH VIN - VOL Where: tDLY = 75,000 TC minimum VIN = 5 V R = 8.2 K 5% fOSC = 20 MHz VTH = 2.5 V VOL = 0.4 V CDLY = 1 mf 20% TC = 50 ns 1. IRQA, and IRQB must be driven to the logic levels appropriate for the application. 2. MODA and MODB must be driven to the logic levels appropriate for the application. AA0908 Figure 4-5 Reset Circuit Using MC34064/MC33064 4-14 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56001A Application Examples IRQA IRQB B30 A27 A26 A25 A24 A23 A22 A17 A11 B14 B13 OSC A04 A05 A06 A07 A08 A09 A14 AEN IOR IOW +5V 1 2 3 4 5 6 7 8 9 10 11 23 13 PAL22V10 External Interrupt Sources 17 16 14 22 21 15 L13 BR B10 HREQ A9 HACK A10 A11 B5 A4 A5 HEN HR/W MODA/IRQA MODB/IRQB RESET B4 D23 DSP56001A 19 1 OE DIR A02 A03 A04 A05 A06 A07 A08 A09 A31 A30 A29 Note: D07 D06 D05 D04 D03 D02 D01 D00 11 12 13 14 15 16 17 18 MC74ACT245 Freescale Semiconductor, Inc... Figure 4-6 shows the DSP56001A connected to the bus of an IBM-PC computer. This circuit is complete and does not require external ROM or RAM to load and execute code from the PC. The PAL equations and other details of this circuit are available in the application report entitled "DSP56001 Interface Techniques and Examples" (APR11/D). 9 8 7 6 5 4 3 2 A00 A01 A02 B11 A12 A13 B12 B13 C12 C13 D12 H7 H6 H5 H4 H3 H2 H1 H0 B8 HA0 A8 HA1 A7 HA2 1. Connector is J1 of ISA Bus. 2. All series resistors are 15 K. AA0909 Figure 4-6 DSP56001A-to-ISA Bus Interface Schematic MOTOROLA DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com 4-15 Freescale Semiconductor, Inc. DSP56001A Freescale Semiconductor, Inc... Application Examples 4-16 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 5 ORDERING INFORMATION Table 5-1 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts. Freescale Semiconductor, Inc... Table 5-1 DSP56001A Ordering Information Part DSP56001A Package Type Ceramic Pin-Grid Array (PGA) Plastic Quad Flat Pack (PQFP) Ceramic Quad Flat Pack (CQFP) MOTOROLA Pin Count Frequency (MHz) 88 27 DSP56001ARC27 33 DSP56001ARC33 27 DSP56001AFC27 33 DSP56001AFC33 27 DSP56001AFE27 33 DSP56001AFE33 132 132 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com Order Number 5-1 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... DSP56001A 5-2 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. ROM Table Listings mu-Law / A-Law Expansion Tables APPENDIX A ROM TABLE LISTINGS The data ROM in the 56001A contains numeric tables. Freescale Semiconductor, Inc... Table A-1 contains the -law and A-law expansion table, stored in X-ROM from address X:$100. Table A-2 contains the sine wave table, stored in Y-ROM from address Y:$100. MU-LAW / A-LAW EXPANSION TABLES Table A-1 -Law / A-law Expansion Table ; M_00 M_01 M_02 M_03 M_04 M_05 M_06 M_07 M_08 M_09 M_0A M_0B M_0C M_0D M_0E M_0F M_10 M_11 M_12 M_13 M_14 M_15 ORG X:$100 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC $7D7C00 $797C00 $757C00 $717C00 $6D7C00 $697C00 $657C00 $617C00 $5D7C00 $597C00 $557C00 $517C00 $4D7C00 $497C00 $457C00 $417C00 $3E7C00 $3C7C00 $3A7C00 $387C00 $367C00 $347C00 MOTOROLA ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 8031 7775 7519 7263 7007 6751 6495 6239 5983 5727 5471 5215 4959 4703 4447 4191 3999 3871 3743 3615 3487 3359 M_16 M_17 M_18 M_19 M_1A M_1B M_1C M_1D M_1E M_1F M_20 M_21 M_22 M_23 M_24 M_25 M_26 M_27 M_28 M_29 M_2A M_2B M_2C M_2D DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DSP56001A/D, Rev. 1 $327C00 $307C00 $2E7C00 $2C7C00 $2A7C00 $287C00 $267C00 $247C00 $227C00 $207C00 $1EFC00 $1DFC00 $1CFC00 $1BFC00 $1AFC00 $19FC00 $18FC00 $17FC00 $16FC00 $15FC00 $14FC00 $13FC00 $12FC00 $11FC00 For More Information On This Product, Go to: www.freescale.com ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 3231 3103 2975 2847 2719 2591 2463 2335 2207 2079 1983 1919 1855 1791 1727 1663 1599 1535 1471 1407 1343 1279 1215 1151 A-1 Freescale Semiconductor, Inc. ROM Table Listings Freescale Semiconductor, Inc... mu-Law / A-Law Expansion Tables M_2E M_2F M_30 M_31 M_32 M_33 M_34 M_35 M_36 M_37 M_38 M_39 M_3A M_3B M_3C M_3D M_3E M_3F M_40 M_41 M_42 M_43 M_44 M_45 M_46 M_47 M_48 M_49 M_4A M_4B M_4C M_4D M_4E M_4F M_50 M_51 M_52 M_53 M_54 M_55 M_56 A-2 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC $10FC00 $0FFC00 $0F3C00 $0EBC00 $0E3C00 $0DBC00 $0D3C00 $0CBC00 $0C3C00 $0BBC00 $0B3C00 $0ABC00 $0A3C00 $09BC00 $093C00 $08BC00 $083C00 $07BC00 $075C00 $071C00 $06DC00 $069C00 $065C00 $061C00 $05DC00 $059C00 $055C00 $051C00 $04DC00 $049C00 $045C00 $041C00 $03DC00 $039C00 $036C00 $034C00 $032C00 $030C00 $02EC00 $02CC00 $02AC00 ; 1087 ; 1023 ; 975 ; 943 ; 911 ; 879 ; 847 ; 815 ; 783 ; 751 ; 719 ; 687 ; 655 ; 623 ; 591 ; 559 ; 527 ; 495 ; 471 ; 455 ; 439 ; 423 ; 407 ; 391 ; 375 ; 359 ; 343 ; 327 ; 311 ; 295 ; 279 ; 263 ; 247 ; 231 ; 219 ; 211 ; 203 ; 195 ; 187 ; 179 ; 171 M_57 M_58 M_59 M_5A M_5B M_5C M_5D M_5E M_5F M_60 M_61 M_62 M_63 M_64 M_65 M_66 M_67 M_68 M_69 M_6A M_6B M_6C M_6D M_6E M_6F M_70 M_71 M_72 M_73 M_74 M_75 M_76 M_77 M_78 M_79 M_7A M_7B M_7C M_7D M_7E M_7F DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DSP56001A/D, Rev. 1 $028C00 $026C00 $024C00 $022C00 $020C00 $01EC00 $01CC00 $01AC00 $018C00 $017400 $016400 $015400 $014400 $013400 $012400 $011400 $010400 $00F400 $00E400 $00D400 $00C400 $00B400 $00A400 $009400 $008400 $007800 $007000 $006800 $006000 $005800 $005000 $004800 $004000 $003800 $003000 $002800 $002000 $001800 $001000 $000800 $000000 For More Information On This Product, Go to: www.freescale.com ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 163 155 147 139 131 123 115 107 99 93 89 85 81 77 73 69 65 61 57 53 49 45 41 37 33 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 MOTOROLA Freescale Semiconductor, Inc. ROM Table Listings Freescale Semiconductor, Inc... mu-Law / A-Law Expansion Tables A_80 A_81 A_82 A_83 A_84 A_85 A_86 A_87 A_88 A_89 A_8A A_8B A_8C A_8D A_8E A_8F A_90 A_91 A_92 A_93 A_94 A_95 A_96 A_97 A_98 A_99 A_9A A_9B A_9C A_9D A_9E A_9F A_A0 A_A1 A_A2 A_A3 A_A4 A_A5 A_A6 A_A7 A_A8 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC MOTOROLA $158000 $148000 $178000 $168000 $118000 $108000 $138000 $128000 $1D8000 $1C8000 $1F8000 $1E8000 $198000 $188000 $1B8000 $1A8000 $0AC000 $0A4000 $0BC000 $0B4000 $08C000 $084000 $09C000 $094000 $0EC000 $0E4000 $0FC000 $0F4000 $0CC000 $0C4000 $0DC000 $0D4000 $560000 $520000 $5E0000 $5A0000 $460000 $420000 $4E0000 $4A0000 $760000 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 688 656 752 720 560 528 624 592 944 912 1008 976 816 784 880 848 344 328 376 360 280 264 312 296 472 456 504 488 408 392 440 424 2752 2624 3008 2880 2240 2112 2496 2368 3776 A_A9 A_AA A_AB A_AC A_AD A_AE A_AF A_B0 A_B1 A_B2 A_B3 A_B4 A_B5 A_B6 A_B7 A_B8 A_B9 A_BA A_BB A_BC A_BD A_BE A_BF A_C0 A_C1 A_C2 A_C3 A_C4 A_C5 A_C6 A_C7 A_C8 A_C9 A_CA A_CB A_CC A_CD A_CE A_CF A_D0 A_D1 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DSP56001A/D, Rev. 1 $720000 $7E0000 $7A0000 $660000 $620000 $6E0000 $6A0000 $2B0000 $290000 $2F0000 $2D0000 $230000 $210000 $270000 $250000 $3B0000 $390000 $3F0000 $3D0000 $330000 $310000 $370000 $350000 $015800 $014800 $017800 $016800 $011800 $010800 $013800 $012800 $01D800 $01C800 $01F800 $01E800 $019800 $018800 $01B800 $01A800 $005800 $004800 For More Information On This Product, Go to: www.freescale.com ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 3648 4032 3904 3264 3136 3520 3392 1376 1312 1504 1440 1120 1056 1248 1184 1888 1824 2016 1952 1632 1568 1760 1696 43 41 47 45 35 33 39 37 59 57 63 61 51 49 55 53 11 9 A-3 Freescale Semiconductor, Inc. ROM Table Listings Freescale Semiconductor, Inc... mu-Law / A-Law Expansion Tables A_D2 A_D3 A_D4 A_D5 A_D6 A_D7 A_D8 A_D9 A_DA A_DB A_DC A_DD A_DE A_DF A_E0 A_E1 A_E2 A_E3 A_E4 A_E5 A_E6 A_E7 A_E8 A_E9 A_EA A_EB A_EC A_ED A_EE A_EF A_F0 A_F1 A_F2 A_F3 A_F4 A_F5 A_F6 A_F7 A_F8 A_F9 A_FA A-4 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC $007800 $006800 $001800 $000800 $003800 $002800 $00D800 $00C800 $00F800 $00E800 $009800 $008800 $00B800 $00A800 $056000 $052000 $05E000 $05A000 $046000 $042000 $04E000 $04A000 $076000 $072000 $07E000 $07A000 $066000 $062000 $06E000 $06A000 $02B000 $029000 $02F000 $02D000 $023000 $021000 $027000 $025000 $03B000 $039000 $03F000 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 15 13 3 1 7 5 27 25 31 29 19 17 23 21 172 164 188 180 140 132 156 148 236 228 252 244 204 196 220 212 86 82 94 90 70 66 78 74 118 114 126 A_FB A_FC A_FD A_FE A_FF DC DC DC DC DC DSP56001A/D, Rev. 1 $03D000 $033000 $031000 $037000 $035000 For More Information On This Product, Go to: www.freescale.com ; ; ; ; ; 122 102 98 110 106 MOTOROLA Freescale Semiconductor, Inc. ROM Table Listings Sine Wave Table SINE WAVE TABLE Freescale Semiconductor, Inc... This sine wave table is normally used by FFT routines that use bit-reversed address pointers. This table can be used as it is for up to 512 point FFTs; however, for larger FFTs, the table must be copied to a different memory location to allow the Reverse-carry addressing mode to be used (see REVERSE-CARRY MODIFIER (Mn = $0000) in the DSP56001 User's Manual for additional information). Table A-2 Sine Wave Table ; S_00 S_01 S_02 S_03 S_04 S_05 S_06 S_07 S_08 S_09 S_0A S_0B S_0C S_0D S_0E S_0F S_10 S_11 S_12 S_13 S_14 S_15 S_16 S_17 S_18 S_19 ORG Y:$100 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC $000000 $03242B $0647D9 $096A90 $0C8BD3 $0FAB27 $12C810 $15E214 $18F8B8 $1C0B82 $1F19F9 $2223A5 $25280C $2826B9 $2B1F35 $2E110A $30FBC5 $33DEF3 $36BA20 $398CDD $3C56BA $3F174A $41CE1E $447ACD $471CED $49B415 MOTOROLA ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +0.0000000000 +0.0245412998 +0.0490676016 +0.0735644996 +0.0980170965 +0.1224106997 +0.1467303932 +0.1709619015 +0.1950902939 +0.2191012055 +0.2429800928 +0.2667128146 +0.2902846038 +0.3136816919 +0.3368898928 +0.3598949909 +0.3826833963 +0.4052414000 +0.4275551140 +0.4496113062 +0.4713967144 +0.4928981960 +0.5141026974 +0.5349975824 +0.5555701852 +0.5758082271 S_1A S_1B S_1C S_1D S_1E S_1F S_20 S_21 S_22 S_23 S_24 S_25 S_26 S_27 S_28 S_29 S_2A S_2B S_2C S_2D S_2E S_2F S_30 S_31 S_32 S_33 S_34 S_35 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DSP56001A/D, Rev. 1 $4C3FE0 $4EBFE9 $5133CD $539B2B $55F5A5 $5842DD $5A827A $5CB421 $5ED77D $60EC38 $62F202 $64E889 $66CF81 $68A69F $6A6D99 $6C2429 $6DCA0D $6F5F03 $70E2CC $72552D $73B5EC $7504D3 $7641AF $776C4F $788484 $798A24 $7A7D05 $7B5D04 For More Information On This Product, Go to: www.freescale.com ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +0.5956993103 +0.6152315736 +0.6343932748 +0.6531729102 +0.6715589762 +0.6895405054 +0.7071068287 +0.7242470980 +0.7409511805 +0.7572088242 +0.7730104923 +0.7883464098 +0.8032075167 +0.8175848722 +0.8314697146 +0.8448535204 +0.8577286005 +0.8700870275 +0.8819212914 +0.8932244182 +0.9039893150 +0.9142097235 +0.9238795042 +0.9329928160 +0.9415441155 +0.9495282173 +0.9569402933 +0.9637761116 A-5 Freescale Semiconductor, Inc. ROM Table Listings Freescale Semiconductor, Inc... Sine Wave Table S_36 S_37 S_38 S_39 S_3A S_3B S_3C S_3D S_3E S_3F S_40 S_41 S_42 S_43 S_44 S_45 S_46 S_47 S_48 S_49 S_4A S_4B S_4C S_4D S_4E S_4F S_50 S_51 S_52 S_53 S_54 S_55 S_56 S_57 S_58 S_59 S_5A S_5B S_5C S_5D S_5E A-6 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC $7C29FC $7CE3CF $7D8A5F $7E1D94 $7E9D56 $7F0992 $7F6237 $7FA737 $7FD888 $7FF622 $7FFFFF $7FF622 $7FD888 $7FA737 $7F6237 $7F0992 $7E9D56 $7E1D94 $7D8A5F $7CE3CF $7C29FC $7B5D04 $7A7D05 $798A24 $788484 $776C4F $7641AF $7504D3 $73B5EC $72552D $70E2CC $6F5F03 $6DCA0D $6C2429 $6A6D99 $68A69F $66CF81 $64E889 $62F202 $60EC38 $5ED77D ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +0.9700313210 +0.9757022262 +0.9807853103 +0.9852777123 +0.9891765118 +0.9924796224 +0.9951847792 +0.9972904921 +0.9987955093 +0.9996988773 +0.9999998808 +0.9996988773 +0.9987955093 +0.9972904921 +0.9951847792 +0.9924796224 +0.9891765118 +0.9852777123 +0.9807853103 +0.9757022262 +0.9700313210 +0.9637761116 +0.9569402933 +0.9495282173 +0.9415441155 +0.9329928160 +0.9238795042 +0.9142097235 +0.9039893150 +0.8932244182 +0.8819212914 +0.8700870275 +0.8577286005 +0.8448535204 +0.8314697146 +0.8175848722 +0.8032075167 +0.7883464098 +0.7730104923 +0.7572088242 +0.7409511805 S_5F S_60 S_61 S_62 S_63 S_64 S_65 S_66 S_67 S_68 S_69 S_6A S_6B S_6C S_6D S_6E S_6F S_70 S_71 S_72 S_73 S_74 S_75 S_76 S_77 S_78 S_79 S_7A S_7B S_7C S_7D S_7E S_7F S_80 S_81 S_82 S_83 S_84 S_85 S_86 S_87 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DSP56001A/D, Rev. 1 $5CB421 $5A827A $5842DD $55F5A5 $539B2B $5133CD $4EBFE9 $4C3FE0 $49B415 $471CED $447ACD $41CE1E $3F174A $3C56BA $398CDD $36BA20 $33DEF3 $30FBC5 $2E110A $2B1F35 $2826B9 $25280C $2223A5 $1F19F9 $1C0B82 $18F8B8 $15E214 $12C810 $0FAB27 $0C8BD3 $096A90 $0647D9 $03242B $000000 $FCDBD5 $F9B827 $F69570 $F3742D $F054D9 $ED37F0 $EA1DEC For More Information On This Product, Go to: www.freescale.com ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; +0.7242470980 +0.7071068287 +0.6895405054 +0.6715589762 +0.6531729102 +0.6343932748 +0.6152315736 +0.5956993103 +0.5758082271 +0.5555701852 +0.5349975824 +0.5141026974 +0.4928981960 +0.4713967144 +0.4496113062 +0.4275551140 +0.4052414000 +0.3826833963 +0.3598949909 +0.3368898928 +0.3136816919 +0.2902846038 +0.2667128146 +0.2429800928 +0.2191012055 +0.1950902939 +0.1709619015 +0.1467303932 +0.1224106997 +0.0980170965 +0.0735644996 +0.0490676016 +0.0245412998 +0.0000000000 -0.0245412998 -0.0490676016 -0.0735644996 -0.0980170965 -0.1224106997 -0.1467303932 -0.1709619015 MOTOROLA Freescale Semiconductor, Inc. ROM Table Listings Freescale Semiconductor, Inc... Sine Wave Table S_88 S_89 S_8A S_8B S_8C S_8D S_8E S_8F S_90 S_91 S_92 S_93 S_94 S_95 S_96 S_97 S_98 S_99 S_9A S_9B S_9C S_9D S_9E S_9F S_A0 S_A1 S_A2 S_A3 S_A4 S_A5 S_A6 S_A7 S_A8 S_A9 S_AA S_AB S_AC S_AD S_AE S_AF S_B0 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC $E70748 $E3F47E $E0E607 $DDDC5B $DAD7F4 $D7D947 $D4E0CB $D1EEF6 $CF043B $CC210D $C945E0 $C67323 $C3A946 $C0E8B6 $BE31E2 $BB8533 $B8E313 $B64BEB $B3C020 $B14017 $AECC33 $AC64D5 $AA0A5B $A7BD23 $A57D86 $A34BDF $A12883 $9F13C8 $9D0DFE $9B1777 $99307F $975961 $959267 $93DBD7 $9235F3 $90A0FD $8F1D34 $8DAAD3 $8C4A14 $8AFB2D $89BE51 MOTOROLA ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; -0.1950902939 -0.2191012055 -0.2429800928 -0.2667128146 -0.2902846038 -0.3136816919 -0.3368898928 -0.3598949909 -0.3826833963 -0.4052414000 -0.4275551140 -0.4496113062 -0.4713967144 -0.4928981960 -0.5141026974 -0.5349975824 -0.5555701852 -0.5758082271 -0.5956993103 -0.6152315736 -0.6343932748 -0.6531729102 -0.6715589762 -0.6895405054 -0.7071068287 -0.7242470980 -0.7409511805 -0.7572088242 -0.7730104923 -0.7883464098 -0.8032075167 -0.8175848722 -0.8314697146 -0.8448535204 -0.8577286005 -0.8700870275 -0.8819212914 -0.8932244182 -0.9039893150 -0.9142097235 -0.9238795042 S_B1 S_B2 S_B3 S_B4 S_B5 S_B6 S_B7 S_B8 S_B9 S_BA S_BB S_BC S_BD S_BE S_BF S_C0 S_C1 S_C2 S_C3 S_C4 S_C5 S_C6 S_C7 S_C8 S_C9 S_CA S_CB S_CC S_CD S_CE S_CF S_D0 S_D1 S_D2 S_D3 S_D4 S_D5 S_D6 S_D7 S_D8 S_D9 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DSP56001A/D, Rev. 1 $8893B1 $877B7C $8675DC $8582FB $84A2FC $83D604 $831C31 $8275A1 $81E26C $8162AA $80F66E $809DC9 $8058C9 $802778 $8009DE $800000 $8009DE $802778 $8058C9 $809DC9 $80F66E $8162AA $81E26C $8275A1 $831C31 $83D604 $84A2FC $8582FB $8675DC $877B7C $8893B1 $89BE51 $8AFB2D $8C4A14 $8DAAD3 $8F1D34 $90A0FD $9235F3 $93DBD7 $959267 $975961 For More Information On This Product, Go to: www.freescale.com ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; -0.9329928160 -0.9415441155 -0.9495282173 -0.9569402933 -0.9637761116 -0.9700313210 -0.9757022262 -0.9807853103 -0.9852777123 -0.9891765118 -0.9924796224 -0.9951847792 -0.9972904921 -0.9987955093 -0.9996988773 -1.0000000000 -0.9996988773 -0.9987955093 -0.9972904921 -0.9951847792 -0.9924796224 -0.9891765118 -0.9852777123 -0.9807853103 -0.9757022262 -0.9700313210 -0.9637761116 -0.9569402933 -0.9495282173 -0.9415441155 -0.9329928160 -0.9238795042 -0.9142097235 -0.9039893150 -0.8932244182 -0.8819212914 -0.8700870275 -0.8577286005 -0.8448535204 -0.8314697146 -0.8175848722 A-7 Freescale Semiconductor, Inc. ROM Table Listings Freescale Semiconductor, Inc... Sine Wave Table S_DA S_DB S_DC S_DD S_DE S_DF S_E0 S_E1 S_E2 S_E3 S_E4 S_E5 S_E6 S_E7 S_E8 S_E9 S_EA S_EB S_EC S_ED S_EE S_EF S_F0 S_F1 S_F2 S_F3 S_F4 S_F5 S_F6 S_F7 S_F8 S_F9 S_FA S_FB S_FC S_FD S_FE S_FF A-8 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC $99307F $9B1777 $9D0DFE $9F13C8 $A12883 $A34BDF $A57D86 $A7BD23 $AA0A5B $AC64D5 $AECC33 $B14017 $B3C020 $B64BEB $B8E313 $BB8533 $BE31E2 $C0E8B6 $C3A946 $C67323 $C945E0 $CC210D $CF043B $D1EEF6 $D4E0CB $D7D947 $DAD7F4 $DDDC5B $E0E607 $E3F47E $E70748 $EA1DEC $ED37F0 $F054D9 $F3742D $F69570 $F9B827 $FCDBD5 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; -0.8032075167 -0.7883464098 -0.7730104923 -0.7572088242 -0.7409511805 -0.7242470980 -0.7071068287 -0.6895405054 -0.6715589762 -0.6531729102 -0.6343932748 -0.6152315736 -0.5956993103 -0.5758082271 -0.5555701852 -0.5349975824 -0.5141026974 -0.4928981960 -0.4713967144 -0.4496113062 -0.4275551140 -0.4052414000 -0.3826833963 -0.3598949909 -0.3368898928 -0.3136816919 -0.2902846038 -0.2667128146 -0.2429800928 -0.2191012055 -0.1950902939 -0.1709619015 -0.1467303932 -0.1224106997 -0.0980170965 -0.0735644996 -0.0490676016 -0.0245412998 DSP56001A/D, Rev. 1 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... 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