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S
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6
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8-BIT LATCHED
DMOS POWER DRIVER
The A6B273KA and A6B273KLW combine eight (positive-edge-
triggered D-type) data latches and DMOS outputs for systems requiring
relatively high load power. Driver applications include relays, sole-
noids, and other medium-current or high-voltage peripheral power
loads. The CMOS inputs and latches allow direct interfacing with
microprocessor-based systems. Use with TTL may require appropriate
pull-up resistors to ensure an input logic high.
The DMOS output inverts the DATA input. All of the output
drivers are disabled (the DMOS sink drivers turned OFF) with the
CLEAR input low. The A6B273KA/KLW DMOS open-drain outputs
are capable of sinking up to 500 mA. Similar devices with reduced
rDS(on) are available as the A6273KA/KLW.
The A6B273KA is furnished in a 20-pin dual in-line plastic
package. The A6B273KLW is furnished in a 20-lead wide-body,
small-outline plastic package (SOIC) with gull-wing leads for surface-
mount applications. Copper lead frames, reduced supply current
requirements, and low on-state resistance allow both devices to sink
150 mA from all outputs continuously, to ambient temperatures over
85°C.
FEATURES
■50 V Minimum Output Clamp Voltage
■150 mA Output Current (all outputs simultaneously)
■5Ω Typical rDS(on)
■Low Power Consumption
■Replacements for TPIC6B273N and TPIC6B273DW
6B273
Note that the A6B273KA (DIP) and the A6B273KLW
(SOIC) are electrically identical and share a common
terminal number assignment.
1
2
3
8
9
13
14
15
16
17
19
4
5
6
7
12
18
20
IN
V
DD
GROUND
OUT
8
OUT
7
OUT
6
Dwg. PP-015-2A
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
10 11
CLEAR LOGIC
SUPPLY
STROBE
8
IN
7
IN
6
IN
5
IN
4
IN
3
IN
2
IN
1
LATCHES
LATCHES
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO............................... 50 V
Output Drain Current,
Continuous, IO.......................... 150 mA*
Peak, IOM ................................... 500 mA†
Single-Pulse Avalanche Energy,
EAS ................................................. 30 mJ
Logic Supply Voltage, VDD .................. 7.0 V
Input Voltage Range,
VI................................... -0.3 V to +7.0 V
Package Power Dissipation,
PD........................................... See Graph
Operating Temperature Range,
TA................................. -40°C to +125°C
Storage Temperature Range,
TS................................. -55°C to +150°C
* Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to damage if
exposed to extremely high static electrical charges.
Selection Guide
Part Number Pb-free* Package Packing RθJA
(°C/W)
A6B273KLW-T Yes 20-pin SOICW 37 per tube 70
A6B273KLWTR-T Yes 20-pin SOICW 1000 per reel 70
RθJC
(°C/W)
17
17
*Pb-based variants are being phased out of the product line. Some variants cited in
this footnote are in production but have been determined to be LAST TIME BUY or
NOT FOR NEW DESIGN. This classification indicates that sale of this device is currently
restricted to existing customer applications. The variants should not be purchased for new
design applications because obsolescence in the near future is probable. Samples are no
longer available. Status change for LAST TIME BUY: October 31, 2006. Deadline for
receipt of LAST TIME BUY orders: April 27, 2007. These variants include: A6B273KLW and
A6B273KLWTR. Status change for NOT FOR NEW DESIGN: May 1, 2006. These variants
include: A6B273KA.