LP2998MAXNOPB - NATIONAL SEMICONDUCTOR

LP2997

LP2997 DDR-II Termination Regulator

Literature Number: SNVS295D

LP2997

March 28, 2011

DDR-II Termination Regulator

General Description

The LP2997 linear regulator is designed to meet the JEDEC

SSTL-18 specifications for termination of DDR-II memory.

The device contains a high-speed operational amplifier to

provide excellent response to load transients. The output

stage prevents shoot through while delivering 500mA contin-

uous current and transient peaks up to 900mA in the appli-

cation as required for DDR-II SDRAM termination. The

LP2997 also incorporates a VSENSE pin to provide superior

load regulation and a VREF output as a reference for the

chipset and DIMMs.

An additional feature found on the LP2997 is an active low

shutdown (SD) pin that provides Suspend To RAM (STR)

functionality. When SD is pulled low the VTT output will tri-

state providing a high impedance output, but, VREF will remain

active. A power savings advantage can be obtained in this

mode through lower quiescent current.

Features

■Source and sink current

■Low output voltage offset

■No external resistors required

■Linear topology

■Suspend to Ram (STR) functionality

■Low external component count

■Thermal Shutdown

■Available in SO-8, PSOP-8 packages

Applications

■DDR-II Termination Voltage

■SSTL-18 Termination

Typical Application Circuit

20109418

LP2997 DDR-II Termination Regulator

Connection Diagrams

20109403

PSOP-8 Layout

20109404

SO-8 Layout

Pin Descriptions

SO-8 Pin or PSOP-8 Pin Name Function

1 GND Ground

2 SD Shutdown

3 VSENSE Feedback pin for regulating VTT.

4 VREF Buffered internal reference voltage of VDDQ/2

5 VDDQ Input for internal reference equal to VDDQ/2

6 AVIN Analog input pin

7 PVIN Power input pin

8 VTT Output voltage for connection to termination resistors

EP Exposed pad thermal connection Connect to soft Ground

Ordering Information

Order Number Package Type NSC Package Drawing Supplied As

LP2997M SO-8 M08A 95 Units per Rail

LP2997MX SO-8 M08A 2500 Units Tape and Reel

LP2997MR PSOP-8 MRA08A 95 Units Tape and Reel

LP2997MRX PSOP-8 MRA08A 2500 Units Tape and Reel

www.national.com 2

LP2997

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

AVIN to GND −0.3V to +6V

PVIN to GND -0.3V to AVIN

VDDQ (Note 2) −0.3V to +6V

Storage Temp. Range −65°C to +150°C

Junction Temperature 150°C

Lead Temperature (Soldering, 10 sec) 260°C

SO-8 Thermal Resistance (θJA)151°C/W

PSOP-8 Thermal Resistance (θJA)43°C/W

Minimum ESD Rating (Note 3) 1kV

Operating Range

Junction Temp. Range (Note 4) 0°C to +125°C

AVIN to GND 2.2V to 5.5V

Electrical Characteristics Specifications with standard typeface are for TJ = 25°C and limits in boldface type

apply over the full Operating Temperature Range (TJ = 0°C to +125°C) (Note 5). Unless otherwise specified,

AVIN = 2.5V, PVIN = 1.8V, VDDQ = 1.8V.

Symbol Parameter Conditions Min Typ Max Units

VREF VREF Voltage PVIN = VDDQ = 1.7V

PVIN = VDDQ = 1.8V

PVIN = VDDQ = 1.9V

0.837

0.887

0.936

0.860

0.910

0.959

0.887

0.937

0.986

ZVREF VREF Output Impedance IREF = -30 to +30 μA 2.5 kΩ

VTT VTT Output Voltage IOUT = 0A

PVIN = VDDQ = 1.7V

PVIN = VDDQ = 1.8V

PVIN = VDDQ = 1.9V

0.822

0.874

0.923

0.856

0.908

0.957

0.887

0.939

0.988 V

IOUT = ±0.5A (Note 8)

PVIN = VDDQ = 1.7V

PVIN = VDDQ = 1.8V

PVIN = VDDQ = 1.9V

0.828

0.878

0.928

0.856

0.908

0.957

0.890

0.940

0.990

VosTT/VTT VTT Output Voltage Offset

(VREF-VTT)

IOUT = 0A

IOUT = -0.5A

IOUT = +0.5A

-25

IQQuiescent Current (Note 6) IOUT = 0A (Note 6) 320 500 µA

ZVDDQ VDDQ Input Impedance 100 kΩ

ISD Quiescent Current in

Shutdown (Note 6)

SD = 0V 115 150 µA

IQ_SD Shutdown Leakage Current SD = 0V 2 5µA

VIH Minimum Shutdown High

Level

1.9 V

VIL Maximum Shutdown Low

Level

0.8 V

ISENSE VSENSE Input Current 13 nA

TSD Thermal Shutdown (Note 7) 165 Celsius

TSD_HYS Thermal Shutdown

Hysteresis

10 Celsius

3 www.national.com

LP2997

Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is

intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics.

The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under

the listed test conditions.

Note 2: VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller.

Note 3: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.

Note 4: At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at θJA = 151.2° C/W

junction to ambient with no heat sink.

Note 5: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality

Control (SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL).

Note 6: Quiescent current defined as the current flow into AVIN.

Note 7: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction to ambient thermal resistance, θJA,

and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal

shutdown.

Note 8: VTT load regulation is tested by using a 10 ms current pulse and measuring VTT.

www.national.com 4

LP2997

Typical Performance Characteristics

Iq vs AVIN in SD

20109420

Iq vs AVIN

20109421

VIH and VIL

20109422

VREF vs VDDQ

20109424

VTT vs VDDQ

20109426

Iq vs AVIN in SD Temperature

20109427

5 www.national.com

LP2997

Iq vs AVIN Temperature

20109428

Maximum Sourcing Current vs AVIN

(VDDQ = 1.8V, PVIN = 1.8V)

20109435

Maximum Sinking Current vs AVIN

(VDDQ = 1.8V)

20109436

Block Diagram

20109405

www.national.com 6

LP2997

Description

The LP2997 is a linear bus termination regulator designed to

meet the JEDEC requirements of SSTL-18. The output, VTT

is capable of sinking and sourcing current while regulating the

output voltage equal to VDDQ / 2. The output stage has been

designed to maintain excellent load regulation while prevent-

ing shoot through. The LP2997 also incorporates two distinct

power rails that separates the analog circuitry from the power

output stage. This allows a split rail approach to be utilized to

decrease internal power dissipation. It also permits the

LP2997 to provide a termination solution for the next gener-

ation of DDR-SDRAM memory (DDRII).

Pin Descriptions

AVIN AND PVIN

AVIN and PVIN are the input supply pins for the LP2997. AVIN

is used to supply all the internal control circuitry. PVIN, how-

ever, is used exclusively to provide the rail voltage for the

output stage used to create VTT. These pins have the capa-

bility to work off separate supplies, under the condition that

AVIN is always greater than or equal to PVIN. For SSTL-18

applications, it is recommended to connect PVIN to the 1.8V

rail used for the memory core and AVIN to a rail within its

operating range of 2.2V to 5.5V (typically a 2.5V supply). PVIN

should always be used with either a 1.8V or 2.5V rail. This

prevents the thermal limit from tripping because of excessive

internal power dissipation. If the junction temperature ex-

ceeds the thermal shutdown than the part will enter a shut-

down state identical to the manual shutdown where VTT is tri-

stated and VREF remains active. A lower rail such as 1.5V can

be used but it will reduce the maximum output current, there-

fore it is not recommended for most termination schemes.

VDDQ

VDDQ is the input used to create the internal reference volt-

age for regulating VTT. The reference voltage is generated

from a resistor divider of two internal 50kΩ resistors. This

guarantees that VTT will track VDDQ / 2 precisely. The optimal

implementation of VDDQ is as a remote sense. This can be

achieved by connecting VDDQ directly to the 1.8V rail at the

DIMM instead of PVIN. This ensures that the reference volt-

age tracks the DDR memory rails precisely without a large

voltage drop from the power lines. For SSTL-18 applications

VDDQ will be a 1.8V signal, which will create a 0.9V termina-

tion voltage at VTT (See Electrical Characteristics Table for

exact values of VTT over temperature).

VSENSE

The purpose of the sense pin is to provide improved remote

load regulation. In most motherboard applications the termi-

nation resistors will connect to VTT in a long plane. If the output

voltage was regulated only at the output of the LP2997 then

the long trace will cause a significant IR drop resulting in a

termination voltage lower at one end of the bus than the other.

The VSENSE pin can be used to improve this performance, by

connecting it to the middle of the bus. This will provide a better

distribution across the entire termination bus. If remote load

regulation is not used then the VSENSE pin must still be con-

nected to VTT. Care should be taken when a long VSENSE trace

is implemented in close proximity to the memory. Noise pick-

up in the VSENSE trace can cause problems with precise

regulation of VTT. A small 0.1uF ceramic capacitor placed next

to the VSENSE pin can help filter any high frequency signals

and preventing errors.

SHUTDOWN

The LP2997 contains an active low shutdown pin that can be

used for suspend to RAM functionality. In this condition the

VTT output will tri-state while the VREF output remains active

providing a constant reference signal for the memory and

chipset. During shutdown VTT should not be exposed to volt-

ages that exceed PVIN. With the shutdown pin asserted low

the quiescent current of the LP2997 will drop, however, VD-

DQ will always maintain its constant impedance of 100kΩ for

generating the internal reference. Therefore, to calculate the

total power loss in shutdown both currents need to be con-

sidered. For more information refer to the Thermal Dissipation

section. The shutdown pin also has an internal pull-up current;

therefore, to turn the part on the shutdown pin can either be

connected to AVIN or left open

VREF

VREF provides the buffered output of the internal reference

voltage VDDQ / 2. This output should be used to provide the

reference voltage for the Northbridge chipset and memory.

Since these inputs are typically an extremely high impedance,

there should be little current drawn from VREF. For improved

performance, an output bypass capacitor can be used, locat-

ed close to the pin, to help with noise. A ceramic capacitor in

the range of 0.1 µF to 0.01 µF is recommended. This output

remains active during the shutdown state and thermal shut-

down events for the suspend to RAM functionality.

VTT

VTT is the regulated output that is used to terminate the bus

resistors. It is capable of sinking and sourcing current while

regulating the output precisely to VDDQ / 2. The LP2997 is

designed to handle continuous currents of up to +/- 0.5A with

excellent load regulation. If a transient is expected to last

above the maximum continuous current rating for a significant

amount of time, then the bulk output capacitor should be sized

large enough to prevent an excessive voltage drop. If the

LP2997 is to operate in elevated temperatures for long dura-

tions care should be taken to ensure that the maximum junc-

tion temperature is not exceeded. Proper thermal de-rating

should always be used. (Please refer to the Thermal Dissi-

pation section) If the junction temperature exceeds the ther-

mal shutdown point than VTT will tri-state until the part returns

below the temperature hysteresis trip-point

Component Selections

INPUT CAPACITOR

The LP2997 does not require a capacitor for input stability,

but it is recommended for improved performance during large

load transients to prevent the input rail from dropping. The

input capacitor should be located as close as possible to the

PVIN pin. Several recommendations exist dependent on the

application required. A typical value recommended for AL

electrolytic capacitors is 22 µF. Ceramic capacitors can also

be used. A value in the range of 10 µF with X5R or better

would be an ideal choice. The input capacitance can be re-

duced if the LP2997 is placed close to the bulk capacitance

from the output of the 1.8V DC-DC converter. For the AVIN

pin, a small 0.1uF ceramic capacitor is sufficient to prevent

excessive noise from coupling into the device.

OUTPUT CAPACITOR

The LP2997 has been designed to be insensitive of output

capacitor size or ESR (Equivalent Series Resistance). This

allows the flexibility to use any capacitor desired. The choice

for output capacitor will be determined solely on the applica-

7 www.national.com

LP2997

tion and the requirements for load transient response of VTT.

As a general recommendation the output capacitor should be

sized above 100 µF with a low ESR for SSTL applications with

DDR-SDRAM. The value of ESR should be determined by the

maximum current spikes expected and the extent at which the

output voltage is allowed to droop. Several capacitor options

are available on the market and a few of these are highlighted

below:

AL - It should be noted that many aluminum electrolytics only

specify impedance at a frequency of 120 Hz, which indicates

they have poor high frequency performance. Only aluminum

electrolytics that have an impedance specified at a higher fre-

quency (100 kHz) should be used for the LP2997. To improve

the ESR several AL electrolytics can be combined in parallel

for an overall reduction. An important note to be aware of is

the extent at which the ESR will change over temperature.

Aluminum electrolytic capacitors can have their ESR rapidly

increase at cold temperatures.

Ceramic - Ceramic capacitors typically have a low capaci-

tance, in the range of 10 to 100 µF range, but they have

excellent AC performance for bypassing noise because of

very low ESR (typically less than 10 mΩ). However, some

dielectric types do not have good capacitance characteristics

as a function of voltage and temperature. Because of the typ-

ically low value of capacitance it is recommended to use

ceramic capacitors in parallel with another capacitor such as

an aluminum electrolytic. A dielectric of X5R or better is rec-

ommended for all ceramic capacitors.

Hybrid - Several hybrid capacitors such as OS-CON and SP

are available from several manufacturers. These offer a large

capacitance while maintaining a low ESR. These are the best

solution when size and performance are critical, although

their cost is typically higher than any other capacitors.

Thermal Dissipation

Since the LP2997 is a linear regulator any current flow from

VTT will result in internal power dissipation generating heat.

To prevent damaging the part from exceeding the maximum

allowable junction temperature, care should be taken to der-

ate the part dependent on the maximum expected ambient

temperature and power dissipation. The maximum allowable

internal temperature rise (TRmax) can be calculated given the

maximum ambient temperature (TAmax) of the application and

the maximum allowable junction temperature (TJmax).

TRmax = TJmax − TAmax

From this equation, the maximum power dissipation (PDmax)

of the part can be calculated:

PDmax = TRmax / θJA

The θJA of the LP2997 will be dependent on several variables:

the package used; the thickness of copper; the number of vias

and the airflow. For instance, the θJA of the SO-8 is 163°C/W

with the package mounted to a standard 8x4 2-layer board

with 1oz. copper, no airflow, and 0.5W dissipation at room

temperature. This value can be reduced to 151.2°C/W by

changing to a 3x4 board with 2 oz. copper that is the JEDEC

standard. Figure 1 shows how the θJA varies with airflow for

the two boards mentioned.

20109407

FIGURE 1. θJA vs Airflow (SO-8)

Additional improvements can be made by the judicious use of

vias to connect the part and dissipate heat to an internal

ground plane. Using larger traces and more copper on the top

side of the board can also help. With careful layout it is pos-

sible to reduce the θJA further than the nominal values shown

in Figure 1

Optimizing the θJA and placing the LP2997 in a section of a

board exposed to lower ambient temperature allows the part

to operate with higher power dissipation. The internal power

dissipation can be calculated by summing the three main

sources of loss: output current at VTT, either sinking or sourc-

ing, and quiescent current at AVIN and VDDQ. During the

active state (when shutdown is not held low) the total internal

power dissipation can be calculated from the following equa-

tions:

PD = PAVIN + PVDDQ + PVTT

Where,

PAVIN = IAVIN * VAVIN

PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ

To calculate the maximum power dissipation at VTT both con-

ditions at VTT need to be examined, sinking and sourcing

current. Although only one equation will add into the total,

VTT cannot source and sink current simultaneously.

PVTT = VVTT x ILOAD (Sinking) or

PVTT = ( VPVIN - VVTT) x ILOAD (Sourcing)

The power dissipation of the LP2997 can also be calculated

during the shutdown state. During this condition the output

VTT will tri-state, therefore that term in the power equation will

disappear as it cannot sink or source any current (leakage is

negligible). The only losses during shutdown will be the re-

duced quiescent current at AVIN and the constant impedance

that is seen at the VDDQ pin.

PD = PAVIN + PVDDQ

PAVIN = IAVIN x VAVIN

PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ

www.national.com 8

LP2997

Typical Application Circuits

Several different application circuits have been shown to il-

lustrate some of the options that are possible in configuring

the LP2997. Graphs of the individual circuit performance can

be found in the Typical Performance Characteristics section

in the beginning of the datasheet. These curves illustrate how

the maximum output current is affected by changes in AVIN

and PVIN.

Figure 2 shows the recommended circuit configuration for

DDR-II applications. The output stage is connected to the

1.8V rail and the AVIN pin can be connected to either a 2.5V,

3.3V or 5V rail.

This circuit permits termination in a minimum amount of board

space and component count. Capacitor selection can be var-

ied depending on the number of lines terminated and the

maximum load transient. However, with motherboards and

other applications where VTT is distributed across a long plane

it is advisable to use multiple bulk capacitors and addition to

high frequency decoupling. The bulk output capacitors should

be situated at both ends of the VTT plane for optimal place-

ment. Large aluminum electrolytic capacitors are used for

their low ESR and low cost.

20109413

FIGURE 2. Recommended DDR-II Termination

PCB Layout Considerations

1. The input capacitor for the power rail should be placed

as close as possible to the PVIN pin.

2. VSENSE should be connected to the VTT termination bus

at the point where regulation is required. For

motherboard applications an ideal location would be at

the center of the termination bus.

3. VDDQ can be connected remotely to the VDDQ rail input at

either the DIMM or the Chipset. This provides the most

accurate point for creating the reference voltage.

4. For improved thermal performance excessive top side

copper should be used to dissipate heat from the

package. Numerous vias from the ground connection to

the internal ground plane will help. Additionally these can

be located underneath the package if manufacturing

standards permit.

5. Care should be taken when routing the VSENSE trace to

avoid noise pickup from switching I/O signals. A 0.1uF

ceramic capacitor located close to the SENSE can also be

used to filter any unwanted high frequency signal. This

can be an issue especially if long SENSE traces are used.

6. VREF should be bypassed with a 0.01 µF or 0.1 µF

ceramic capacitor for improved performance. This

capacitor should be located as close as possible to the

VREF pin.

9 www.national.com

LP2997

Physical Dimensions inches (millimeters) unless otherwise noted

8-Lead Small Outline Package (M8)

NS Package Number M08A

8-Lead PSOP Package (PSOP-8)

NS Package Number MRA08A

www.national.com 10

LP2997

Notes

11 www.national.com

LP2997

Notes

LP2997 DDR-II Termination Regulator

For more National Semiconductor product information and proven design tools, visit the following Web sites at:

www.national.com

Products Design Support

Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench

Audio www.national.com/audio App Notes www.national.com/appnotes

Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns

Data Converters www.national.com/adc Samples www.national.com/samples

Interface www.national.com/interface Eval Boards www.national.com/evalboards

LVDS www.national.com/lvds Packaging www.national.com/packaging

Power Management www.national.com/power Green Compliance www.national.com/quality/green

Switching Regulators www.national.com/switchers Distributors www.national.com/contacts

LDOs www.national.com/ldo Quality and Reliability www.national.com/quality

LED Lighting www.national.com/led Feedback/Support www.national.com/feedback

Voltage References www.national.com/vref Design Made Easy www.national.com/easy

PowerWise® Solutions www.national.com/powerwise Applications & Markets www.national.com/solutions

Serial Digital Interface (SDI) www.national.com/sdi Mil/Aero www.national.com/milaero

Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic

PLL/VCO www.national.com/wireless PowerWise® Design

University

www.national.com/training

THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION

(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY

OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO

SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,

IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS

DOCUMENT.

TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT

NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL

PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR

APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND

APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE

NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.

EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO

LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE

AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR

PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY

RIGHT.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and

whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected

to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform

can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other

brand or product names may be trademarks or registered trademarks of their respective holders.

For the most current product information visit us at www.national.com

National Semiconductor

Americas Technical

Support Center

Email: support@nsc.com

Tel: 1-800-272-9959

National Semiconductor Europe

Technical Support Center

Email: europe.support@nsc.com

National Semiconductor Asia

Pacific Technical Support Center

Email: ap.support@nsc.com

National Semiconductor Japan

Technical Support Center

Email: jpn.feedback@nsc.com

www.national.com

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic."Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Audio www.ti.com/audio Communications and Telecom www.ti.com/communications

Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers

Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps

DLP®Products www.dlp.com Energy and Lighting www.ti.com/energy

DSP dsp.ti.com Industrial www.ti.com/industrial

Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical

Interface interface.ti.com Security www.ti.com/security

Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265