R3119x
7
OPERATING
Diagram for Operation (CD pin type: R3119NxxxA)
▪Due to Nch Open Drain output,
DOUT pin should be pulled-up to an
external voltage level.
Vref Delay
Circuit
VDD
Fig.1 Block Diagram of External Capacitor Connection
I x V DD
Fig.2 Operation Diagram II x V DD
Explanation of Operation
Step 1. The output voltage is equal to the pull-up voltage.
Step 2. At point “A”, Vref
>
VDD x (R2+R3) / (R1+R2+R3) is true, as a result, the output of comparator is
reversed from ”L” to “H”, therefore the output voltage becomes the GND level. The voltage level of
Point A means a detector threshold voltage (-VDET)
Step 3. When the input voltage is lower than the minimum operating voltage, the operation of the output
transistor becomes indefinite,. The output voltage is equal to the pull-up voltage.
Step 4. The output voltage is equal to the GND level.
Step 5. At Point “B”, Vref
<
VDD x R2 / (R1+R2) it true, as a result, the output of comparator is reversed from
“H” to “L”, then the output voltage is equal to the pull-up voltage. The voltage level of Point B means
a released voltage (+VDET)
Output delay time (tDELAY) is calculatable by an external capacitor as the following formula.
t
DELAY [s] =8.5 x 106 x CD [F]
Step 1 2 3
4 5
Comparator (-) pin
Input Voltage I II II II I
Comparator
Output L H
Indefinite H L
HYS Tr. OFF ON Indefinite ON OFF
Output Nch Tr. OFF ON Indefinite ON OFF
GND
CD
-
+
Comparator
R1
R2
R3 HYS Tr.
DOUT
Capacitor
Nch
4513 2
R2
R1+R2
R2+R3
R1+R2+R3
Input Voltage VDD
GND
Detector Threshold
Hysterisis
B
Released Voltage +
DET
Detector Threshold -
DET
GND
Detector
Delay Time
tRESET
Output Voltage DOUT Output
Delay Time
tDELAY
Pull-up Voltage
Minimum Operating Voltage
DDL