SiHG30N60E
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S15-1063-Rev. H, 04-May-15 1Document Number: 91455
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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E Series Power MOSFET
FEATURES
• Low figure-of-merit (FOM) Ron x Qg
• Low input capacitance (Ciss)
• Reduced switching and conduction losses
• Ultra low gate charge (Qg)
• Avalanche energy rated (UIS)
• Material categorization: for definitions of
compliance please see www.vishay.com/doc?99912
APPLICATIONS
• Server and telecom power supplies
• Switch mode power supplies (SMPS)
• Power factor correction power supplies (PFC)
• Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
- LED lighting
• Industrial
- Welding
- Induction heating
- Motor drives
• Battery chargers
• Renewable energy
- Solar (PV inverters)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 7 A.
c. 1.6 mm from case.
d. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C.
PRODUCT SUMMARY
VDS (V) at TJ max. 650
RDS(on) max. at 25 °C (Ω)V
GS = 10 V 0.125
Qg max. (nC) 130
Qgs (nC) 15
Qgd (nC) 39
Configuration Single
N-Channel MOSFET
G
D
S
TO-247AC
G
D
S
Available
ORDERING INFORMATION
Package TO-247AC
Lead (Pb)-free SiHG30N60E-E3
Lead (Pb)-free and Halogen-free SiHG30N60E-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 600 V
Gate-Source Voltage VGS ± 30
Continuous Drain Current (TJ = 150 °C) VGS at 10 V TC = 25 °C ID
29
ATC = 100 °C 18
Pulsed Drain Current a IDM 65
Linear Derating Factor 2W/°C
Single Pulse Avalanche Energy b EAS 690 mJ
Maximum Power Dissipation PD250 W
Operating Junction and Storage Temperature Range TJ, Tstg -55 to +150 °C
Drain-Source Voltage Slope VDS = 0 V to 80 % VDS dV/dt 70 V/ns
Reverse Diode dV/dt d18
Soldering Recommendations (Peak Temperature) c for 10 s 300 °C
SiHG30N60E
www.vishay.com Vishay Siliconix
S15-1063-Rev. H, 04-May-15 2Document Number: 91455
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA -62
°C/W
Maximum Junction-to-Case (Drain) RthJC -0.5
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 600 - - V
VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 250 μA - 0.64 - V/°C
Gate-Source Threshold Voltage (N) VGS(th) VDS = VGS, ID = 250 μA 2.0 2.8 4.0 V
Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA
VGS = ± 30 V - - ± 1 μA
Zero Gate Voltage Drain Current IDSS
VDS = 600 V, VGS = 0 V - - 1 μA
VDS = 600 V, VGS = 0 V, TJ = 150 °C - - 100
Drain-Source On-State Resistance RDS(on) V
GS = 10 V ID = 15 A - 0.104 0.125 Ω
Forward Transconductance a g
fs VDS = 8 V, ID = 3 A - 5.4 - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = 100 V,
f = 1.0 MHz
- 2600 -
pF
Output Capacitance Coss - 138 -
Reverse Transfer Capacitance Crss -3-
Effective Output Capacitance, Energy
Related a Co(er)
VDS = 0 V to 480 V, VGS = 0 V
-98-
Effective Output Capacitance, Time
Related b Co(tr) - 346 -
Total Gate Charge Qg
VGS = 10 V ID = 15 A, VDS = 480 V
-85130
nC Gate-Source Charge Qgs -15-
Gate-Drain Charge Qgd -39-
Turn-On Delay Time td(on)
VDD = 380 V, ID = 15 A,
VGS = 10 V, Rg = 4.7 Ω
-1940
ns
Rise Time tr -3265
Turn-Off Delay Time td(off) -6395
Fall Time tf -3675
Gate Input Resistance Rgf = 1 MHz, open drain - 0.63 - Ω
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISMOSFET symbol
showing the
integral reverse
p - n junction diode
--29
A
Pulsed Diode Forward Current ISM --65
Diode Forward Voltage VSD TJ = 25 °C, IS = 15 A, VGS = 0 V - - 1.3 V
Body Diode Reverse Recovery Time trr
TJ = 25 °C, IF = IS = 15 A,
dI/dt = 100 A/μs, VR = 20 V
- 402 605 ns
Body Diode Reverse Recovery Charge Qrr -715μC
Reverse Recovery Current IRRM -3265A
S
D
G
SiHG30N60E
www.vishay.com Vishay Siliconix
S15-1063-Rev. H, 04-May-15 3Document Number: 91455
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Coss and Eoss vs. VDS
0
10
20
30
40
50
60
70
80
0 5 10 15 20 25 30
ID- Drain Current (A)
VDS-Drain-to-Source Voltage (V)
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
BOTTOM 5.0 V
5 V
T
J
= 25 °C
0
10
20
30
40
50
0 5 10 15 20 25 30
ID- Drain Current (A)
VDS-Drain-to-Source Voltage (V)
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
BOTTOM 5.0 V
T
J
= 150 °C
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
0
20
40
80
0 5 10 15 20 25
TJ= 150 °C
TJ= 25 °C
60
0.0
0.5
1.0
1.5
2.0
2.5
3.0
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160
RDS(on) -On-Resistance
(Normalized)
TJ- Junction Temperature (°C)
ID= 15 A
VGS = 10 V
C - Capacitance (pF)
VDS - Drain-to-Source Voltage (V)
1
10
100
1000
10 000
0 100 200 300 400 500 600
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd x Cds shorted
Coss = Cds + Cgd
Crss = Cgd
Ciss
Crss
Coss
0
2
4
6
8
10
12
14
16
18
20
200
2000
0100200300400500600
Eoss (μJ)
Coss (pF)
VDS
Coss Eoss
SiHG30N60E
www.vishay.com Vishay Siliconix
S15-1063-Rev. H, 04-May-15 4Document Number: 91455
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Safe Operating Area
Fig. 10 - Maximum Drain Current vs. Case Temperature
Fig. 11 - Temperature vs. Drain-to-Source Voltage
0
4
8
12
16
20
24
0 25 50 75 100 125 150
VGS -Gate-to-Source Voltage (V)
Qg-Total Gate Charge (nC)
VDS= 480 V
ID= 15 A VDS= 300 V
VDS= 120 V
0.001
0.01
0.1
1
10
100
1000
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
IS-Source Current (A)
VSD-Source-to-Drain Voltage (V)
TJ= 150 °C
TJ= 25 °C
V
DS
, Drain-to-Source Voltage (V)
ID, Drain Current (A)
0.1
1
10
100
1000
0.1 1 10 1000
* V
GS
> minimum V
GS
at which R
DS(on)
is specied
Operation in this area
limited by R
DS(on)
BVDSS Limited
T
C
= 25 °C
T
J
= 150 °C
Single Pulse
100 μs
1 ms
10 ms
100
I
DM
Limited
10 μs
1 μs
0.1 μs
VDS, Drain-to-Source Breakdown
Voltage (V)
TJ-Temperature (°C)
550
575
600
625
650
675
700
725
-60 -40 -20 0 20 40 60 80 100 120 140 160
SiHG30N60E
www.vishay.com Vishay Siliconix
S15-1063-Rev. H, 04-May-15 5Document Number: 91455
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
Fig. 13 - Switching Time Test Circuit
Fig. 14 - Switching Time Waveforms
Fig. 15 - Unclamped Inductive Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
Fig. 17 - Basic Gate Charge Waveform
Fig. 18 - Gate Charge Test Circuit
0.01
0.1
1
0.0001 0.001 0.01 0.1 1
Normalized Effective Transient
Thermal Impedance
Square Wave Pulse Duration (s)
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
Single Pulse
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10 V
+
-
VDS
VDD
VDS
90 %
10 %
VGS
td(on) trtd(off) tf
R
G
I
AS
0.01 Ω
t
p
D.U.T
L
V
DS
+
-V
DD
10 V
Vary t
p
to obtain
required I
AS
IAS
VDS
VDD
VDS
tp
QGS QGD
QG
V
G
Charge
10 V
D.U.T.
3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
SiHG30N60E
www.vishay.com Vishay Siliconix
S15-1063-Rev. H, 04-May-15 6Document Number: 91455
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91455.
P.W. Period
dI/dt
Diode recovery
dV/dt
Ripple ≤ 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
VGS = 10 Va
ISD
Driver gate drive
D.U.T. lSD waveform
D.U.T. VDS waveform
Inductor current
D = P.W.
Period
+
-
+
+
+
-
-
-
Peak Diode Recovery dV/dt Test Circuit
VDD
• dV/dt controlled by Rg
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. - device under test
D.U.T. Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
Rg
Note
a. VGS = 5 V for logic level devices
VDD
Package Information
www.vishay.com Vishay Siliconix
Revision: 01-Jul-13 1Document Number: 91360
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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TO-247AC (High Voltage)
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Contour of slot optional.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions D1 and E1.
5. Lead finish uncontrolled in L1.
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").
7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.
8. Xian and Mingxin actually photo.
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.58 5.31 0.180 0.209 D2 0.51 1.30 0.020 0.051
A1 2.21 2.59 0.087 0.102 E 15.29 15.87 0.602 0.625
A2 1.17 2.49 0.046 0.098 E1 13.72 - 0.540 -
b 0.99 1.40 0.039 0.055 e 5.46 BSC 0.215 BSC
b1 0.99 1.35 0.039 0.053 Ø k 0.254 0.010
b2 1.53 2.39 0.060 0.094 L 14.20 16.25 0.559 0.640
b3 1.65 2.37 0.065 0.093 L1 3.71 4.29 0.146 0.169
b4 2.42 3.43 0.095 0.135 N 7.62 BSC 0.300 BSC
b5 2.59 3.38 0.102 0.133 Ø P 3.51 3.66 0.138 0.144
c 0.38 0.86 0.015 0.034 Ø P1 - 7.39 - 0.291
c1 0.38 0.76 0.015 0.030 Q 5.31 5.69 0.209 0.224
D 19.71 20.82 0.776 0.820 R 4.52 5.49 0.178 0.216
D1 13.08 - 0.515 - S 5.51 BSC 0.217 BSC
ECN: X13-0103-Rev. D, 01-Jul-13
DWG: 5971
0.10 AC
M M
E
E/2
(2)
(4)
R/2
B
2 x R
S
D
See view B
2 x e
b4
3 x b
2 x b2
L
C
L1
123
Q
D
A
A2
A
A
A1
C
Ø k BD
M M
A
ØP (Datum B)
ØP1
D1
4
E1
0.01 BD
M M
View A - A
Thermal pad
D2
DDE E
CC
View B
(b1, b3, b5) Base metal
c1
(b, b2, b4)
Section C - C, D - D, E - E
(c)
Planting
4
3
5
7
4
4
4
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
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Revision: 08-Feb-17 1Document Number: 91000
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