Acts) Integrator Series FPGAs 1200XL and 3200DX Familes Features Cadence, Escalade, Exemplar, IST, Mentor Graphics, Synopsys and Viewlogic e JTAG 1149.1 Boundary Scan Testing High Capacity e 2,500 to 40,000 logic gates Upto 4 Kbits configurable dual-port SRAM General Description + . : h * Fast wide-decode circuitry . Actels Integrator Series FPGAs are the first programmable * Up to 288 user-programmable 1/0 Pins logic devices optimized for high-speed system logic sg High Performance integration. Based on Actel's proprietary PLICE antifuse 225 MHz performance technology and_ state-of-the-art 0.6-micron double metal = 5nsDual-Port SRAM Access CMOS process, the Integrator Series devices offer a fine-grained, register-rich architecture with the industry's fastest embedded dual-port SRAM and wide decode circuitry. 3200DX and 1200XL FPGAs were designed to integrate 100 MHz FIFOs 7.5 ns 35-bit Address Decode Ease-of-Integration system logic which is typically implemented in multiple Synthesis-friendly architecture supports ASIC design CPLDs, PALs and FPGAs. These devices provide the features methodologies and performance required for todays complex, high-speed 95-100% device utilization using automatic Place and digital logic systems. The 3200DX family offers the industrys Route Tools fastest dual-port SRAM for implementing fast FIFOs, LIFOs and temporary data storage. The large number of storage elements can efficiently address applications requiring wide datapath manipulation and transformation functions such as telecommunications, networking and DSP. Deterministic, user-controllable timing via DirectTime software tools Supported by Actel Designer Series development system with interfaces to popular design environments such as Integrator Series Product Profile Device A1225XL A1240XL A3265DX A1280XL A32100DX A32140DX A32200DX A32300DX A32400DX Capacity Logic Gates' 2,500 4,000 6,500 8,000 10,000 14,000 20,000 30,000 40,000 SRAM Bits N/A N/A N/A N/A 2,048 N/A 2,560 3,072 4,096 Logic Modules Sequential 231 348 510 624 738 954 1276 1944 2592 Combinatorial 220 336 475 608 698 912 1226 1885 2560 Decode N/A N/A 20 N/A 22 24 28 32 34 SRAM Modules (64x4 or 32x8) NA NA NA NA 8 NA 10 12 16 Dedicated Flip-Flops 231 348 510 624 738 954 1,276 1,944 2,592 Clocks 2 2 2 2 6 2 6 6 6 User VO (maximum) 83 104 126 140 152 176 202 250 288 JTAG No No No No Yes Yes Yes Yes Yes Packages PL84 PL84 PL84 PL84 PL84 PQ1t60 PQ208 BG432 BG432 PQ100 PQ100 PQ160 PQ160 PQ160 PQ208 RQ208 VQ100 PQ144 TQ176 PQ208 TQ176 TQ176 RQ240 PG100 TQ176 TQ176 BG240 BG240 BG240 PG132 PG176 BG432 CQ172 Note 1: Logic gate capacity does not include SRAM bits as logic. April 1996 1-7 1996 Actel CorporationActs Ordering Information A1225 XL vVo- PQ 100 c Application (Temperature Range) C = Commercial (0 to +70C) | = Industrial (-40 to +85C) M = Military (-55 to +125C) B = MIL-STD-883 Package Lead Count Package Type PG = Ceramic Pin Grid Array PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flatpack RQ = Plastic Power Quad Flatpack TQ = Thin (1.4 mm) Quad Flatpack CQ = Ceramic Quad Flatpack BG = Plastic Ball Grid Array VQ = Very Thin (1.0 mm) Quad Flatpack \-- Speed Grade Blank = Standard Speed 1 = Approximately 15% faster than Standard 2 = Approximately 25% faster than Standard ' Operating Voltage V = 3.3 Volt Blank = 5.0 Volt ' Die Revision XL = 1200XL Family DX = 3200DX Family ' Part Number A1225 = 2500 Gates At240 = 4000 Gates A3265 = 6500 Gates Ai280 = 8000 Gates A32100 = 10000 Gates A32140 = 14000 Gates A32200 = 20000 Gates A32300 = 30000 Gates A32400 = 40000 Gates 1-8Integrator Series FPGAs - 1200XL and 3200DX Families Product Plan Speed Grade Application Std -1" ~2* c I M B A1225XL Device 84-pin Plastic Leaded Chip Carrier (PLCC) Vv Vv Vv v v _ _ 100-pin Plastic Quad Flatpack (PQFP) v v v Vv _ _ 100-pin Very Thin Plastic Quad Flatpack (VQFP) Vv v Vv v v _ 100-pin Ceramic Pin Grid Array (CPGA) v Vv v v _ _ - A1225XLV Device 84-pin Plastic Leaded Chip Carrier (PLCC) _ _ _ _ 100-pin Very Thin Plastic Quad Flatpack (VQFP) _ _ P _ _ _ A1240XL Device 84-pin Plastic Leaded Chip Carrier (PLCC) v v v v _ _ 100-pin Plastic Quad Flatpack (PQFP) P P P Pp P _ 132-pin Ceramic Pin Grid Array (CPGA) v v Vv _ _ _ 144-pin Plastic Quad Flatpack (PQFP) v v Vv v _ _ 176-pin Thin Plastic Quad Flatpack (TQFP) Vv v Vv Vv Vv _ A1240XLV Device 84-pin Plastic Leaded Chip Carrier (PLCC) Pp _ _ Pp _ _ 176-pin Thin Plastic Quad Flatpack (TQFP) P _ _ Pp _ _ A3265DX Device 84-pin Plastic Leaded Chip Carrier (PLCC) v v v v _ _ 160-pin Plastic Quad Flatpack (PQFP) v Vv v v Vv _ _ 176-pin Thin Plastic Quad Flatpack (TQFP) v v v Vv _ _ A3265DXV Device 84-pin Plastic Leaded Chip Carrier (PLCC) P _ _ P _ _ _ 176-pin Thin Plastic Quad Flatpack (TQFP) Pp _ p _ A1280XL Device 84-pin Plastic Leaded Chip Carrier (PLCC) Vv v v v _ _ 160-pin Plastic Quad Flatpack (PQFP) v v v Vv v _ _ 172-pin Ceramic Quad Flatpack (CQFP) Vv v v Vv _ P Pp 176-pin Thin Plastic Quad Flatpack (TQFP) v v v v v _ _ 176-pin Ceramic Pin Grid Array (CPGA) v v v v P P 208-pin Plastic Quad Flatpack (PQFP) P P P P P _ _ A1280XLV Device 84-pin Plastic Leaded Chip Carrier (PLCC) Pp _ Pp _ _ 176-pin Thin Plastic Quad Flatpack (TQFP) Pp _ _ Pp _ _ _ Applications: C = Commercial Availability, &% = Available * Speed Grade: -1 = Approx, 15% faster than Standard fo = Industrial P = Planned -2 = Approx, 25% faster than Standard M = Military ~~ = Not Planned B = MIL-STD-883 IntegratortS y/ Product Plan (continued) Speed Grade Application Std -t*" -2* Cc I M B A32100DX Device 84-pin Plastic Leaded Chip Carrier (PLCC) P P P P P _ _ 160-pin Plastic Quad Flatpack (PQFP) P P P P P _ 176-pin Thin Plastic Quad Flatpack (TQFP) P P P P Pp 240-pin Plastic Super Ball Grid Array (SBGA) P P P P Pp _ _ A32140DX Device 160-pin Plastic Quad Flatpack (PQFP) Vv Vv v Vv v _ _ 176-pin Thin Plastic Quad Flatpack (TQFP) v Vv v v v _ _ 208-pin Plastic Quad Flatpack (PQFP) Vv v v Vv _ _ 240-pin Plastic Super Ball Grid Array (SBGA) v v v v _ _ A32140DXV Device 176-pin Thin Plastic Quad Flatpack (TQFP) P _ P _ _ 208-pin Plastic Quad Flatpack (PQFP) _ _ Pp _ _ A32200DX Device 208-pin Plastic Quad Flatpack (PQFP) v v P v Pp _ _ 208-pin Plastic Power Quad Flatpack (RQFP) Vv P v P _ 240-pin Plastic Power Quad Flatpack (ROFP) Vv v P Vv Pp _ _ 240-pin Plastic Super Ball Grid Array (SBGA) P P P Pp P _ _ 432-pin Plastic Super Ball Grid Array (SBGA) Pp P P P P _ _ A32300DX Device 432-pin Plastic Super Ball Grid Array (SBGA) Pp P Pp P Pp _ _ A32400DX Device 432-pin Plastic Super Ball Grid Array (SBGA) P P P P Pp _ _ Applications: Co = Commercial Availability; W = Available * Speed Grade: ~1 = Approx. 15% faster than Standard f= Industrial P = Planned -2 = Approx. 25% faster than Standard M = Military = Not Planned B MIL-STD-883 1-10Integrator Serles FPGAs - 1200XL and 3200DX Familes Integrator Series devices are supported by Actels Designer Series Development software which provides a seamless integration into any ASIC design flow. The Designer Series development tools offer automatic placement and routing (even with pre-assigned pins), static timing analysis, user programming, and debug and diagnostic probe capabilities. In addition, the DirectTime tool provides deterministic as well as controllable timing. DirectTime allows the designer to specify the performance requirements of individual paths and system clock(s). Using these specifications, the software will automatically optimize the placement and routing of the logic to meet these constraints. Included with the Designer Series tools is Actels ACTGen Macro Builder, ACTGen allows the designer to quickly build fast, efficient logic functions such as counters, adders, FIFOs, and RAM. The Designer Series tools provide designers the capability to move up to High-Level Description Languages, such as VUDL Plastic Device Resources and Verilog, or use schematic design entry with interfaces to most EDA tools. Designer Series is supported on the following development platforms: 486 and Pentium PC, Sun and HP workstations. The software provides CAE interfaces to Cadence, Mentor Graphics, Escalade, OrCAD) and Viewlogic design environments. Additional development tools are supported through Actels Industry Alliance Program, including DATA I/O (ABEL FPGA) and MINC. Actels FPGAs are an ideal solution for shortening the system design and development cycle and offers a cost-effective alternative for low volume production runs. The 8200DX and 1200XL devices are an excellent choice for integrating logic that is currently implemented in multiple PALs, CPLDs and FPGAs. Some example applications include high-speed controllers and address decoding, peripheral bus interfaces, DSP, and co-processor functions. User VOs PLCC VQFP PQFP PQFP POFP PQFP RQFP TQFP SBGA SBGA Device 84-pin | 100-pin | 100-pin 144-pin 160-pin 208-pin 240-pin 176-pin | 240-pin 432-pin A1225XL 72 83 83 _ _ _ _ _ _ _ A1240XL 72 _ 83 104 _ _ 103 _ _ A3265DX 72 _ _ _ 125 _ _ 126 _ _ A1280XL 72 ~ _ _ 125 140 _ 140 _ _ A32100DX 72 _ _ 125 152 150 152 A32140DX _ _ _ _ 125 176 _ 150 176 _ A32200DX _ _ _ _ _ 176 202 _ _ 202 A32300DX _ _ _ _ ~ _ _ _ 250 A32400DX _ _ _ _ _ _ _ _ _ 288 Package Definitions (Consult your local Actel Sales Representative for product availability.) PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, BGA = Ball Grid Array, VQFP = Very Thin Quad Flat Pack, RQFP = Plastic Power Quad Flat Pack Also available in RQFP 208-pin. Hermetic Device Resources User /Os CPGA CQFP Device 176-pin 172-pin A1280XL 140 140 Package Definitions (Consult your local Actel Sales Representative for product availability. ) CPGA = Ceramic Pin Grid Array, CQFP = Ceramic Quad Flat Pack 1-11 integrator(Sy/ Pin Description CLKA, CLKB Clock A and Clock B (Input) TTL Clock inputs for clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK Diagnostic Clock (Input) TTL Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an 1/O when the MODE pin is LOW. GND Ground (input) Input LOW supply voltage. vo Input/Output (Input, Output) YO pin functions as an input, output, three-state or bi-directional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused [I/O pins are automatically driven LOW by the Designer Series software. MODE Mode (Input) The MODE pin controls the use of multi-function pins (DCLK, PRA, PRB, SDI, TDO). When the MODE pin is HIGH, the special functions are active. To provide Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the MODE pin can be pulled high when required. nc No Connection This pin is not connected to circuitry within the device. PRA/I/O Probe A (Output) The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined 1/0 when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is active when the MODE pin is HIGH. This pin functions as an [I/O when the MODE pin is LOW. PRB/V/O Probe B (Output) The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined 1/0 when debugging has been completed. The pins probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. QCLKA/B,C,D Quadrant Clock (Input/Output) These four pins are the quadrant clock inputs. When not used as a register control signal, these pins can function as general purpose [/0. SDI Serial Data Input (Input) Serial data input for diagnostic probe and device programming. SD] is active when the MODE pin is HIGH. This pin functions as an 1/O when the MODE pin is LOW. TCK Test Clock Clock signal to shift the JTAG data into the device. This pin functions as an I/O when the JTAG fuse is not programmed. Tol Test Data In Serial data input for JTAG instructions and data. Data is shifted in on the rising edge of TCLK. This pin functions as an I/O when the JTAG fuse is not programmed. Too Test Data Out Serial data output for JTAG instructions and test data. This pin functions as an I/O when the JTAG fuse is not programmed. TMS Test Mode Select Serial data input for JTAG test mode. Data is shifted in on the rising edge of TCLK. This pin functions as an I/O when the JTAG fuse is not programmed. Veco Supply Voltage (Input) Input HIGH supply voltage. TCK, TDI, TDO, TMS are only available on devices containing JTAG circuitry. Note: Integrator Series Architectural Overview The 1200XL and 3200DX architecture is composed of fine-grained building blocks which produce fast, efficient logic designs. All devices within the Integrator Series are composed of Logic Modules, Routing Resources, Clock Networks, and 1/O modules which are the building blocks to design fast logic designs. In addition, a subset of devices contain embedded dual-port SRAM and wide decode modules. The dual-port SRAM modules are optimized for high-speed data path functions such as FIFOs, LIFQs, and scratchpad memory. Integrator Series Product Profile on page 1-7 lists the specific logic resources contained within each device. 1-12Integrator Series FPGAs - 1200XL and 3200DX Familes Logic Modules 3200DX and 1200XL devices contain three types of logic modules: combinatorial (C-modules), sequential (S-modules), and decode (D-modules). 1200XL devices contain only the C-module and S-module, while the 3200DX devices contain D-modules and dual-port SRAM modules; in addition to the S-module and C-module. The C-module is shown in Figure 1 and implements the following function: Y=!81*1S0*D00+!8 1*S0*DG1+5 1*!S0*D01+51*S0*D11 where: S0=A0*B0 S1=A1+Bl The S-module shown in Figure 2 is designed to implement high-speed sequential functions within a single logic module. The S-module implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D Figure I C-module Implementation flip-flop or a transparent latch. To increase flexibility, the S-module register can be by-passed so that it implements purely combinatorial logic. H OUT Up to 7-input function plus D-type flip-flop with clear ]| Do Y D QrL OUT GATE Ss CLR Up to 4-input function plus latch with clear D Qr-- OUT GATE Up to 7-input function plus latch OUT Up to 8-input function (same as C-module) Figure 2 S-module Implementation 1-13 integrator3200DX devices contain a third type of logic module, D-modules, which are arranged around the periphery of device. D-modules contain wide decode circuitry which provides a fast, wide-input AND function similar to that found in product term architectures (Figure 3). The D-module allows 3200DX devices to perform wide decode functions at speeds comparable CPLDs and PAL devices. The output of the D-module has a programmable inverter for active HIGH or LOW assertion. The D-module output is hardwired to an output pin or can be fed back into the array to be incorporated into other logic. Dual-Port SRAM Modules Several 3200DX devices contain dual-port SRAM modules that have been optimized for synchronous or asynchronous applications. The SRAM modules are arranged in 256 bit blocks which can be configured as 32 x 8 or 64 x 4 (refer to Integrator Series Product Profile on page 7 for the number of SRAM blocks within a particular device). SRAM modules 7 inputs hardwire to I/O Programmable inverter feedback to array Figure 3 * D-Module Implementation can be cascaded together to form memory spaces of user-definable width and depth. A block diagram of the 3200DX dual-port SRAM block is shown in Figure 4. WDI[7:0] i Latches [7:0] [5:0] RDAD{5:0} Write SRAM Module Read a Latches <j Port 32 x 8 or 64x 4 Port WRAD[5:0} (5:0) | Logic (256 bits) Logic ~ Latch ea PP Latches | ocic i REN MODE tf RCLK BLKEN t>| Write | AD{7:0) Logic WEN ? 4 Routing Tracks WCLK Figure 4 3200DX Dual-Port SRAM Block The 3200DX SRAM modules are true dual-port structures containing independent READ and WRITE ports. Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0] respectively) for 64x4 bit blocks. When configured in byte mode, the highest order address bits (RDAD5 and WRADS) are not used. The read and write ports of the SRAM block contain independent clocks (RCLK and WCLK) with programmable polarities offering active HIGH or LOW implementation. The SRAM block contains eight data inputs (WD[7:0]) and eight outputs (RD[7:0]) which are connected to segmented vertical routing tracks. The 3200DX dual-port SRAM blocks are ideal for high-speed buffered applications requiring fast FIFO and LIFO queues. Actels ACTGen Macro Builder provides the capability to quickly design memory functions, such as FIFOs, LIFOs, andIntegrator Series FPGAs - 1200XL and 3200DX Familes RAM arrays. Additionally, unused SRAM blocks need not be wasted since they can be used to implement registers for other logic within the design. VO Modules The I/O modules provide the interface between the device pins and the logic array. Figure 5 is a block diagram of the 1/0 module. A variety of user functions, determined by a library macro selection, can be implemented in the module (refer to the Macro Library Guide for more information). YO modules contain a tri-state buffer, input and output latches which can be configured for input, output, or bi-directional pins (Figure 5). EN From Array PAD maQ D To Array G/CLK*} * Can be configured as a Latch or D Flip-Flop (using C-module) Figure 5 1/0 Module The Integrator Series devices contain flexible 1/0 structures in that each output pin has a dedicated output enable control. The I/O module can be used to latch input and/or output data, providing a fast setup time. In addition, the Actel Designer software tools can build a D flip-flop, using a C-module, to register input and/or output signals. Actels Designer Series development tools provide a design library of I/O macros. The I/O macro library provides macrofunctions which can implement all 1/0 configurations supported by the Integrator Series FPGAs. Routing Structure The I[ntegrator Series architecture uses Vertical and Horizontal routing tracks to interconnect the various logic and I/O modules. These routing tracks are metal interconnects that may either be of continuous length or broken into pieces called segments. Varying segment lengths allows the interconnect of over 90% of design tracks to occur with only two antifuse connections. Segments can be joined together at the ends, using antifuses, to increase their lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four antifuses. Horizontal Routing Horizontal channels are located between the rows of modules and are composed of several] routing tracks. The horizontal routing tracks within the channel are divided into one or more segments. The minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment length is the full length of the channel. Any segment that spans more than one-third the row length is considered a long horizontal segment. A typical channel is shown in Figure 6. Non-dedicated horizontal routing tracks are used to route signal nets. Dedicated routing tracks are used for the global clock networks and for power and ground tie-off tracks. Vertical Routing Another set of routing tracks run vertically through the module. Vertical tracks are of three types: input, output, and long. Vertical tracks are also divided into one or more segments. Each segment in an input track is dedicated to the input of a particular module. Each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. LVTs contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 6. Segmented horizontal | | i routing tracks ILI Logic L ill {| Moduies Antifuses Vertical routing tracks A Figure 6 Routing Structure Antifuse Structures An antifuse is a normally open structure as opposed to the normally closed fuse structure used in PROMs or PALs. The use of antifuses to implement a Programmable Logic Device results in highly testable structures as well as efficient programming algorithms. The structure is highly testable integratorSy/ because there are no pre-existing connections; therefore, temporary connections can be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed as well as isolate individual circuit structures to be tested. This can be done both before and after programming. For example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. Clock Networks Two low-skew, high fanout clock distribution networks are provided in each 3200DX device. These networks are referred to as CLKO and CLK]. Each network has a clock module (CLKMOD) that selects the source of the clock signal and may be driven as follows: I. Externally from the CLKA pad 2. Externally from the CLKB pad 3, Internally from the CLKINA input 4. Internally from the CLKINB input The clock modules are located in the top row of 1/0 modules. Clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. The user controls the clock module by selecting one of two clock macros from the macro library. The macro CLKBUF is used to connect one of the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally generated clock signal to a clock network. Since both clock networks are identical, the user does not care whether CLK0 or CLKI is being used. The clock input pads may also be used as normal I/Os, bypassing the clock networks (see Figure 7). The 3200DX devices which contain SRAM modules (all except A8265DX and A32140DX) have four additional register control resources, called Quadrant Clock Networks (Figure 8). Each quadrant. clock provides a local, high-fanout resource to the contiguous logic modules within its quadrant of the device. Quadrant clock signals can originate from specific I/O pins or from the internal array and can be used as a secondary register clock, register clear, or output enable. Test Circuitry Both 3200DX and 1200XL devices provide the means to test and debug a design once it is programmed into a device. 3200DX and 1200XL devices contain Actels Actionprobe test. facility. Once a device has been programmed, the Actionprobe test. facility allows the designer to probe any internal node during device operation to aid in debugging a design. In addition, 3200DX devices contain JTAG 1149.1 Boundary Scan Test. CLKB [X} CLKIN CLKA ae CLKIN PADS. L So INTERNAL CLKMOD | ___ gy SIGNAL r CLKO(17) DRIVERS : CLKO(16) f CLKO(15) | | | | 1 CLKO2) CLKO(1) CLOCK TRACKS Figure 7 Clock Networks JTAG Boundary Scan Testing (BST) Device pin spacing is decreasing with the advent of fine-pitch packages such as TQFP and BGA packages and manufacturers are routinely implementing surface-mount technology with multi-layer PC boards. Boundary scan is becoming an attractive tool to help systems manufacturers test their PC boards. The Joint Test Action Group (JTAG) developed the IEEE Boundary Scan standard 1149.1 to facilitate board-level testing during manufacturing. IEEE Standard 1149.1 defines a 4-pin Test Access Port (TAP) interface for testing integrated circuits in a system. The 3200DX family provides four JTAG BST pins: Test Data In (TDI), Test Data Out (TDO), Test Clock (TCLK) and Test Mode Select (TMS). Devices are configured in a JTAG chain where BST data can be transmitted serially between devices via TDO to TDI interconnections. The TMS and TCLK signals are shared between all devices in the JTAG chain so that. all components operate in the same state. The 3200DX family implements a subset of the IEEE 1149.1 Boundary Scan Test (BST) instruction in addition to a private instruction to allow the use of Actels Actionprobe facility with JTAG BST. Refer to the IEEE 1149.1 specification for detailed information regarding JTAG testing. STAG Architecture The 3200DX JTAG BST circuitry consist of a Test Access Port (TAP) controller, JTAG instruction register, JPROBE register, bypass register and boundary scan register, Figure 9 is a block diagram of the 3200DX JTAG circuitry.Integrator Series FPGAs - 1200XL and 3200DX Familes QCLKA ar ra QCLKC Quad Quad Clock QCcLK1 QCLK3 J Clock CLKB LKD Q KH Module Module 1) ac "QCLK1IN *QCLK3IN so $1 S1 SO Quad Quad Clock QCLK2 QCLK4 ; Clock Module Module *QCLK2IN J - *QCLK4IN so Si $1 SO *OCLKIIN, OCLEGIN, QCLKSIN, and QCKIAIN are internally generated signals. Figure 8 Quadrant Clock Network JPROBE Register MUX TDO Control Logic a Bypass Register Instruction Decode 4 TMS xt TAP Controller tc. [Xx] Instruction TOI 4 Register o- Figure 9 JTAG BST Circuitry IntegratorSy/ When a device is operating in JTAG BST mode, four I/O pins are used for the TDI, TDO, TMS, and TCLK signals. An active reset (nTRST) pin is not supported, however the 3200DX contains power-on reset circuitry which resets the JTAG BST circuitry upon power-up. During normal device operation, the JTAG pins should be held LOW to disable the JTAG circuitry. The following table summarizes the functions of the JTAG BST signals. JTAG Signat Name Function TDI Test Datatn Serial data input for JTAG instructions and data. Data is shifted in on the rising edge of TCLK. TDO Test Data Serial data output for JTAG Out instructions and test data. TS Test Mode Serial data input for JTAG test Select mode. Data is shifted in on the rising edge of TCLK. TCLK Test Clock Clock signal to shift the JTAG data into the device. JTAG BST Instructions JTAG BST testing within the 3200DX devices is controlled by a Test Access Port (TAP) state machine. The TAP controller drives the three-bit instruction register, a bypass register, and the boundary scan data registers within the device. The TAP controller uses the TMS signal to control the JTAG testing of the device. The JTAG test mode is determined by the bit stream entered on the TMS pin. The table in the next column describes the JTAG instructions supported by the 3200DX. Actionprobe If a device has been successfully programmed and the security fuse has not been programmed, any internal logic or I/O module output can be observed using the Actionprobe circuitry and the PRA and/or PRB pins. The Actionprobe diagnostic system provides the software and hardware required to perform real-time debugging. Refer to Using the Actionprobe for System-Level Debug application note on page 4-123 for further information, Test Mode Code Description EXTEST 000 Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. SAMPLE/ 001 Allows a snapshot of the signals PRELOAD at the device pins to be captured and examined during device operation. INTEST 010 Refer to IEEE 1149.1 Specification JPROBE o11 A private instruction allowing the user to connect Actels Micro Probe registers to the JTAG chain. USER 100 Allows the user to build INSTRUCTION application-specific instructions such as RAM READ and RAM WRITE. HIGH Z 101 Refer to IEEE 1149.1 Specification CLAMP 110 Refer to IEEE 1149.1 Specification BYPASS 111 Enables the by bypass register between the TOI and TDO pins. The test data passes through the selected device to adjacent devices in the JTAG chain.Integrator Series FPGAs - 1200XL and 3200DX Familes 5.0V Operating Conditions Recommended Operating Conditions Absolute Maximum Ratings! Parameter Commercial Industrial Military Units Temperature Oto ~40 to 55 to C Free air temperature range Range +70 485 4125 Symbol Parameter Limits Units Power Supply Voc DC Supply Voltage 0.5 to +7.0 Vv Tolerance +5 +10 #10 %Vcc Note: Vv Input Voltage 0.5 toV 05 V pu 9 cc * 1. Ambient temperature (T,) is used for commercial and Vo Output Voltage O0.5tOVec+0.5 V industrial, case temperature (T;) is used for military. lio /O Source/Sink +20 mA Current Tste Storage Temperature ~65 to +150 C Notes: I. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum. rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2 Device inputs are normally high impedence and draw extremely low current. However, when input voltage is greater than Veo + 0.5 V or less than GND - O.5V, the internal protection diode will be forward biased and can draw excessive current, Electrical Specifications Commercial Industrial Military Symbol Parameter Units Min. Max. Min. Max. Min. Max. Vou! (lon = -10 mA) @ 24 Vv (lon = -6 mA) 3.84 Vv (lon = 4 mA) 3.7 3.7 Vv Vo! (lo, = 10 mA)? 0.5 Vv (lo, = 6 MA) 0.33 0.40 0.40 Vv Vit -0.3 0.8 -0.3 0.8 -0.3 0.8 Vv Vin 20 Vect03 20 Veot+03 20 Vect+03 V Input Transition Time ta, te 500 500 500 ns Cio VO Capacitance? * 10 10 10 pF Standby Current, lec? (typical = 1 mA) 1.5 10 20 mA locip) Dynamic Voc Supply Current See Power Dissipation on page 1-21 Notes: 1 Only one output tested at a time. Veg = min. 2 Not tested, for information only. 3. Includes worst-case 176 CPGA package capacitance. Vopr = 0 V, f= 1 MHz. 4. All outmuts unloaded. All inputs = Voc or GND, typical lpg = L mA. [og Limit includes [pp and Ig, during normal operation. Integrator3.3V Operating Conditions Recommended Operating Conditions Absolute Maximum Ratings! Parameter Commercial Units Free air temperature range Temperature Range 0 to +70 C Power Supply Tolerance 45 %V Symbol Parameter Limits Units Note: Voc DC Supply Voltage 0.5 to +7.0 Vv 1. Ambient temperature (T,) is used for commercial. vi Input Voltage 0.5 to Voce +0.5 v Vo Output Voltage -0.5 to Voc +0.5 Vv VO Source Sink 20 mA 0 Current? Tstg Storage Temperature 65 to +150 C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute marimum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current, However, when input voltage is greater than Vor + 0.5 V or less than GND - 0.5 V, the internal protection diodes will forward bias and can draw excessive current. Electrical Specifications Commercial Parameter Units Min. Max. 4 (lon = ~4 mA) 2.15 Vv Vou (loy = -3.2 MA) 2.4 Vv Vow! (Io, = 6 MA) 0.4 Vv Vir 0.3 0.8 Vv Vin 2.0 Vec +0.3 Vv Input Transition Time ta, te? 500 ns Cio VO Capacitance: $ 10 pF Standby Current, icc (typical = 0.3 mA) 0.75 mA \oc(p) Dynamic Vcc Supply Current See Power Dissipation on page 1-21 Notes: {Only one output tested at a time. Voc = min. Not tested, for information only. 2. 3. Includes worst-case 84-pin PLCC package capacitance. Vor = 0 V, f = 1 MHz. 4. Typical standby current = 0.3 mA, All outputs wiloaded. All ingnets = Voc or GND.integrator Series FPGAs - 1200XL and 3200DX Familes Package Thermal Characteristics The device junction to case thermai characteristic is 6jc, and the junction to ambient air characteristic is @ja. The thermal characteristics for @ja are shown with two different air flow rates. Maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for a PQFP 160-pin package at commercial temperature is as follows: Max. junction temp. (C) - Max. commercial temp. _ [50C 70C _ @ja CCW) = ecw = 766 oja Maximum Power Dissipation Package Type Pin Count Still Air 300 ft/min Still Air 300 ft/min Plastic Quad Flatpack 160 36 C/W 30 C/W 2.2W 26W Plastic Quad Flatpack 208 25 C/W 16.2 C/W 3.2W 49W Plastic Leaded Chip Carrier 84 37 C/W 28 C/W 2.2W 2.9W Thin Quad Flatpack 176 32 C/W 25 C/W 25W 3.2W Power Quad Flatpack 208 16.8 C/W 11.4 C/W 48W 7.0W Power Quad Flatpack 240 16.1 C/W 10.6 C/W 5.0W 7.5W Bail Grid Array 240 14.0 C/W 10.0 C/W 5.7W 8.0W Ball Grid Array 432 10.0 C/W 8.0 CW 8.0OW 10.0W Power Dissipation General Power Equation P = [Igestandby + Ipcactive] * Vee + Top* Voy* N + lon* (Wee Vou) *M Where: Icestandby is the current flowing when no inputs or outputs are changing. Iccactive is the current flowing due to CMOS switching. low [oy are TTL sink/source currents. Vor: You are TTL level output voltages. N equals the number of outputs driving TTL loads to Vo), M equals the number of outputs driving TTL loads to Voy. An accurate determination of N and M is problematic because their values depend on the family type, design details, and on the system 1/0. The power can be divided into two components: static and active. Static Power Component Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALS/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial, worst case conditions. loc Vee Power 2mA 5.25 V 10.5 mW The static power dissipation by TTL loads depends on the number of outputs driving high or low and the DC load current. Again, this number is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with all outputs driving low and 140 mW with all outputs driving high. The actual dissipation will average somewhere between as [/Os switch states with time. Active Power Component Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem-pole current in the CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. IntegratorS/ Equivatent Capacitance The power dissipated by a CMOS circuit can be expressed by Equation 1. Power (LW) = Cyg * Vo? +P qd) Where: Crg Is the equivalent capacitance expressed in picofarads (pF). Voc is power supply in volts (VY). F is the switching frequency in megahertz (MHz}. Equivalent capacitance is calculated by measuring Iocartive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of Vo... Equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. Ceq Values for Actel FPGAs Modules (Cpgy) 5.2 Input Buffers (Cyqi) 11.6 Output Buffers (Cygo) 23.8 Routed Array Clock Buffer Loads (Cpgc) 3.5 To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piece-wise linear summation over all components. 25 . ke Power = Voc" * [Cx Crgat * find Modules + (n* Cra * fu) inputs +(p* (Cargo + Cy) * f outputs + 0.5 * (q; * Crgcr * fi routed_ClkI + (r * {qi routed Clk + 0.5 * (qa * Cegcr * fyadrouted_cike + (2 * fy2)routed_cura (2) Where: m = Number of logic modules switching at frequency f,, n = Number of input buffers switching at frequency f, p = Number of output buffers switching at frequency fp qy = Number of clock loads on the first routed array clock qe = Number of clock loads on the second routed array clock TY = Fixed capacitance due to first routed array clock Tr) = Fixed capacitance due to second routed array clock Cpgm = Equivalent capacitance of logic modules in pF Crg) = Equivalent capacitance of input buffers in pF Cregg = Equivalent capacitance of output buffers in pF Crack = Equivalent capacitance of routed array clock in pF Ch = Output load capacitance in pF fun = Average logic module switching rate in MHz fy = Average input buffer switching rate in MHz fh = Average output buffer switching rate in MHz fy. = Average first routed array clock rate in MHz fiz = Average second routed array clock rate in MHz Fixed Capacitance Values for Actel FPGAs (pF) r Ty Device Type routed. Clk routed_CIk2 AL225XL 106 106 Al240XL 134 134 A8265DX 158 158 AL280XL 168 168 A32100DX 178 178 A382140DX 190 190 A32200DX 230 230 A32300DX 285 285 Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: Logic Modules (m) = 80% of combinatorial modules Inputs switching (n) = # of inputs/4 Outputs switching (p) = #outputs/4 First routed array clock loads (q,) = 40% of sequential modules Second routed array clock loads = 40% of sequential (qa) modules Load capacitance (C,) = 35 pF Average logic module switching rate = F/10 (fn) Average input switching rate (f,) 9 = F/5 Average output switching rate (fp) = F/10 Average first routed array clock rate = F (fai) Average second routed array clock == F/2 rate (f,2) 1-22Integrator Series FPGAs - 1200XL and 3200DX Familes 1200XL Timing Model* XX Input Delays Internal Delays Proicted Output Delays outing _ F : Delays x Combinatorial [vo Module | Logie Module [170 Module 7 INYL= F-9NS t045=3.2 nst KKH {> | t {> | J | | toy = 3.8 ns | tap =0.8ns _- TT o- - D Q tep = 2.6 ns tee =1.3Nns | | tAD4 = ao ns = 32S _ G | ADB [VO Module toLH =3.8ns Sequential | tN = oS ns | Logic Module | | INSU = 9.3 NS _- 7-7 7 7 | tinat = 2.6 ns _| [ | | | Combin- Da DQ | | atorial | | Logic tapi = 0.8 ns tenuz = 5.4 ns | included | L in tsup t G L _ _ _l | fouTs = oo ns | = = OUTSU = . ARRAY 'suo=0-4ns | tco= 2.6 ns ton = 4.208 CLOCKS tub = 0.0 ns | | teoxu=5.1ns | FO = 256 7-7 Fax = 225 MHz tleo = 10.7 ns (64 loads, pad-pad) Values shown for A1225XL-2 at worst-case commercial conditions, + Input Module Predicted Routing Delay IntegratorSy/ 3200DX Timing Model (Logic Functions using Array Clocks)* Input Delays Internal Delays Predicted Output Delays outing - Delays _ [VO Module [VO Module | tinpy = 1.3.ns t =3.2ns iRO1= 9. Xt | [> e Combinatorial ? {> & | J | Module | tory = 3.7 ns | tapi =13 ns _ |- or | oa | 'pp = 2.5 ns tape = 1.8ns tap4q = 2.6 ns G | Decode | tind = 0.0 ns | eo tinsu =0.3 ns Module tapp =0.3ns L lingo = 2.6 ns _ t 2.9ns _ POD = - Me) Module _ toLH =3.7 ns Sequential | | Logic Module Combin- tapi = 1.3.ns | | atorial dba | | DQ Logic t = | included | \ ENHz = 3.7 ns in tsup 1 G fo | n= 2.0 ns | tsup = 0.3 ns tco = 2.5ns LSU = 0.9 NS tup = 0.0 ns |_tcHi= 4.6 ns | ARRAY CLOCKS texy = 5.1.ns Fax = 200 MHz Values shown for A3265DX-2 at worst-case commercial conditions. 1-24Integrator Series FPGAs - 1200XL and 3200DX Famites 3200DX Timing Model (Logic Functions using Quadrant Clocks)* Input Delays Internal Delays Fredicted Output Delays outing _ Delays [1/0 Module [70 Module 7] tinpy =1.3ns t =3.2ns x |e oo | N, | YI ' 7 t Combinatorial * 1 [ 1 | | Module | lou = 3.7 ns | D tro =1.3ns _ | - Tl | Q | tpp = 2.5 ns tape = 1.8 ns taba =26ns G | hh 2 Decode | tiny =0.0 ns | eo 8 tinsu = be ns Module tapp = 0.3 ns 5 t =2.6ns | INGOTS | tppp = 2.9ns = [VO Module _ toLH =3.7ns Sequential | | Logic Module [ | | Logic included | | in tsup | { G _ | tly =0.0ns Dans. es tigy = 0.3 ns tsup =0.3ns tco =2.5ns LSU _ tHp = 0.0 ns | tari= 4.6 ns QUADRANT CLOCKS * tokH = 12ns* Fax = 100 MHz * Preliminary values shown for A32200DX-2 al worst-case commercial conditions. ** Load dependent. | in- t =13 : Combin Da a ns 7 D a v : NJ tenHz =3.7ns | _ | 1-253200DX Timing Model (SRAM Functions)* Input Delays [vo Module tnpy =1.3ns tirot =3.2ns tinsu =0.3ns tinH =0.0ns tinco =2.6ns | WD [7:0] WRAD [5:0} BLKEN WEN WCLK AD [7:0] RDAD [5:0] REN RCLK tapsu =1.8ns tapH =0.0ns ARRAY twensu =2.9ns CLOCKS terns = 2.98 tapsu =1.8ns taoH = 0.0 ns trensu = 0.8 ns Predicted Routing VO Module Delays totH = 3.7 ns G tgHL= 4.6 ns tLsu =0.3ns {tH =0.0ns taco =3.8ns Fax = 100 MHz Values shown for Ad2200DX-2 at worst-case commercial conditions. 1-26Integrator Series FPGAs - 1200XL and 3200DX Familes Parameter Measurement Output Buffer Delays ieee TO AC test loads (shown below) 50% 50% touH toe integrator AC Test Loads Load 1 Load 2 (Used to measure propagation delay) (Used to measure rising/alling edges) Vec GND To the output under test e 35 pF R to Vcc for tpyz/tpz, R to GND for tpyz/tpzy To the output under test R=1kQ T aan a 35 pF Input Buffer Delays Module Delays s A -H Y PAD Y 1B "50% S5O0%K__ S, AorBy av Y 50% 50% teu teHL 50% Y 50% 50% tinyy tiny PHL PLM 1-27(Si Sequential Module Timing Characteristics Flip-Flops and Latches d D] PRE - Y E CLK P CLR | (Positive edge triggered) | tho D! x x betsup >| twotka ++-+| [+ t, ____+| G, CLK j | | | [ | |tsuenae be tworki>| l-+] thena E e tcoe| Q xX xX ++ trs PRE, CLR | | | twasyn | Note: D represents all data functions involving A, B, and S for maltiplered flip-flops. 1-28Integrator Series FPGAs - 1200XL and 3200DX Familes Sequential Timing Characteristics (continued) Input Buffer Latches DATA CLK IBDL CLKBUF DATA x x oles CLK |}< insu >| + tuext >| -@ tguext >| Output Buffer Latches OBDLHS IntegratorSy/ Decode Module Timing A-G,H OnmMooODyY teLH SRAM Timing Characteristics Write Port Read Port WRAD [5:0] RDAD [5:0] BLKEN RAM Array LEW WEN 32x8 or 64x4 (256 bits) REN WCLK RCLK WD [7:0} RD [7:0] 1-30Integrator Series FPGAs - 1200XL and 3200DX Familes Dual-Port SRAM Timing Waveforms 3200DX SRAM Write Operation tackHL tacKHL WCLK 4 tabH WDI7:0] WRADI5:0] V he WENH $ WEN a & BENH - BLKEN Note: Identical timing for falling-edge clock. 3200DX SRAM Synchronous Read Operation tRoKHL RCLK \ / tRENSU tRENH REN tapsu tabH RDAD[5:0] Valid taco toou RD[7:0] Old Data New Data Note: Identical timing for falling-edge clock. 1-31S/ 3200DX SRAM Asynchronous Read OperationType 1 (Read Address Controlled) taoaov RDAD[5:0] appre XX RD{[7:0} Data 2 3200DX SRAM Asynchronous Read OperationType 2 (Write Address Controlted) WEN t i WENSU 'WENH WD{(7:0] WRAD{[5:0] Valid BLKEN | taosu tau WCLK / RPD toon RD[7:0] Old Data New Data 1-32Integrator Series FPGAs - 1200XL and 3200DX Familes Predictable Performance: Tight Delay Distributions Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing tracks, the number of interconnect. elements, or the number of inputs increases. From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout. usually requires some paths to have longer routing tracks. The Integrator Series delivers a very tight fanout delay distribution. This tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel's patented PLICE antifuse offers a very low resistive/capacitive interconnect. The antifuses, fabricated in 0.6 micron lithography, offer nominal levels of 100 ohms resistance and 7.0 femtofarad (fF) capacitance per antifuse. The Integrator Series fanout distribution is also tight due to the low number of antifuses required for each interconnect. path. The proprietary architecture limits the number of antifuses per path to a maximum of four, with 90% of interconnects using two antifuses. Timing Characteristics Timing characteristics for devices fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all Integrator Series members. Internal routing delays are device dependent. Design dependency means actual delays are not determined until after placement and routing of the users design is complete. Delay values may then be determined by using the Designer Series utility or performing simulation with post-layout delays. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Since the architecture provides deterministic timing and abundant routing resources, Actels Designer Series development tools offers DirectTime; a timing-driven place and route tool. Using DirectTime, the designer may specify timing-critical nets and system clock frequency. Using these timing specifications, the place and route software optimized the layout of the design to meet the user's specifications. Long Tracks Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6% of nets in a fully utilized device require long tracks. Long tracks contribute approximately 3 ns to 6 ns delay. This additional delay is represented statistically in higher fanout (FO=8) routing delays in the data sheet specifications section. Timing Derating A best case timing derating factor of 0.45 is used to reflect best case processing. Note that this factor is relative to the standard speed timing parameters, and must be multiplied by the appropriate voltage and temperature derating factors for a given application. Timing Derating Factor (Temperature and Voltage) industrial Military Min. Max. Min. Max. (Commercial Specification) x 0.69 1.11 0.67 1.23 Timing Derating Factor for Designs at Typical Temperature (Ty = 25C) and Voltage {5.0 V) (Maximum Specification, Worst-Case Condition) x 0.85 | Note: This derating factor applies to all routing and propagation delays. 1-33 Integrator(Sy Temperature and Voltage Derating Factors (normalized to Worst-Case Commercial, Ty = 4.75 V, 70C) Note: -55 40 0 25 70 85 125 4.50 0.75 0.79 0.86 0.92 1.06 1.11 1.23 4,75 0.71 0.75 0.82 0.87 1.05 1.16 5.00 0.69 0.72 0.80 0.85 0.97 1.02 1.13 5.25 0.68 0.69 0.77 0.82 0.95 0.98 1.09 5.50 0.67 0.69 0.76 0.81 0.93 0.97 1.08 Junction Temperature and Voltage Derating Curves (normalized to Worst-Case Commercial, T) = 4.75 V, 70C) 1.3 1.2 eee = 11 a 3 . oe 125C Oo 3 1.0 2 a 885C = $s 006 eo + & 09 0.8 25C . ns , ()C> 0.7 _ x-40C_ * ~55C 0.6 + + + + + 4.50 4.75 5.00 5.25 5.50 Voltage (V) This derating factor applies to all routing and propagation delays. 1-34Integrator Series FPGAs - 1200XL and 3200DX Familes A1225XL Timing Characteristics (Worst-Case Commercial Conditions, Voc = 4.75 V, Ty = 70C) Logic Module Propagation Delays _2Speed | -1'Speed | Std Speed | 3.3V Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Units tens Single Modute 2.6 3.0 3.5 4.2 ns tco Sequential Clk to Q 2.6 3.0 3.5 4.2 ns tco Latch GtoQ 2.6 3.0 3.5 4.2 ns tas Flip-Flop (Latch) Reset to Q 2.6 3.0 3.5 4.2 ns Predicted Routing Delays tapi FO=1 Routing Delay 0.8 0.9 11 1.3 ns 5 tap2 FO=2 Routing Delay 1.3 1.4 17 2.0 ns 3 taps FO=3 Routing Delay 1.7 1.8 2.2 2.6 ns a tapa FO=4 Routing Delay 2.0 2.3 2.7 3.2 ns = taps FO=8 Routing Delay 3.2 3.5 4.2 5.0 ns = Sequential Timing Characteristics* tsup Flip-Flop (Latch) Data Input Setup 0.4 0.4 0.5 0.6 ns tub Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 ns ISUENA Flip-Flop (Latch) Enable Setup 0.8 0.9 1.0 1.2 ns THENA Flip-Flop (Latch) Enable Hoid 0.0 0.0 0.0 0.0 ns IWCLKA Flip-Flop (Latch) Clock Active Pulse Width 3.2 3.6 43 5.2 ns twasyn Flip-Flop (Latch) Asynchronous Pulse Width 3.2 3.6 43 .2 ns ty Flip-Flop Clock Input Period 6.5 7.4 8.7 10.4 ns tINH Input Buffer Latch Hald 0.0 0.0 0.0 0.0 ns tinsu Input Buffer Latch Setup 0.3 0.4 0.4 0.5 ns touTH Output Buffer Latch Hold 0.0 0.0 0.0 0.0 ns touTsu Output Buffer Latch Setup 0.3 0.4 0.4 0.5 ns tmax Flip-Flop (Latch) Clock Frequency 225.0 200.0 170.0 115.0 | MHz Notes: I. For dual-module macros, use lpp; + trp + tpn feo + trp + tpn OF bpps + trp + tsp Whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing ts based on actual routing delay measurements performed on the device prior to shipment. 3 Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained fram the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold toning parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5 Vee = 8.0 V for 2.38V specifications. 1-35Sy/ A1225XL Timing Characteristics (continued) (Worst-Case Commercial Conditions) Input Module Propagation Delays -2'Speed | -1 Speed | StdSpeed | 3.3V Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Units tiNvH Pad to Y High 1.1 1.2 1.4 1.7 | ns UNYL Pad to Y Low 1.3 1.4 1.7 2.0 ns tiNGH G to Y High 2.0 2.3 2.7 3.2 ns tinGL G to Low 2.6 3.0 3.5 42 ns Input Module Predicted Routing Delays trp FO=1 Routing Delay 2.9 3.3 3.9 47 ns trp2 FO=2 Routing Delay 3.2 3.6 43 5.2 ns tps FO=3 Routing Delay 3.8 4.2 5.0 6.0 ns tips FO=4 Routing Delay 4.1 46 5.4 6.5 ns trps FO=8 Routing Delay 5.2 5.9 6.9 8.3 ns Global Clock Network tcKH Input Low to High FO = 32 .1 5.8 6.8 8.2 ns FO = 256 5.7 6.5 7.6 9.1 tox Input High to Low FO = 32 5.0 5.7 6.7 8.0 ns FO = 256 5.7 6.5 7.6 9.1 tpwH Minimum Pulse Width FO = 32 2.6 3.0 3.5 4.2 ns High FO = 256 2.7 3.1 3.6 4.3 tpwe Minimum Pulse Width Low FO = 32 2.6 3.0 3.5 4.2 ns FO = 256 2.7 3.1 3.6 43 tcksw Maximum Skew FO = 32 0.8 0.9 1.0 1.2 ns FO = 256 0.8 0.9 1.0 1.2 tsuext Input Latch External Setup FO = 32 0.0 0.0 0.0 0.0 ns FO = 256 0.0 0.0 0.0 0.0 tuext Input Latch External Hold FO = 32 2.6 2.9 3.4 4.1 ns FO = 256 3.2 3.7 43 5.2 tp Minimum Period FO = 32 5.4 6.1 7.2 8.6 ns FO = 256 5.6 6.3 74 8.9 fax Maximum Frequency FO = 32 225.0 200.0 170.0 115.0 MHz FO = 256 200.0 180.0 155.0 105.0 Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-36Integrator Series FPGAs - 1200XL and 3200DX Famites A1225XL Timing Characteristics (continued) (Worst-Case Commercial Conditions) Output Module Timing -2Speed | -1Speed | Std Speed | 3.3V Speed Parameter Description Min. Max. | Min. Max. | Min. Max.| Min. Max. | Units TTL Output Module Timing! towH Data to Pad High 3.8 43 5.0 6.0 ns tou Data to Pad Low 41 4.6 5.4 6.5 ns tENZH Enable Pad Z to High 3.8 4.3 5.0 6.0 ns TENZL Enable Pad Z to Low 41 47 5.5 6.5 ns tennz Enable Pad High to Z 5.4 6.1 7.2 8.6 | ns 3 teNLz Enable Pad Low to Z 5.4 6.1 7.2 8.6 ns 5 toLy G to Pad High 42 48 56 6.7 | ns 2 tent G to Pad Low 47 5.4 6.3 7.6 | ns tico /O Latch Clock-Out (pad-to-pad), 64 clock loading 9.0 10.0 12.0 14.4 ns taco Array Clock-Out (pad-to-pad), 64 clock loading 12.8 14.4 17.0 20.4 } ns qty Capacitive Loading, Low to High 0.04 0.04 0.05 0.06 | ns/pF OTH Capacitive Loading, High to Low 0.05 0.06 0.07 0.08 | ns/pF CMOS Output Module Timing! toLH Data to Pad High 48 5.4 6.4 7.7 ns toHL Data to Pad Low 3.4 3.8 4.5 5.4 ns tenzH Enable Pad Z to High 3.8 4.3 5.0 6.0 ns tenzi Enable Pad Z to Low 41 47 5.5 6.6 ns tenNHz Enable Pad High to Z 5.4 6.1 7.2 8.6 ns tenLz Enable Pad Low to Z 5.4 6.1 7.2 86 ns tetH G to Pad High 4.2 48 5.6 6.7 ns teu G to Pad Low 4.7 5.4 6.3 76 ns tico VO Latch Clock-Out (pad-to-pad), 64 clock loading 10.7 11.8 14.2 17.0 ns taco Array Clock-Out (pad-to-pad), 64 clock loading 15.0 17.0 20.0 24.0 ns dtuH Capacitive Loading, Low to High 0.05 0.06 0.07 0.08 | ns/pF OTHL Capacitive Loading, High to Low 0.05 0.05 0.06 0.07 | ns/pF Notes: I. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note on page 4-125. 1-37'S)/ A1240XL Timing Characteristics (Worst-Case Commercial Conditions, Veg = 4.75 V, Ty = 70C) Logic Module Propagation Delays -2Speed | -1Speed | Std Speed | 3.3V Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Units tppy Single Module 2.6 3.0 3.5 4.2 ns tco Sequential Clk to Q 2.6 3.0 3.5 4.2 ns teo Latch G to Q 2.6 3.0 3.5 42 ns trs Flip-Flop (Latch) Reset to Q 2.6 3.0 3.5 42 ns Predicted Routing Delays trp1 FO=1 Routing Delay 1.1 1.2 1.4 1.7 ns tape FO=2 Routing Delay 1.3 1.4 1.7 2.0 ns taps FO=3 Routing Delay 1.7 1.9 2.2 2.6 ns taps FO=4 Routing Delay 2.3 2.6 3.0 3.6 ns trpa FO=8 Routing Delay 3.4 3.8 4.5 5.4 ns Sequential Timing Characteristics: * tsup Flip-Flop (Latch) Data Input Setup 0.4 0.4 0.5 0.6 ns tuo Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 ns tsuENA Flip-Flop (Latch) Enable Setup 08 0.9 1.0 1.2 ns tHeNA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 ns tweika Flip-Flop (Latch) Clock Active Pulse Width 3.4 3.8 45 5.4 ns twasyn Flip-Flop (Latch) Asynchronous Pulse Width 3.4 3.8 45 5.4 ns ta Flip-Flop Clock Input Period 6.8 7.7 9.1 10.9 ns tinH Input Buffer Latch Hold 0.0 0.0 0.0 0.0 ns tnsu Input Buffer Latch Setup 0.3 0.4 0.4 0.5 ns touTtH Output Buffer Latch Hold 0.0 0.0 0.0 0.0 ns toutsu Output Buffer Latch Setup 0.3 0.4 0.4 0.5 ns fraax Flip-Flop (Latch) Clock Frequency 215.0 190.0 160.0 105.0 | MHz Notes: 1 For duat-module macros use tyy, + tens + tppy tea + bent + lpn OF tppy + tens + typyy whichever is appropriate. 2. Routing delays are for typical designs across: warst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or sinuidation is required lo determine actual worst-case performance, Past-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3 Data applies ta macros based on the S-modile, Timing parameters for sequential macros constructed from C-modutes can be obtained from the DirectTime Analyzer wtitity. 4. Setup and hold tiniug parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing paramelers must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input sublracts (adds) to the internal setup (hold } time. 5 Vee = 320 V for 3.3V specifications, 1-38Integrator Series FPGAs - 1200XL and 3200DX Famiies A1240XL Timing Characteristics (continued) (Worst-Case Commercial Conditions) Input Module Propagation Delays -2 Speed -1 Speed [| Std Speed | 3.3V Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Units tinvH Pad to Y High 11 1.2 1.4 1.7 ns tinyL Pad to Y Low 1.3 1.4 1.7 2.0 ns tINGH G to Y High 2.0 2.3 27 3.2 ns tinal G to Y Low 2.6 3.0 3.5 4.2 as Input Module Predicted Routing Delays taba FO=1 Routing Delay 2.9 3.3 3.9 4.7 ns o tinpe FO=2 Routing Delay 3.4 3.8 4.5 5.4 ns 3 tinD3 FO=3 Routing Delay 3.8 43 5.1 6.1 ns > tinpa FO=4 Routing Delay 44 47 5.5 6.6 ns t taps FO=8 Routing Delay 56 6.3 7.4 8.9 | ns Global Clock Network toKH Input Low to High FO = 32 5.1 5.8 6.8 8.2 ns FO = 256 5.7 6.5 7.6 9.1 tox. input High to Low FO = 32 5.0 5.7 6.7 80} FO = 256 5.7 6.5 7.6 9.1 tewr Minimum Pulse Width FO = 32 2.7 31 3.6 43 ns High FO = 256 29 3.3 3.9 47 towe Minimum Pulse Width Low FO = 32 27 3.1 3.6 4.3 ns FO = 256 2.9 3.3 3.9 47 tcoxsw Maximum Skew FO = 32 0.8 0.9 1.0 1.2 ns FO = 256 0.8 0.9 1.0 1.2 tsuext input Latch External Setup FO = 32 0.0 0.0 0.0 0.0 ns FO = 256 0.0 0.0 0.0 0.0 tuext Input Latch External Hold FO = 32 2.6 2.9 3.4 41 ns FO = 256 3.2 3.7 43 5.2 tp Minimum Period FO = 32 5.6 6.3 7.4 8.9 ns FO = 256 6.0 6.8 8.0 9.6 fmax Maximum Frequency FO = 32 215.0 490.0 160.0 105.0 MHz FO = 256 195.0 170.0 144.0 95.0 Note: 1 These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to dns, Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case 1-39S/ A1240XL Timing Characteristics (continued) (Worst-Case Commercial Conditlons) Output Module Timing -2Speed | -1Speed | StdSpeed | 3.3V Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Units TTL Output Module Timing! toy Data to Pad High 3.8 4.3 5.0 6.0 ns tone Data to Pad Low 41 4.6 5.4 6.5 ns tenzH Enable Pad Z to High 3.8 43 5.0 6.0 ns tenze Enable Pad Z to Low 4.1 4.7 5.5 6.6 ns tenuz Enable Pad High to Z 5.4 6.1 72 8.6 ns tencz Enable Pad Low to Z 5.4 61 7.2 8.6 ns taux G to Pad High 4.2 4.8 5.6 6.7 ns tent G to Pad Low 4.7 5.4 63 7.6 ns {ico 1/0 Latch Clock-Out (pad-to-pad), 64 clock loading 9.2 10.5 12.3 14.8 | ns taco Array Clock-Out (pad-to-pad), 64 clock loading 12.9 14.6 17.2 20.6 ns dri Capacity Loading, Low to High 0.04 0.04 0.05 0.06 | ns/pF rue Capacity Loading, High to Low 0.05 0.06 0.07 0.08 | ns/pF CMOS Output Module Timing! {oLH Data to Pad High 4.8 5.4 6.4 77 ns tou Data to Pad Low 3.4 3.8 45 5.4 ns tenzH Enable Pad Z to High 3.8 43 5.0 6.0 ns tenze Enable Pad Z to Low 4.1 4.7 5.5 6.6 ns tenHz Enable Pad High to Z 5.4 6.1 7.2 8.6 ns tencz Enable Pad Low to Z 5.4 6.1 7.2 8.6 ns tauy G to Pad High 4.2 48 5.6 67 ns tout G to Pad Low 4.7 5.4 6.3 7.6 ns tico \/O Latch Clock-Out (pad-to-pad), 64 clock loading 10.9 12.4 14.5 17.4 ns taco Array Clock-Out (pad-to-pad), 64 clock loading 15.2 17.2 20.3 24.4 ns dtiy Capacity Loading, Low to High 0.05 0.06 0.07 0.08 | ns/pF dry Capacity Loading, High to Low 0.05 0.05 0.06 0.07 | ns/pF Notes: 1 Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note on page 4-125. 1-40Integrator Series FPGAs - 1200XL and 3200DX Famiies A3265DX Timing Characteristics (Worst-Case Commercial Conditions) Advanced Information Preliminary Information Logic Module Propagation Delays -2'Speed | -1'Speed | Std Speed | 3.3V Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Units Combinatorial Functions tpp Internal Array Module Delay 2.6 3.0 3.5 4.2 ns tppp Internal Decode Module Delay 2.9 3.3 3.9 4.7 ns . Predicted Routing Delays 2 tapi FO=1 Routing Delay 1.3 1.4 1.7 2.0 ns = tape FO=2 Routing Delay 1.8 2.0 2.4 2.9 ns & tro3 FO=3 Routing Delay 2.2 2.5 2.9 3.5 ns taps FO=4 Routing Detay 2.6 3.0 3.5 4.2 ns taps FO=8 Routing Delay 5.0 5.7 6.7 8.0 ns troop Decode-to-Output Routing Delay 0.3 0.4 0.5 0.6 ns Sequential Timing Chatacteristics* 4 tco Flip-Flop Clock-to-Output 25 3.0 3.5 4.2 ns teo Latch Gate-to-Output 2.5 3.0 3.5 4.2 ns tsu Flip-Flop (Latch) Setup Time 0.3 0.4 0.5 0.6 ns ty Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 0.0 ns tro Flip-Flop (Latch) Reset to Output 2.5 3.0 3.5 42 ns tsueNa Flip-Flop (Latch) Enable Setup 0.8 09 1.0 1.2 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 ns tweoLka Flip-Flop (Latch) Clock Active Pulse Width 3.7 4.2 49 5.9 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 3.7 4.2 49 5.9 ns Notes: For dual-module macros, use tpy; + tens + trp feo + taps + tppn OF tpp; + beni + tsup whichever is appropriate. 2 Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-roule timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3 Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G inpat subtracts (adds) to the internal setup (hold) time. 5. Voc = 3.0 V for 3.2V specifications. 1-41Sy/ A3265DX Timing Characteristics (continued) (Worst-Case Commercial Conditions) Advanced Information Preliminary Information Input Module Propagation Delays -2Speed | -1Speed | Std Speed | 3.3V Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Units tinpy Input Data Pad to Y 1.3 1.4 1.7 2.0 ns tinco Input Latch Gate-to-Output 2.6 3.0 3.5 42 ns tiny Input Latch Hold 0.0 0.0 0.0 0.0 ns tinsu Input Latch Setup 0.3 0.3 0.4 0.5 ns tiLa Latch Active Pulse Width 3.7 4.2 49 5.9 ns Input Module Predicted Routing Delays! tiapy FO=1 Routing Delay 3.2 3.7 43 5.2 ns tiaoe FO=2 Routing Delay 3.7 4.2 49 5.9 ns tino FO=3 Routing Delay 4.0 4.5 5.3 6.4 ns taba FO=4 Routing Delay 4.6 5.2 6.1 7.3 ns tinDSs FO=8 Routing Delay 6.6 7.5 8.8 10.6 ns Global Clock Network toKH Input Low to High FO=32 5.1 5.8 6.8 8.2 ns FO=256 5.7 6.5 7.6 9.1 ns tek Input High to Low FO=32 5.0 5.7 6.7 8.0 ns FOQ=256 5.7 6.5 76 9.1 ns tpw Minimum Pulse Width FO=32 2.5 3.0 3.5 4.2 ns FO=256 3.0 3.7 46 5.5 ns toxsw Maximum Skew FO=32 0.8 09 1.0 1.2 ns FO=256 0.8 09 1.0 1.2 ns tguext Input Latch External Setup FO=32 0.0 0.0 0.0 0.0 ns FO=256 0.0 0.0 0.0 0.0 ns tuext Input Latch External Hold FO=32 2.6 2.6 3.4 41 ns FO=256 3.2 3.2 43 5.2 ns tp Minimum Period (1/fmax) FO=32 45 6.0 7.0 8.4 ns FO=256 6.0 7.4 8.7 10.4 ns fax Maximum Datapath FO=32 200.0 167.0 143.0 120.0 | MHz Frequency FO=256 180.0 150.0 130.0 110.0 | MHz Note: 1 Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance, Post-route timing analysis ar simulation is required to determine actual worst-case performance,integrator Series FPGAs - 1200XL and 3200DX Familes A3265DX Timing Characteristics (continued) (Worst-Case Commercial Conditions) Advanced Preliminary Information Output Module Timing -2Speed | -1Speed | Std Speed | 3.3V Speed Parameter Description Min. Max. | Min. Max.| Min. Max. | Min. Max. | Units TTL Output Module Timing toLH Data to Pad High 3.7 43 5.0 6.0 ns toxL Data to Pad Low 3.9 4.6 5.4 6.5 ns tenzH Enable Pad Z to High 3.7 43 5.0 6.0 ns h tenzL Enable Pad Z to Low 4.0 47 5.5 6.6 ns : tennz Enable Pad High to Z 5.2 6.1 7.2 8.6 | ns a TENLZ Enable Pad Low to Z 5.2 6.1 7.2 8.6 ns {et G to Pad High 41 48 5.6 6.7 ns < toHL G to Pad Low 4.6 5.4 6.3 7.6 ns tisu \/O Latch Output Setup 0.3 0.3 0.4 0.5 ns tty VO Latch Output Hold 0.0 0.0 0.0 0.0 ns tico /O Latch Clock-Out (Pad-to-Pad) 32 /O 9.4 11.0 13.1 15.7 | ns taco ey Latch Clock-Out (Pad-to-Pad) 133 167 185 22 . . . . ns ttn Capacitive Loading, Low to High 0.03 0.04 0.05 0.06 | ns/pF dtu Capacitive Loading, High to Low 0.03 0.04 0.07 0.08 | ns/pF CMOS Output Module Timing! totx Data to Pad High 46 5.4 6.4 77 ns toHL Data to Pad Low 3.2 3.8 45 5.4 ns teNZzH Enable Pad Z to High 3.7 4.3 5.0 6.0 ns tenzL Enable Pad Z to Low 4.0 4.7 5.5 6.6 ns tenHz Enable Pad High to Z 5.2 6.1 7.2 8.6 ns tenLz Enable Pad Low to Z 5.2 6.1 7.2 8.6 ns teLH G to Pad High 41 48 5.6 6.7 ns toHL G to Pad Low 46 5.4 6.3 7.6 ns tisu VO Latch Setup 0.4 0.4 0.4 0.5 ns tiy VO Latch Hold 0.0 0.0 0.0 0.0 ns tico VO Latch Clock-Out (Pad-to-Pad) 32 I/O 11.1 13.0 15.5 18.6 | ns/pF taco array Latch Clock-Out (Pad-to-Pad} 157 185 os 362 . : . .2 | ns/pF GTLH Capacitive Loading, Low to High 0.05 0.06 0.07 0.08 | ns/pF tHe Capacitive Loading, High to Low 0.04 0.05 0.06 0.07 | ns/pF Notes: 1. Delays based on 35pF loading. 2 SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note on page 4-125. 1-43'S)/ A1280XL Timing Characteristics (Worst-Case Commercial Conditions, Vcc = 4.75 V, Ty = 70C) Logic Module Propagation Delays! ~2'Speed | -1'Speed | Std Speed | 3.3V Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Units tep1 Single Module 2.6 3.0 3.5 42 ns tco Sequential Clk to Q 2.6 3.0 3.5 42 ns teo Latch G to Q 2.6 3.0 3.5 42 ns tas Flip-Flop (Latch) Reset to Q 2.6 3.0 3.5 4.2 ns Predicted Routing Delays fap4 FO=1 Routing Delay 1.3 1.4 1.7 2.0 ns tape FO=2 Routing Delay 18 2.0 2.4 2.9 ns tapos FO=3 Routing Delay 2.2 2.5 2.9 3.5 ns taba FO=4 Routing Delay 2.6 3.0 3.5 4.2 ns tans FO=8 Routing Delay 5.0 5.7 6.7 8.0 ns Sequential Timing Characteristics? tsup Flip-Flop (Latch) Data Input Setup 0.4 0.4 0.5 0.6 ns tub Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 ns tsUENA Flip-Flop (Latch) Enable Setup 08 0.9 1.0 1.2 ns tuENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 ns tweLka Flip-Flop (Latch) Clock Active Pulse Width 3.7 43 49 5.9 ns TWASYN Flip-Flop (Latch) Asynchronous Pulse 3.7 43 Width 49 5.9 ns ta Flip-Flop Clock Input Period 8.0 8.7 10 12 ns tiny Input Buffer Latch Hold 0.0 0.0 0.0 0.0 ns tinsu Input Buffer Latch Setup 0.3 0.4 0.4 a5 ns touTH Output Buffer Latch Hold 0.0 0.0 0.0 0.0 ns toutsu Output Buffer Latch Setup 0.3 0.4 0.4 0.5 ns imax Flip-Flop (Latch) Clock Frequency 200.0 167.0 130.0 110.0 | MHz Notes: 1 For dual-modite macros, use ton, + tape + lop toot tant + lem OF Lop + dan + typ whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance, Post-route ining analysis or simadation is required to determine actual worst-case performance. Post-rowe ming is based on actual routing delay measurements performed on the device prior to shipment. 3 Data applies to macros based on the S-module. Timing parameters for sequential macros constructed fram C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters neust account for delay from ea external PAD signal to the G inputs. Delay from an external PAD signal to the @ input subtracts fadds) to the bilernal setup Chald ) time. 5 Vo = BV for 2.3V specifications. 1-44Integrator Series FPGAs - 1200XL and 3200DX Familes A1280XL Timing Characteristics (continued) (Worst-Case Commercial Conditions) Input Module Propagation Delays 2 Speed -1Speed | Std Speed | 3.3V Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Units thy Pad to Y High V1 1.2 1.4 1.7 ns tNYL Pad to Y Low 1.3 1.4 1.7 2.0 | ns tnew G to Y High 2.0 2.3 2.7 3.2 ns UNG@L Gto Low 2.6 3.0 3.5 42 ns Input Module Predicted Routing Delays trot FO=1 Routing Delay 3.2 3.7 43 5.2 | ns 3 tirpe FO=2 Routing Delay 3.7 42 49 5.9 ns s tiRD3 FO=3 Routing Delay 4.0 45 5.3 6.4 | ns tirps FO=4 Routing Delay 46 5.2 6.1 7.3 ns = tros FO=8 Routing Delay 6.6 75 8.8 10.6 ns Global Clock Network tcKH Input Low to High FO = 32 5.1 5.8 6.8 8.2 ns FO = 384 5.7 6.5 7.6 9.1 tox input High to Low FO = 32 5.0 5.7 6.7 8.0 ns FO = 384 5.7 6.5 7.6 9.1 tpwH Minimum Pulse Width FO = 32 3.2 3.5 43 5.2 ns High FO = 384 3.5 3.9 46 5.5 tpwe Minimum Pulse Width Low FO = 32 3.2 3.5 43 5.2 ns FO = 384 3.5 3.9 46 5.5 tcxksw Maximum Skew FO = 32 0.8 0.9 1.0 1.2 ns FO = 384 0.8 0.9 1.0 1.2 tsuexT Input Latch External Setup FO = 32 0.0 0.0 0.0 0.0 ns FO = 384 0.0 0.0 0.0 0.0 tuext input Latch External Hold FO = 32 2.6 2.9 3.4 41 ns FO = 384 3.2 3.7 43 5.2 tp Minimum Period FO = 32 6.5 7.4 8.7 10.4 ns FO = 384 7.2 8.0 96 11.5 fax Maximum Frequency FO = 32 200.0 167.0 143.0 120.0 MHz FO = 384 180.0 150.0 130.0 110.0 Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Rouling delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-45ea! A1280XL Timing Characteristics (continued) (Worst-Case Commercial Conditions) Output Module Timing -2Speed | -1Speed | StdSpeed | 3.3V Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Units TTL Output Module Timing! toy Data to Pad High 3.8 4.3 5.0 6.0 ns tou Data to Pad Low 4.1 46 5.4 6.5 ns tenzH Enable Pad Z to High 3.8 43 5.0 6.0 ns tenze Enable Pad Z to Low 41 47 5.5 6.6 ns tennz Enable Pad High to Z 5.4 61 7.2 8.6 ns tenLz Enable Pad Low to Z 5.4 6.1 7.2 8.6 ns tet G to Pad High 42 48 5.6 6.7 ns toHL G to Pad Low 47 5.4 6.3 7.6 ns ico 6a clack loading (pad-to-pad), 9.8 11.0 13.1 157 | ns taco 64 clock losding (pad-to-pad), 13.9 15.7 18.5 22.2 | ns dtp Capacitive Loading, Low to High 0.04 0.04 0.05 0.06 | ns/pF Ory Capacitive Loading, High to Low 0.05 0.06 0.07 0.08 | ns/pF CMOS Output Module Timing! tovy Data to Pad High 48 5.4 6.4 7.7 ns toute Data to Pad Low 3.4 3.8 45 5.4 ns tenzH Enable Pad Z to High 3.8 4.3 5.0 6.0 ns tenze Enable Pad Z to Low 4.1 47 6.5 6.6 ns tenyz Enable Pad High to Z 5.4 6.1 7.2 8.6 ns tenLz Enable Pad Low to Z 5.4 6.1 7.2 8.6 ns tety G to Pad High 42 48 5.6 6.7 ns tou G to Pad Low 47 5.4 6.3 76 ns tico VO Latch Clock-Out (pad-to-pad), 116 13.0 155 186 ns 64 clock loading taco Array Clock-Out (pad-to-pad), 16.4 18.5 21.8 26.2 | ns 64 clock loading Gtty Capacitive Loading, Low to High 0.05 0.06 0.07 0.08 | ns/pF OTH Capacitive Loading, High to Low 0.05 0.05 0.06 0.07 | ns/pF Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note on page 4-125. 1-46Integrator Series FPGAs - 1200XL and 3200DX Familes A32140DX Timing Characteristics {Worst-Case Commercial Conditions) Advanced information Preliminary Information Logic Module Propagation Delays -2 Speed +1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units Combinatorial Functions tpp Internal Array Module Delay 2.6 3.0 3.5 ns tepp Internal Decode Module Delay 29 3.3 3.9 ns Predicted Routing Delays? s tap1 FO=1 Routing Delay 1.3 1.4 1.7 ns = tape FO=2 Routing Delay 2.0 2.2 2.6 ns a taps FO=3 Routing Delay 29 3.3 3.8 ns = tapa FO=4 Routing Delay 3.5 3.9 4.6 ns taps FO=8 Routing Delay 6.3 7A 8.4 ns trop Decode-to-Output Routing Delay 0.3 0.4 0.5 ns Sequential Timing Characteristics 4 tco Flip-Flop Clock-to-Output 2.6 3.0 3.5 ns teo Latch Gate-to-Output 2.6 3.0 3.5 ns tsu Flip-Flop (Latch) Setup Time 0.4 0.4 0.5 ns ty Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 ns tRo Flip-Flop (Latch) Reset to Output 2.6 3.0 3.5 ns ISUENA Flip-Flop (Latch) Enable Setup 0.8 0.9 1.0 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 ns tweLkA Flip-Flop (Latch) Clock Active Pulse Width 3.7 4.2 49 ns tWasyN Flip-Flop (Latch) Asynchronous Pulse Width 3.7 4.2 49 ns Notes: 1 For dual-module macros, use lp; + trp, + Lepy boo + Crp + teow OF Lpp t laps + lsun whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3 Data applies to macros based on. the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DireciTime Analyzer utility. 4 Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 1-47A32140DX Timing Characteristics (continued) (Worst-Case Commercial Conditions) Advanced Information Preliminary Information Input Module Propagation Delays +2 Speed 1 Speed Std Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Units tinpy Input Data Pad to Y 1.3 1.4 1,7 ns tinao Input Latch Gate-to-Output 2.6 3.0 3.5 ns tinH Input Latch Hold 0.0 0.0 0.0 ns tnsu Input Latch Setup 0.3 0.3 0.4 ns tila Latch Active Pulse Width 3.7 4.2 49 ns input Module Predicted Routing Delays' tiro1 FO=1 Routing Delay 3.2 3.7 4.3 ns tirpe FO=2 Routing Delay 3.7 4.2 49 ns bros FO=3 Routing Delay 4.0 45 5.3 ns trp FO=4 Routing Delay 46 .2 6.1 ns tinps FOQ=8 Routing Delay 6.6 7.5 8.8 ns Global Clock Network tekH Input Low to High FO=32 5.1 5.8 6.8 ns FO=486 5.7 6.5 7.6 ns toKL Input High to Low FO=32 5.0 5.7 6.7 ns FO=486 5.7 6.5 7.6 ns tpw Minimum Pulse Width FO=32 3.2 3.7 4.3 ns FO=486 3.5 3.9 4.6 ns tcxsw Maximum Skew FO=32 0.8 0.9 1.0 ns FO=486 0.8 0.9 1.0 ns tsuext Input Latch External Setup FO=32 0.0 0.0 0.0 ns FO=486 0.0 0.0 0.0 ns tuext Input Latch External Hold FOQ=32 2.6 29 3.4 ns FO=486 3.2 3.7 4.3 ns tp Minimum Period (4/fmax} FO=32 6.5 7.4 8.7 ns FO=486 7.2 8.2 9.6 ns fax Maximum Datapath Frequency FO=32 153.0 133.0 115.0 | MHz FO=486 140.0 123.0 105.0 | MHz Note: 1, Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. 1-48Integrator Series FPGAs - 1200XL and 3200DX Familes A32140DX Timing Characteristics (continued) (Worst-Case Commercial Conditions) Advanced Information Preliminary Information Output Module Timing +2 Speed -1' Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units TTL Output Module Timing! totH Data to Pad High 3.7 4.3 5.0 ns tout Data to Pad Low 3.9 46 5.4 ns TeNZH Enable Pad Z to High 3.7 43 5.0 ns - fenze Enable Pad Z to Low 4.0 47 5.5 ns : teNHZ Enable Pad High to Z 5.2 6.1 7.2 ns a tentz Enable Pad Low to Z 5.2 6.1 7.2 ns fotH G to Pad High 41 48 5.6 ns teu G to Pad Low 46 5.4 6.3 ns tusu V/O Latch Output Setup 0.3 0.3 0.4 ns thy VO Latch Output Hold 0.0 0.0 0.0 ns tico VO Latch Clock-Out (Pad-to-Pad) 32 /O 9.4 11.0 13.1 ns taco Array Latch Clock-Out (Pad-to-Pad) 32 /O 13.3 15.7 18.5 ns tty Capacitive Loading, Low to High 0.03 0.04 0.05 | ns/pF OTH Capacitive Loading, High to Low 0.03 0.04 0.07 | ns/pF CMOS Output Module Timing! toLH Data to Pad High 4.6 5.4 6.4 ns toHL Data to Pad Low 3.2 3.8 45 ns tenzH Enable Pad Z to High 3.7 4.3 5.0 ns tenze Enable Pad Z to Low 4.0 47 5.5 ns tennz Enable Pad High to Z 5.2 6.1 7.2 ns tenLz Enable Pad Low to Z 5.2 6.1 7.2 ns teLH G to Pad High 41 48 5.6 ns teHL G to Pad Low 46 5.4 6.3 ns tisu 1/0 Latch Setup 0.4 0.4 0.4 ns ti VO Latch Hold 0.0 0.0 0.0 ns tico \/O Latch Clock-Out (Pad-to-Pad) 32 I/O 11.1 13.0 15.6 | ns/pF taco Array Latch Clock-Out (Pad-to-Pad) 32 /O 15.7 18.5 21.8 | ns/pF Otty Capacitive Loading, Low to High 0.05 0.06 0.07 | ns/pF dtu Capacitive Loading, High to Low 0.04 0.05 0.06 | ns/pF Notes: 1. Delays based on 35 pF loading. 2 SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note on page 4-125. 1-49S/ A32200DX Timing Characteristics (Worst-Case Commercial Conditions) Advanced Information Logic Module Propagation Delays -2 Speed -1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units Combinatorial Functions tpp Internal Array Module Delay 2.6 3.0 3.5 ns tppp Internal Decode Module Delay 2.9 3.3 3.9 ns Predicted Module Routing Delays tapi FO=1 Routing Delay 2.0 2.2 2.6 ns tape FO=2 Routing Delay 2.5 2.9 3.4 ns tap3 FO=3 Routing Delay 2.9 3.3 3.8 ns troa FO=4 Routing Delay 3.4 3.9 46 ns tros FO=8 Routing Delay 6.8 7.7 91 ns trop Decode-to-Output Routing Delay 0.3 0.4 0.5 ns Sequential Timing Characteristics tco Flip-Flop Clock-to-Output 26 3.0 3.5 ns teo Latch Gate-to-Output 2.6 3.0 3.5 ns tsy Flip-Flop (Latch) Setup Time 0.4 0.4 0.5 ns ty Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 ns tro Flip-Flop (Latch) Reset to Output 2.6 3.0 3.5 ns tsuENA Flip-Flop (Latch) Enable Setup 0.8 0.9 1.0 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 ns IWCLKA Flip-Flop (Latch) Clock Active Pulse Width 3.7 4.2 4.9 ns twasvn Flip-Flop (Latch) Asynchronous Pulse Width 3.7 4.2 49 ns 1-50Integrator Series FPGAs - 1200XL and 3200DX Familes A32200DX Timing Characteristics (continued) (Worst-Case Commercial Conditions) Advanced Information Logic Module Timing -2 Speed -1' Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units Synchronous SRAM Operations tac Read Cycle Time 7.5 8.5 10.0 ns twe Write Cycle Time 75 85 10.0 ns tACKHL Clock High/Low Time 3.8 4.3 5.0 ns taco Data Valid After Clock High/Low 3.8 4.3 5.0 ns 8 taosu Address/Data Setup Time 1.8 2.0 24 ns & tao Address/Data Hold Time 0.0 0.0 0.0 ns > tRENSU Read Enable Setup 0.8 0.9 1.0 ns E tRENH Read Enable Hold 0.4 0.4 0.5 ns twENsU Write Enable Setup 29 3.2 3.8 ns tWENH Write Enable Hold 0.0 0.0 0.0 ns tBENS Block Enable Setup 29 3.3 3.9 ns tBeENH Block Enable Hold 0.0 0.0 0.0 ns Asynchronous SRAM Operations trep Asynchronous Access Time 9.0 10.2 12.0 ns tapapv Read Address Valid 9.8 11.0 13.0 ns tapsu Address/Data Setup Time 1.8 2.0 2.4 ns tabH Address/Data Hold Time 0.0 0.0 0.0 ns tRENSUA Read Enable Setup to Address Valid 0.8 0.9 1.0 ns tRENHA Read Enable Hold 0.4 0.4 0.5 ns twensu Write Enable Setup 29 3.2 3.8 ns tWENH Write Enable Hold 0.0 0.0 0.0 ns tpoH Data Out Hold Time 1.4 1.5 1.8 ns 1-51Sy A32200DX Timing Characteristics (continued) (Worst-Case Commercial Conditions) Advanced Information Input Module Propagation Delays ~2' Speed -1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units tinpy Input Data Pad to Y 1.3 1.4 17 ns tingo Input Latch Gate-to-Output! 26 3.0 3.5 ns tinh input Latch Hold! 0.0 0.0 0.0 ns tinsu Input Latch Setup 0.3 0.3 0.4 ns tila Latch Active Pulse Width! 3.7 42 49 ns Input Module Predicted Routing Delays tapt FO=1 Routing Delay 3.2 3.7 43 ns tiap2 FO=2 Routing Delay 3.7 4.2 49 ns taps FO=3 Routing Delay 4.0 45 5.3 ns tlapa FO=4 Routing Delay 4.6 5.2 6.1 ns tiapa FO=8 Routing Delay 6.6 75 8.8 ns Global Clock Network teKH Input Low to High FOQ=32 5.1 5.8 6.8 ns FO=635 5.7 6.5 76 ns tox. Input High to Low FO=32 5.0 5.8 6.7 ns FO=635 5.7 6.5 7.6 ns tpwH Minimum Pulse Width High FOQ=32 3.2 3.7 4.3 ns FO=635 3.5 41 46 ns tewe Minimum Pulse Width Low FO=32 3.2 3.7 4.3 ns FO=635 3.5 41 4.6 ns texsw Maximum Skew FO=32 0.8 0.9 1.0 ns FO=635 0.8 0.9 1.0 ns tsuext Input Latch External Setup FO=32 0.0 0.0 0.0 ns FO=635 0.0 0.0 0.0 ns tuext Input Latch External Hold FO=32 2.6 29 3.4 ns FO=635 3.2 3.7 4.3 ns tp Minimum Period (1/fmax} FOQ=32 6.5 7.4 8.7 ns FO=635 72 8.2 9.6 ns fumax Maximum Datapath Frequency FO=32 153.0 133.0 115.0 | MHz FO=635 140.0 123.0 105.0 | MHz Note: 1 Routing delays are for typical designs across worst-case operating conditions, These parameters shotdd be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. 1-52integrator Series FPGAs - 1200XL and 3200DX Familes A32200DX Timing Characteristics (continued) (Worst-Case Commercial Conditions} Advanced Information Output Module Timing -2 Speed -1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units TTL Output Module Timing! touH Data to Pad High 3.7 4.3 5.4 ns toHL Data to Pad Low 3.9 46 5.4 ns tenzH Enable Pad Z to High 3.7 43 5.0 ns tenzL Enable Pad Z to Low 4.0 47 5.5 ns 3 tennz Enable Pad High to Z 5.2 6.1 7.2 ns s tentz Enable Pad Low to Z 5.2 6.1 7.2 ns tet G to Pad High 41 48 5.6 ns < tee G to Pad Low 46 5.4 6.3 ns = tLsu VO Latch Output Setup 0.3 0.3 0.4 ns tty VO Latch Output Hold 0.0 0.0 0.0 ns tLco V/O Latch Clock-Out (Pad-to-Pad) 32 I/O 9.4 11.0 13.1 ns taco Array Latch Clock-Out (Pad-to-Pad) 32 /O 13.3 15.7 18.5 ns qty Capacitive Loading, Low to High 0.03 0.04 0.05 | ns/pF OTH Capacitive Loading, High to Low 0.03 0.04 0.07 | ns/pF twoo Hard-Wired Wide Decode Output 0.05 ns CMOS Output Module Timing! tol Data to Pad High 46 5.4 6.4 ns {DHL Data to Pad Low 3.2 3.8 45 ns tenzy Enable Pad Z to High 3.7 4.3 5.0 ns tenze Enable Pad Z to Low 4.0 47 5.5 ns tenuz Enable Pad High to Z 5.2 6.1 7.2 ns tentz Enable Pad Low to Z 5.2 6.1 7.2 ns teuy G to Pad High 4.1 48 5.6 ns tout G to Pad Low 46 5.4 6.3 ns tisu \/O Latch Setup 0.4 0.4 0.4 ns thy VO Latch Hald 0.0 0.0 0.0 ns tLco VO Latch Clock-Out (Pad-to-Pad) 32 I/O W141 13.0 15.5 | ns/pF taco Array Latch Clock-Out (Pad-to-Pad) 32 I/O 15.7 18.5 21.8 | ns/pF tty Capacitive Loading, Low to High 0.05 0.06 0.07 | ns/pF GtHL Capacitive Loading, High to Low 0.04 0.05 0.06 | ns/pF twoo Hard-Wired Wide Decode Output 0.04 0.05 0.06 | ns/pF Notes: 1 Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note on page 4-125. 1-53a Package Pin Assignments 84-Pin PLCC Package (Top View) ) OORM OPE A OA T \ 84-Pin PLCC HOODOO OOOAO AO UJUUUUUUUUUUUUUUUUUU UUUELULUUUUULUUUUUEUUU 1-54Integrator Series FPGAs - 1200XL and 3200DX Familes 84-Pin PLCC Package Pin A1225XL A1240XL A3265DX A1280XL Number Function Function Function Function 2 CLKB,/O CLKB,I/O CLKB,VO CLKB,VO 4 PRB,VO PRB,VO PRB,|/O PRB, I/O 5 vO vO VO (WD) vo 6 GND GND GND GND 8 VO vO /O (WD) vO 9 vO vO VO (WD) VO 10 DCLK,i/O DCLK,VO DCLK,I/O DCLK,VO 12 MODE MODE MODE MODE 3 22 VCC Vcc vec vec 23 VCC vcc VCC vec & 28 GND GND GND GND <= 38 vO vO VO (WD) vO 39 Ze) vO VO (WD) vO 43 vcc VCC VCC VCC 44 vO fe) VO (WD) vO 46 vO vO VO (WD) vO 47 vO VO VO (WD) vO 49 GND GND GND GND 63 GND GND GND GND 64 vec VCC VCC vcc 65 vcc VCC VCC VCC 70 GND GND GND GND 76 SDI,VO SDI,O SDI,VO SDI,VO 78 vO 1) vO (WD) i) 79 vO vo VO (WD) VO 80 vO VO 1/0 (WD) vO B1 PRA,VO PRA,|/O PRA,V/O PRA,|/O 83 CLKA,I/O CLKA,VO CLKA,V/O CLKA,VO 84 VCC VCC vcc VCC Notes: 1 YO (WD): Denotes 1/0 pin with an associated Wide Decode Module 2. Wide Decode 1/0 (WD) can also be general purpose user 1/0 3 NC: Denotes No Connection 4 Allunlisted pin numbers are user [/0's 5. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.Sy/ Package Pin Assignments (continued) 100-pin PQFP Package, 100-pin VQFP Package (Top View) O O A LO 100-Pin VQFP DOO POO ROO UUUUUUU UU UU UU UU UU UU UU UULUUUUUUUUULUUUUU UU 1-56Integrator Series FPGAs - 1200XL and 3200DX Familes 100-pin PQFP Package, 100-pin VQFP Package A1225XL- A1225XL- A1240XL- A1225XL- A1225XL- A1240XL- Pin PQ100 VQ100 PQ100 Pin PQ100 vQ100 PQ100 Number Function Function Function Number = Function Function Function 2 DCLK, VO MODE DCLK, 1/0 64 GND vcc GND 4 MODE vO MODE 65 vec Vcc vec 7 vo GND VO 66 vec VO VCC 9 GND vO GND 67 vcc vO vcc 14 vo VCC vO 70 vO GND VO 15 vO vcc vO 72 GND vO GND 16 vcc vO VCC 77 vO SDI, /O vO 17 vcc vO VCC 79 SDI, /O vO SDI, 0 & 20 vO GND vO 82 vO GND vO 5 22 GND vO GND a4 GND vO GND & 32 vo GND vO 85 vO PRA, I/O vO 34 GND vO GND 87 PRA, I/O CLKA, I/O PRA, /O 38 vO VCC VO 88 vO vcc vO 40 Vcc vO VCC 89 CLKA, VO VO CLKA, I/O 44 vO GND vO 90 vcc CLKB, I/O VCC 46 GND vO GND 92 CLKB, VO - PRB, V0 CLKB, I/O 55 vO GND VO 94 PRB, VO GND PRB, /O 57 GND vO GND 96 GND VO GND 62 vO GND vO 100 vO DCLK,VO VO 63 vO vec vO Notes: I. NC: Denotes No Connection 2. Alluntisted pin numbers are user 10's 3. MODE should be terminated lo GND through a 10K resistor lo enable Actionprobe usage; otherwise it can be terminated directly ta GND. 1-57S)/ Package Pin Assignments (continued) 144-Pin PQFP Package (Top View) Aaa ipmiitsscts S| | i ti 7 144-Pin PQFP 144 TMT hey r | all HH | AMIIntegrator Series FPGAs - 1200XL and 3200DX Familes 144-Pin PQFP Package Pin Number A1240XL Function Pin Number A1240XL Function 2 MODE 89 VCC 9 GND 90 Vcc 10 GND 91 voc 11 GND 92 Vcc 18 Vcc 93 Vcc 19 vec 100 GND 20 voc 101 GND 21 VCC 102 GND . 28 GND 110 SDI, VO & 29 GND 116 GND 30 GND 117 GND 3 44 GND 118 GND 45 GND 123 PRA, I/O 46 GND 125 CLKA, /O 54 voc 126 VCC 55 VCC 127 VCC 56 vcc 128 Vcc 64 GND 130 CLKB, VO 65 GND 132 PRB, \/O 79 GND 136 GND 80 GND 137 GND 81 GND 138 GND 88 GND 144 DCLK, /O Notes: 1 NG: Denotes No Connection 2 Allunlisted pin numbers are user 0's 3 MODE should be terminated ta GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-59(Sy/ Package Pin Assignments (continued) 160-pin PQFP Package (Top View) A Lie 1O Su GUL ee Le 160-Pin PQFP \ : EE Noles: 1 YO(WD): Denotes I/0 pin with an associated Wide Decode Module 2. Wide Decode 1/0 (WD) can also be general purpose user I/O 3. NC: Denotes No Connection 4. All unlisted pin numbers are user 1/0's 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.Integrator Series FPGAs - 1200XL and 3200DX Familes 160-Pin PQFP Package Pin A3265DX A1280XL A32140DX Pin A3265DX A1280XL A32140DX Number Function Function Function Number Function Function Function 2 DCLK,V/O DCLK,I/O DCLK,I/O 80 GND GND GND 4 Vo vo VO (WD) 82 vO VO TDO, VO 5 VO (WD) vo VO (WD) 83 vo VO VO (WD) 6 vcc VCC vec 84 vO Vo VO (WD) 7 VO (WD) vo vO 86 VCG vec vcc 14 GND GND GND 87 VO (WD) vo vo 13 VO (WD) vo VO (WD) 88 VO (WD) vO VO (WD) 14 VO (WD) vo VO (WD) 89 GND GND GND 16 PRB,VO PRB,I/O PRB,I/O 92 VO (WD) vo vO 18 CLKB,I/O CLKB,VO CLKB,IVO 93 VO (WD) vO VO 20 Vcc vcc vcc 96 VO (WD) vO VO (WD) 21 CLKA,I/O CLKA,I/O CLKA,VO 97 VO (WD) vO vO 23 PRA,I/O PRA,VO PRA,VO 98 Vcc VCC vcc 24 vo vo VO (WD) 99 GND GND GND 25 VO (WD) vo VO (WD) 106 VO (WD) vO VO (WD) 26 VO (WD) vo vO 107 VO (WD) vO VO (WD) 29 VO (WD) He) VO (WD) 109 GND GND GND 30 GND GND GND 111 VO (WD) Vo VO (WD) 31 VO (WD) Vo VO (WD) 112 VO (WD) Vo VO (WO) 34 /O (WD) vO vO 114 Vcc vcc vcc 35 VCC Vcc vec 115 vO vo VO (WD) 36 V/O (WD) vo VO (WD) 116 vo He) VO (WD) 37 VO vO VO (WD) 118 VO VO TDI, VO 38 SDI,V/O SDI,V/O SDI,V/O 119 vO vo TMS, I/O 40 GND GND GND 120 GND GNO GND 44 GND GND GND 125 GND GND GND 49 GND GND GND 130 GND GND GND 54 VCC vec vec 135 vcc VCC vec 57 vcc VCC VCC 138 vec vcc vcoc 58 vcc vcc VCC 139 vcc VCC VCC 59 GND GND GND 140 GND GND GND 60 vec VCC VCC 145 GND GND GND 61 GND GND GND 150 VCC vcc vcc 62 vO vO TCK, I/O 155 GND GND GND 64 GND GND GND 159 MODE MODE MODE 69 GND GND GND 160 GND GND GND 1-61 Integrator(Sy/ Package Pin Assignments (continued) 208-Pin PQFP Package, 208-pin RQFP Package (Top View) EE 208-Pin PQFP 208-Pin RQFP Notes: 1 10 (WD) : Denotes /0 pin unth an associated Wide Decode Module 2. Wide Decode 1/0 (WD) can alsu be general purpose user 1/0 3. NC: Denotes No Connection 4. All unlisted pin numbers are user 1/0s 5. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 6. RQFP has an exposed circular metal heatsink on the top surface. 1-62Integrator Series FPGAs ~ 1200XL and 3200DX Familes 208-Pin PQFP Package, 208-pin RQFP Package A32200DX- A32200DX- A32200DX- A32200DX- A1280XL A32140DX Pa208 RQ208 A1280XL A32140DX PQ208 RQ208 Pin Number Functlon Function Function Function Pin Number Functi Functl Fi i Fu I 1 GND GND GND vO 104 vO vO vO GND 2 NC vcc VCC OCLK, /O 105 GND GND GND vO 3 MODE MODE MODE vO 106 NC vcc vec TODO. VO 5 Vo vo vo VO (WD) 107 vo vo vO VO (WD) 6 VO VO vO VO (WD) 108 vo vO vO VO (WD) 7 vo vO vO vcc 110 ie} vo vo vec 9 NC vO vO vo 12 NC vO vO Vo 10 NC vO vO vo 113 NC vO vo vO WW NC vO VO vo 114 NC vO vO 1/0 (WD) 13 vO vO vo QCLKC, 1/0 115 NC vO vO 1/0 (WD) 15 VO vo vO VO (WD) 117 vO v0 Vo QCLKB, I/O 16 NC vO vO VO (WD) 121 vO VO vo (/O (WD) 7 VCC Vcc vcc Vo 122 vO vO vo (/O (WD) 19 VO vO vO VO (WD} 126 GND GND GND vO 3 20 vO vO vo (/O (WD} 128 vO TCK, VO TCK, 1/0 0 22 GND GND GND PRB, I/O 129 GND GND GND vcc 8 24 vO vo vo CLKB, /O 130 vec vcc Vcc GND o 26 vO vO VO GND 131 GND GND GND vO 27 GND GND GND vcc 132 vec vec VCC vO - 28 vcc VCC vec vo 133 vec vec voc vO & 29 VCC VCC Vcc CLKA, 1/0 136 vcc VCC VCC vO 30 vO VO Vo PRA, 1/0 137 vo vo VO VO (WD) 32 vec Vcc Vcc VO (WD) 138 vo vo vO VO (WD) 33 vO VO vo VO (WD) 141 NC VO VO VO (WD) 38 vO vo Vo QCLKD, lO 142 vo vO vO VO (WD) 40 vO vO vo VO (WD) 144 vO vo VO QCLKA, I/O 41 NC vo vo VO (WD) 146 NC vo Vo vO A2 NC vo vo vo 147 NC vo VO vO 43 NC Vo vo vO 148 NC vo vO vO 45 vO vo vo vcc 149 NC vo VO vec 47 vO vO vo VO (WD) 150 GND GND GND vO 48 vO 0 ie) VO (WD) 151 vO vo VO VO (WD) 50 NC vO vo SDI, VO 152 He) Vo VO VO (WD) 51 NC VO vO vO 154 vo vo vO TDI, vO 52 GND GND GND GND 165 vo vo VO TMS, 1/0 53 GND GND GND vO 156 vo vo vO GND 54 vO TMS, VO TMS, VO vO 187 GND GND GND voc 55 vO TDI, vO TDI, vO vO 159 $DI,VO SDILVO SDI,VvO vO 57 vO 1/0 (WD) (70 (WD) vo 161 vO VO (WD) VO (WD) vO 58 vO W/O (WD) W/O (WD) vo 162 vO vO (WD) VO (WD) vo 59 vO vo vo GND 164 vec vcc vec vo 60 vec vcc VCC vO 165 NC vo VO vO 61 NC vO Vo vO 166 NC Vo vO Vo 62 NC vo vo vo 168 vo 70 (WD) VO (WD) vO 65 vo vO QCLKA, VO 1/0 169 vO VO (WD) VO (WD} vO 66 VO VO (WD) VO (WD} vO 171 NC vo QCLKD,/O /O 67 NC VO (WD) vO (WD) vO 176 ie) VO (WD) VO (WD} vO 68 NC vo vo vo 177 VO (0 (WD) VO (WD) vo 70 vO VO (WD) VO (WD) vO 178 PRA,VO PRA,VO PRA,VO- VCC 71 vo (/0 (WD) VO (WD) 0 180 CLKA,V/O CLKA,VO CLKA VO VO 74 vo 1/0 vO voc 181 NC VO vo vec 77 vO vo vO vec 162 NC vec Vcc vec 78 GND GND GND Vcc 183 vec vcc vcc vO 79 vec vec vcc vec 184 GND GNO GND vO 80 NC vcc voc GND 186 CLKBWVO CLKB,VO CLKB,VO vO 81 vo vo vO TCK, VO 187 vo vo vO GND a3 vo Vo vO GNO 188 PRB,VO PRB,IVO PRB,VO vO 85 vo VO (WD) VO (WD) vo 190 70 (0 (WD) VO (WD) vO 86 vo VO (WD) VO (WD) vo 191 vO 1/0 (WD) VO (WD) vO ag NC vo vo VO 193 NC (0 vO vO 90 NC VO vO vO 194 NC (/O (WD) VO (WD) vO a1 vo Vo QCLKB, I/O vO 195 NC (YO (WD) VO (WD) vO 93 vo /O (WD) VO (WD) vO 196 vo vo QCLKC,VO VO 94 vO (70 (WD) VO (WD) Vo 197 NC vO vO vO 95 NC ie) vo vo 201 NC VO vO vO 96 NC O vo vo 202 vcc voc vcc vO 97 NC vo vO vO 203 vo VO (WD) VO (WD) vO 98 vec vec vec Vo 204 vo VO (WD) VO (WD) vO 100 vO (70 (WO) VO (WD) VO 206 vo 1/0 vO MODE 101 VO 70 (WD) VO (WD) VO 207 BCLK,O OCLK,I/O DCLKVO vec 103 vO TDO, VO TDO, VO vcc 208 vo VO vO GNDSy Package Pin Assignments (continued) 240-Pin RQFP Package (Top View} iH EEL I i I eee i! | | | i il 1 | | Exposed Lu pe 4 Heatsink il ' so ce Pott ay I: 1 Ie 1] oJ Ioit 4 I IT | | Hod rt Ho io ; (lot ot 1] ! og i I] 1 : 240-P\ -Pin : RQFP lots oy loti bo lot oy rot so Ife I: ; L | ui tote ny it bot a ii iT ot Th od Th oI it ot Hot i ot oT eli | co ppt | eee 7 ide. Notes; 1. YO (WD): Denotes 1/0 pin with an associated Wide Decode Module 2 Wide Decode YO (WD) can also be general purpose user /O 3. NC: Denotes No Connection 4. All unlisted pin mumbers are user 70's 5. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 6 -ROFP has an exposed circular metal heatsink on the top surface.Integrator Series FPGAs - 1200XL and 3200DX Familes 240-Pin RQFP Package Pin Number A32200DX Function Pin Number A32200DX Function 2 DCLK, I/O 119 GND 6 VO (WD) 120 GND 7 VO (WD) 121 GND 8 vec 123 TDO, VO 15 QCLKC, 1/0 125 VO (WD) 17 VO (WD) 126 VO (WD) 18 VO (WD) 128 VCC 21 VO (WD) 132 VO (WD) . 22 VO (WD) 133 VO (WD) & 24 PRB, /O 135 QCLKB, /0 = 26 CLKB, 1/0 142 VO (WD) o 28 GND 143 VO (WD) 29 VCC 150 vcC 30 VCC 151 VCC 32 CLKA, I/O 152 GND 34 PRA, /O 159 0 (WD) 37 VO (WD) 160 VO (WD) 38 VO (WD) 163 VO (WD) 45 QCLKD, /O 164 1/0 (WD) 47 1/0 (WD) 166 QCLKA, /O 48 1/0 (WD) 172 rere) 52 VCC 174 VO (WD) 54 vO (WD) 175 1/0 (WD) 55 VO (WD) 178 TDI, vO 57 SDI, VO 179 TMS, /O 59 VCC 180 GND 60 GND 181 VCC 61 GND 182 GND 71 VCC 192 VCC 85 VCC 206 VCC 88 VCC 209 VCC 89 VCC 210 VCC 90 VCC 219 vec 91 GND 227 Nee) 92 TCK, /O 237 GND 94 GND 238 MODE 108 VCC 239 VCC 118 VCC 240 GND 1-65(Sy/ Package Pin Assignments (continued) 176-Pin TQFP Package (Top View) cE a i +O Wd ot Ms iol I.) i -L Lod 1 Foal Vt 1 PoUI --1f J u 171 ul Wd il lt oJ 1 LTt it dtd a MW.) ma TE] rf Woot rt WJ H ao I i I I iT il t 176-Pin a : TOFP it ul Wood if WJ a Mo it Wf ui il ri iL I ot I tio] a icon I can I an il foo ti fl] u td i C i at [ooG a to i [io] TE (rod ct to | i| it i mm Meets TTT Notes: 1 VO(WD): Denotes 1/0 pin with an associated Wide Decode Module 2 Wide Decode 1/0 (WD) can also be general purpose user 1/0 3. NC; Denotes No Connection 4. All unlisted pin numbers are user 1/0s 5. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-66Integrator Series FPGAs - 1200XL and 3200DX Familes 176-pin TQFP Package Pin A1240XL =A3265DX A1280XL A32140DX Pin A1240XL A3265DX A1280XL A32140DX Number Function Function Function fFunctlon Number Function Function Function Function 1 GND GND GND GND 97 NC VO VO VO 2 MODE MODE MODE MODE 101 NC NC NG vO 8 NC NC NC VO 103 NC VO VO vo 10 NC NC vO vO 106 GND GND GND GND 1 NC NC vO VO 107 NC VO Vo vo 13 NC vec vec vcc 108 NC VO Vo TCK, VO 18 GND GND GND GND 109 GND GND GND GND 19 NC VO vO vO 110 Vcc VCC VCC VCC 20 NC VO Vo VO 111 GND GND GND GND 22 NC vO ie) vO 112 VCC VCC VCC VCC 23 GND GND GND GND 113 Vcc vCCc vcc Vcc 24 NC Vcc VCC VCC 114 NC VO Vo vo 25 VCC VCC vec vcc 115 NC vO vO vo 26 NC VO vo vO 116 NC VCC VCC VCC 27 NC vO vO vO 117 VO NC VO vo 28 vec Vcc VCC Vcc 121 NC NC NC vO 29 NC NC vo VO 124 NC NC 0 Vo 33 NC NC NC VO 125 NC NC VO vo 37 NC NC vO VO 126 NC NC NC VO 38 NG NC NC VO 133 GND GND GND GND 45 GND GND GND GND 135 SDI,I/O SDI,VO SDI,VvO SDI/O 46 vO vO VO TMS, V/O 136 NC NC vo Vo 47 Vo vO VO TDI, /O 137 vO ie] vO VO (WD) 48 vO NC vO vO 138 vO vO VO VO (WD) 49 Vo vo vO VO (WD) 139 vo VO (WD) vO VO 50 VO vo vO VO (WD) 140 NC voc vcc VCC 52 NC VCC vec VCC 144 VO VO (WD) vO 0 54 NC VO (WO) vO vo 143 NC VO VO VO 55 NC VO (WD) vO VO (WD) 144 NC VO (WD) vO 1/0 (WD) 56 VO vo vO VO (WD) 145 NC NC NC VO (WD) 57 NC NC NC VO 146 vO VO (WD) VO vO 59 vO VO (WD) vO VO (WD) 147 NC vO vo ie) 60 vO VO (WD) vO VO (WD) 149 vO VO (WD) vO vO 61 NC VO vO vO 150 vo VO (WD) Vo VO (WD) 64 NC 0 VO vO 151 NC vO VO VO (WD) 66 NC vO vO VO 152 PRA,V/O PRA,I/O PRA,VO PRA,VO 67 GND GND GND GNO 154 CLKAVO CLKAIO CLKAWVO CLKAIO 68 VCC VCC VCC VCC 155 VCC vcc voc vcc 69 vO VO (WD) vO VO (WD) 156 GND GND GNO GND 70 VO VO (WD) vo VO (WD) 158 CLKBV/O = CLKBIVO CLKB.VVO CLKBVO 73 70 VO (WD) vo vO 160 PRB,VO PRB,I/O PRB,VO PRB,I/O 74 NC NC VO vO 161 NC VO vo VO (WD) 75 VO VO (WD) VO vo 162 vO /O (WD) vo VO (WD) 77 NC NC NC VO (WD) 163 vo VO (WD) vO vO 78 NC NC vO VO (WD) 165 NC NC NC VO (WD) 80 NC VO (WD) VO Vo 166 NC vO vo VO (WD) 81 vO VO (WD) vO Vo 168 NC VO vo vO 82 NC voc vec VCC 169 VO VO (WD) VO vo 84 ie) VO VO VO (WD) 170 NC VCC Vcc Vcc 85 VO vo VO (70 (WD) 171 vO 70 (WD) VO VO (WD) 86 NC NC vO 0 172 vo vO vO (/O (WD) 87 vO VO vO TODO, I/O 173 NC NC vO vO 89 GND GND GND GND 175 DCLK,VO DCLKIO DCLKIO DCLKVO 96 NC NC VO VO 1-67'Sy/ Package Pin Assignments (continued) 100-Pin CPGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 AQOOOOOOCOCOO OA BOOOOCOCO00 OF qdoooooogoo ogo of OOO @ Oo OO O}D EFOOO OO OFF FO OO Of Wk 1O OO OfF GIO OO OO OG HO OC Oo OO O}H JOOOROOO00000 Olu KOOOO0O00CC OO OK YOOROCOOOOC0O0C00 O08 123 4 5 6 7 8 10 11 @ Orientation Pin Signal Pad Number Location PRA or VO 85 A7 PRB or /O 92 A4 MODE 2 C2 SDI or /O 77 C8 DCLK or I/O 100 C3 CLKA or VO 87 C6 CLKB or I/O 90 D6 GND 7, 20, 32, 44, 55, 70, 82, 94 E3, G3, J5, J7, G9, F11, D10, C7, C5 Voc 15, 38, 64, 88 F3, G1, K6, F9, F10, E11, B6 Notes: 1. Unused 1/0 pins are desiqnated as outputs by ALS and are driven low. 2. Allunassigned pins are available for use as /Os. 3. MODE = GND, except during device programming or debugging. 1-68Integrator Series FPGAs - 1200XL and 3200DX Familes Package Pin Assignments (continued) 132-Pin CPGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 AIQOOOOOODOCOOOCOIA BJOOCOOO0CCCOO O00 OF8 crOoOOCOCOoOCOoO oO Kos DIO OO @ O00 OO OjD EIC OO OO O;E . FIOO OO OOO OIF & eBloooo|] Wer 00 O0fs g HOC OO Ooooh s JJOCOO Oo Oj KIO OO O00 OO O|k LID OOCOCOCO0OOC COOL MOOOOOOCOO0O00O0[M NIOOOOOOOOCOO0O0OIN 1 2 3 4 5 6 7 8 9 10 11 12 13 @ Orientation Pin Signal Pad Number Location PRA or VO 113 BB PRB or VO 121 C6 MODE 2 Al SDI or /O 101 B12 DCLK or VO 132 C3 CLKA or I/O 115 B7 CLKB or I/O 119 B6 GND 9, 10, 26, 27, 41, 58, 59, 73, 74, 92, 93, E3, F4, J2, J3, L5, L9, M9, K12, J11, H13, E12, 107, 108, 125, 126 E11, C9, B9, B5, C5 Vec 18, 19, 49, 50, 83, 84, 116, 117 G3, G2, G4, L7, K7, G10, G11, G12, G13, D7, C7 Notes: 1 Unused 1/0 pins are designated as outputs by ALS and are driven low. 2. All unassigned pins are available for use as I/Os. 3. MODE = GND, except during device programming or debugging. 1-69S)/ Package Pin Assignments (continued) 176-Pin CPGA (Top View) 1 2 3 4 5 6 7 8 9 40 11 12 13 14 15 JAQO00OCOOOOCOOCOCOOS! BOOOCOCOCOOCOCCO0C 0 OBB SHOOCOOOCOOCCCOCC oO ofc DOOOOCOCOCCO0O0CC OC Cp EOOCOOO OOOO. FOOO0 OOO OF BOCOO0 O00 O]G6 HOOO0O0 176-Pin OOOO JOOOO OOOO! KO O00 OOO O|k LIO OOO OOO 0k MOOOCO0O0O0CCCO0OCO0C|M NOOOODOCOOODOCOOCCOOON POOOODO0C0C0O0C00000 Or RFOCOOCDOOCOCOCOCOOOR 1 2 3 4 5 6 7 B 9 10 11 12 13 14 15 Signal Pad Number Location PRA or /O 152 C9 PRB or /O 160 D7 MODE 2 c3 SDI or /O 135 B14 DCLK or VO 175 B3 CLKA or I/O 154 Ag CLKB or 1/0 158 B8 GND 1, 8, 18, 23, 33, 38, 45, 57, 67, 77, 89 D4, 4, G4, H4, K4, L4, M4, M6, M8, M10, M12 101, 106, 111, 121, 126, 133, 145, 156, 165 K12, J12, J13, H12, F12, 12, D12, D10, C8, DS Voc 13, 24, 28, 52, 68, 82, 112, 116, 140, 155, 170 O12 11 De Ds. N8, M11, J14, H13, H14, Notes: i Unused 1/0 pins are designated as outmuts by ALS and are driven low. 2 All unassigned pins are available for use as I/Os. 3. MODE = GND, except during device programming or debugging.Integrator Series FPGAs - 1200XL and 3200DX Familes Package Pin Assignments (continued) 172-Pin CQFP Pin #1 eoe index e 1 CL FI a Ce) CT Cd) Ce SA CL . oa eee 6 | CL s CF CL a e e o 172-Pin CQFP & e e 5 a Cc 7 oF LT | Co) Co Ee) CS CL ee CL | CL CT Cc eee Signal Pad Number CLKA or VO 150 CLKB or I/O 154 DCLK or 1/0 171 GND 7,17, 22, 32, 37, 55, 65, 75, 98, 103, 106, 118, 123, 141, 152, 161 MODE 1 PRA or I/O 148 PRB or I/O 156 SDI or VO 131 Vec 12, 23, 24, 27, 50, 66, 80, 107, 109, 110, 113, 136, 151, 166 Notes: I. Unused 1/0 pins are designated as outputs by ALS and are driven low. 2 All unassigned pins are available for use as I/Os. 3 MODE = GND, except during device programming or debugging. 1-71