Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMP8640, LMP8640-Q1, LMP8640HV SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 LMP8640/-Q1/HV Precision High Voltage Current Sense Amplifiers 1 Features 3 Description * * The LMP8640, LMP8640-Q1 and the LMP8640HV are precision current sense amplifiers that detect small differential voltages across a sense resistor in the presence of high input common mode voltages with a supply voltage range from 2.7 V to 12 V. 1 * * * * * * * * * Typical Values, TA = 25C High Common-Mode Voltage Range - LMP8640: -2 V to 42 V - LMP8640-Q1: -2 V to 42 V, AEC-Q100 - LMP8640HV: -2 V to 76 V Supply Voltage Range: 2.7 V to 12 V Gain Options: 20 V/V; 50 V/V; 100 V/V Max Gain Error: 0.25% Low Offset Voltage: 900 V Input Bias Current: 13 A PSRR: 85 dB CMRR (2.1V to 42V): 103 dB Temperature Range: -40C to 125C 6-Pin Thin SOT-23 Package The LMP8640 and LMP8640-Q1 accept input signals with common mode voltage range from -2 V to 42 V, while the LMP8640HV accepts input signal with common mode voltage range from -2 V to 76 V. The LMP8640 and LMP8640HV have fixed gain for applications that demand accuracy over temperature. The LMP8640 and LMP8640HV come out with three different fixed gains 20 V/V, 50 V/V, 100 V/V ensuring a gain accuracy as low as 0.25%. The output is buffered in order to provide low output impedance. This high side current sense amplifier is ideal for sensing and monitoring currents in DC or battery powered systems, excellent AC and DC specifications over temperature, and keeps errors in the current sense loop to a minimum. The LMP8640 and LMP8640HV are ideal choice for industrial and consumer applications, while the LMP8640-Q1 is an AEC-Q100 grade 1 qualified version of the LMP8640 for automotive applications. The LMP8640-x is available in SOT-23-6 package. 2 Applications * * * * * * High-Side Current Sense Vehicle Current Measurement Motor Controls Battery Monitoring Remote Sensing Power Management Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) LMP8640 LMP8640-Q1 SOT23 (6) 2.9 mm x 1.6 mm LMP8640HV (1) Simplified Schematic For all available packages, see the orderable addendum at the end of the datasheet. Output Voltage vs Input Voltage IS -IN RIN + L o a d LMP8640 RIN VOUT (V) + RS +IN + V + VA G ADC VOUT RG = 2*RIN V 13.0 12.0 11.0 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0 VS =12V, VCM =12V GAIN 100V/V GAIN 50V/V GAIN 20V/V 100 200 300 400 500 600 VSENSE (mV) - G = 10 V/V in 20 V/V gain option G = 25 V/V in 50 V/V gain option G = 50 V/V in 100 V/V gain option 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMP8640, LMP8640-Q1, LMP8640HV SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8 1 1 1 2 3 3 4 Absolute Maximum Ratings ...................................... 4 Handling Ratings - LMP8640, LMP8640HV.............. 4 Handling Ratings - LMP8640-Q1 .............................. 4 Recommended Operating Conditions (2) ................... 4 Thermal Information .................................................. 5 Electrical Characteristics 2.7 V ................................ 5 Electrical Characteristics 5 V (5)................................ 6 Electrical Characteristics 12 V (5).............................. 8 Typical Characteristics ............................................ 10 Detailed Description ............................................ 14 8.1 Overview ................................................................. 14 8.2 Functional Block Diagram ....................................... 14 8.3 Feature Description................................................. 14 8.4 Device Functional Modes........................................ 17 9 Application and Implementation ........................ 18 9.1 Application Information............................................ 18 9.2 Typical Application .................................................. 18 9.3 Do's and Don'ts ...................................................... 20 10 Power Supply Recommendations ..................... 20 11 Layout................................................................... 20 11.1 Layout Guidelines ................................................. 20 11.2 Layout Example .................................................... 21 12 Device and Documentation Support ................. 23 12.1 12.2 12.3 12.4 12.5 12.6 Device Support...................................................... Documentation Support ........................................ Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 23 23 23 13 Mechanical, Packaging, and Orderable Information ........................................................... 23 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (April 2013) to Revision G Page * New Q Device added to datasheet ........................................................................................................................................ 1 * Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information .................................................................................................................................... 1 2 Submit Documentation Feedback Copyright (c) 2010-2014, Texas Instruments Incorporated Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV LMP8640, LMP8640-Q1, LMP8640HV www.ti.com SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 5 Device Comparison Table DEVICE NAME GAIN LMP8640-T x20 QUALIFICATIONS MAX COMMON MODE VOLTAGE -2 V to +42 V LMP8640-T x20 LMP8640-Q1-T x20 -2 V to +42 V LMP8640-F x50 -2 V to +42 V LMP8640-H x100 -2 V to +42 V LMP8640HV-T x20 -2 V to +76 V LMP8640HV-F x50 -2 V to +76 V LMP8640HV-H x100 -2 V to +76 V Automotive AEC-Q100, Grade 1 -2 V to +42 V 6 Pin Configuration and Functions 6-Pin SOT-23 DDC0006A Package (Top View) VOUT V - +IN 1 LMP8640 LMP8640HV 2 3 + 6 V 5 NC 4 -IN Pin Functions PIN DESCRIPTION NUMBER NAME 1 VOUT 2 V- 3 +IN Positive Input 4 -IN Negative Input 5 NC Not Internally Connected 6 V+ Positive Supply Voltage Copyright (c) 2010-2014, Texas Instruments Incorporated Output Negative Supply Voltage Submit Documentation Feedback Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV 3 LMP8640, LMP8640-Q1, LMP8640HV SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) (2) (3) LMP8640 limits also apply to the LMP8640-Q1. Supply Voltage (VS = V+ - V-) Differential Voltage +IN- (-IN) Voltage at pins +IN, -IN (1) (2) (3) (4) MAX UNIT -0.3 13.2 V -6 6 V LMP8640HV -6 80 V LMP8640, LMP8640-Q1 -6 60 V - + Voltage at VOUT pin Junction Temperature MIN (4) V V V -40 150 C "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Operating Ratings is not implied. Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond such conditions. For soldering specifications,see product folder at www.ti.com and http://www.ti.com/lit/SNOA549. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), JA, and the ambient temperature, TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA)/ JA or the number given in Absolute Maximum Ratings, whichever is lower. 7.2 Handling Ratings - LMP8640, LMP8640HV MIN Tstg Storage temperature range Human body model (HBM (1)) V(ESD) Electrostatic discharge Charged device model (CDM) Machine model (MM) (1) (2) (3) (2) MAX UNIT C -65 150 For input pins +IN, -IN -5000 5000 For all other pins -2000 2000 All pins -1250 1250 -200 200 (3) V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) 7.3 Handling Ratings - LMP8640-Q1 Tstg MIN MAX UNIT -65 150 C Human body model (HBM), per AEC Q100-002 (1) -2000 2000 Charged device model (CDM), per AEC Q100-011 All pins -1000 1000 All pins -200 200 Storage temperature range V(ESD) Electrostatic discharge Machine model (MM) (1) (2) (2) V AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) 7.4 Recommended Operating Conditions (1) MIN + - Supply Voltage (VS = V - V ) Operating Junction Temperature Range (1) (2) 4 (2) MAX UNIT 2.7 12 V -40 125 C "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Operating Ratings is not implied. Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond such conditions. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), JA, and the ambient temperature, TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA)/ JA or the number given in Absolute Maximum Ratings, whichever is lower. Submit Documentation Feedback Copyright (c) 2010-2014, Texas Instruments Incorporated Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV LMP8640, LMP8640-Q1, LMP8640HV www.ti.com SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 7.5 Thermal Information LMP8640 LMP8640HV LMP8640-Q1 THERMAL METRIC (1) UNIT THIN SOT-23 6 PINS (2) RJA Junction-to-ambient thermal resistance RJC(top) Junction-to-case (top) thermal resistance RJB Junction-to-board thermal resistance 24.6 JT Junction-to-top characterization parameter 0.3 JB Junction-to-board characterization parameter 23.8 (1) (2) 165 28 C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), JA, and the ambient temperature, TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA)/ JA or the number given in Absolute Maximum Ratings, whichever is lower. 7.6 Electrical Characteristics 2.7 V (1) Unless otherwise specified, all limits ensured for at TA = 25C, VS= V+ - V-, VSENSE= +IN-(-IN), V+ = 2.7 V, V- = 0 V, -2 V < VCM < 76 V, RL = 10 M. LMP8640 limits also apply to the LMP8640-Q1. PARAMETER MIN (2) TEST CONDITIONS VCM = 2.1 V VOS Input Offset Voltage TCVOS Input Offset Voltage Drift (4) IB Input Bias Current eni Input Voltage Noise VCM = 2.1 V, Over Temperature (5) -900 900 1160 VCM = 2.1 V 12 f > 10 kHz PSRR CMRR (1) (2) (3) (4) (5) (6) A nV/Hz 20 50 Gain LMP8640-H LMP8640HV-H 100 V/V VCM = 2.1 V -0.25% 0.25% VCM = 2.1 V, Over Temperature -0.51% 0.51% Accuracy over temperature (5) VCM = 2.1V, Over Temperature Power Supply Rejection Ratio VCM = 2.1 V, 2.7 V < V+ < 12 V, 85 LMP8640HV 2.1 V < VCM < 42 V LMP8640 2.1 V < VCM< 42 V 103 LMP8640HV 2.1 V < VCM < 76 V 95 -2 V <VCM < 2 V, 60 Common Mode Rejection Ratio V/C 20 117 Gain LMP8640-F LMP8640HV-F Gain error V 27 Gain LMP8640-T LMP8640HV-T Gain AV UNIT 2.6 VCM = 2.1 V, Over Temperature, VSENSE = 0 V (5) MAX (2) -1160 VCM = 2.1 V, VSENSE = 0 V (6) TYP (3) 26.2 ppm/C dB dB Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. This parameter is ensured by design and/or characterization and is not tested in production. Positive Bias Current corresponds to current flowing into the device. Spec does not include input signal dependent currents on the positive input of approximately Vsense / 5K due to topology feedback action. Copyright (c) 2010-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV 5 LMP8640, LMP8640-Q1, LMP8640HV SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 Electrical Characteristics 2.7 V (1) www.ti.com (continued) Unless otherwise specified, all limits ensured for at TA = 25C, VS= V+ - V-, VSENSE= +IN-(-IN), V+ = 2.7 V, V- = 0 V, -2 V < VCM < 76 V, RL = 10 M. LMP8640 limits also apply to the LMP8640-Q1. PARAMETER BW TYP (3) DC VSENSE = 67.5 mV, CL = 30 pF,RL= 1M 950 Fixed Gain LMP8640-F LMP8640HV-F (5) DC VSENSE =27 mV, CL = 30 pF, RL= 1M 450 Fixed Gain LMP8640-H LMP8640HV-H (5) DC VSENSE = 13.5 mV, CL = 30 pF ,RL= 1 M 230 VCM =5 V, CL = 30 pF, RL = 1 M, LMP8640-T LMP8640HV-T VSENSE =100 mVpp, LMP8640-F LMP8640HV-F VSENSE =40 mVpp, LMP8640-H LMP8640HV-H VSENSE =20 mVpp, 1.4 VCM = 2.1 V 420 600 2000 2500 (7) (5) Slew Rate RIN Differential Mode Input Impedance (5) VCM = -2 V, Over Temperature Maximum Output Voltage CLOAD (7) k A 2750 VCM = 2.1 V Minimum Output Voltage V/s 800 VCM = -2 V UNIT kHz 5 VCM = 2.1 V, Over Temperature Supply Current VOUT MAX (2) Fixed Gain LMP8640-T LMP8640HV-T (5) SR IS MIN (2) TEST CONDITIONS 2.65 V LMP8640-T LMP8640HV-T VCM = 2.1 V 18.2 LMP8640-F LMP8640HV-F VCM = 2.1 V 40 LMP8640-H LMP8640HV-H VCM = 2.1 V 80 Max Output Capacitance Load (5) 30 mV pF The number specified is the average of rising and falling slew rates and measured at 90% to 10%. 7.7 Electrical Characteristics 5 V (1) Unless otherwise specified, all limits ensured for at TA = 25C, VS= V+ - V-, VSENSE= +IN-(-IN), V+ = 5 V, V- = 0 V, -2 V < VCM < 76 V, RL = 10 M. LMP8640 electrical limits also apply to the LMP8640-Q1 unless noted. PARAMETER VCM = 2.1 V VOS Input Offset Voltage TCVOS Input Offset Voltage Drift (4) Input Bias Current eni Input Voltage Noise (1) (2) (3) (4) (5) (6) 6 VCM = 2.1 V, Over Temperature (5) TYP (3) 900 -1160 1160 2.6 13 VCM = 2.1 V, Over Temperature,VSENSE = 0 V (5) MAX (2) -900 VCM = 2.1 V VCM = 2.1 V, VSENSE = 0 V (6) IB MIN (2) TEST CONDITIONS f > 10 kHz 21 28 117 UNIT V V/C A nV/Hz Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. This parameter is ensured by design and/or characterization and is not tested in production. Positive Bias Current corresponds to current flowing into the device. Spec does not include input signal dependent currents on the positive input of approximately Vsense / 5K due to topology feedback action. Submit Documentation Feedback Copyright (c) 2010-2014, Texas Instruments Incorporated Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV LMP8640, LMP8640-Q1, LMP8640HV www.ti.com SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 Electrical Characteristics 5 V (1) (continued) Unless otherwise specified, all limits ensured for at TA = 25C, VS= V+ - V-, VSENSE= +IN-(-IN), V+ = 5 V, V- = 0 V, -2 V < VCM < 76 V, RL = 10 M. LMP8640 electrical limits also apply to the LMP8640-Q1 unless noted. PARAMETER MIN (2) TEST CONDITIONS Gain LMP8640-T LMP8640HV-T Gain AV CMRR 50 Gain LMP8640-H LMP8640HV-H 100 BW -0.25% 0.25% VCM = 2.1 V, Over Temperature -0.51% 0.51% -40C to 125C, VCM=2.1 V Power Supply Rejection Ratio VCM = 2.1 V, 2.7V < V+ < 12 V, 26.2 ppm/C 85 LMP8640HV 2.1 V < VCM < 42 V LMP8640 2.1 V < VCM< 42 V 103 LMP8640HV 2.1 V < VCM < 76 V 95 -2 V <VCM < 2 V, 60 dB DC VSENSE = 67.5 mV, CL = 30 pF ,RL= 1 M 950 Fixed Gain LMP8640-F LMP8640HV-F (5) DC VSENSE =27 mV, CL = 30 pF ,RL= 1 M 450 Fixed Gain LMP8640-H LMP8640HV-H (5) DC VSENSE = 13.5 mV, CL = 30 pF ,RL= 1M 230 VCM =5 V, CL = 30 pF, RL = 1M, LMP8640-T LMP8640HV-T VSENSE = 200 mVpp, LMP8640-F LMP8640HV-F VSENSE = 80 mVpp, LMP8640-H LMP8640HV-H VSENSE = 40 mVpp, 1.6 SR Slew Rate RIN Differential Mode Input Impedance (5) 722 2050 2500 VCM = -2 V, Over Temperature VOUT CLOAD (7) A 2750 VCM = 2.1 V Minimum Output Voltage k 922 VCM = -2 V Maximum Output Voltage V/s 500 VCM = 2.1 V, Over Temperature Supply Current kHz 5 VCM = 2.1 V IS dB Fixed Gain LMP8640-T LMP8640HV-T (5) (7) (5) UNIT V/V VCM = 2.1 V Accuracy over temperature (5) Common Mode Rejection Ratio MAX (2) 20 Gain LMP8640-F LMP8640HV-F Gain error PSRR TYP (3) 4.95 V LMP8640-T LMP8640HV-T VCM = 2.1 V 18.2 LMP8640-F LMP8640HV-F VCM = 2.1 V 40 LMP8640-H LMP8640HV-H VCM = 2.1 V 80 Max Output Capacitance Load (5) 30 mV pF The number specified is the average of rising and falling slew rates and measured at 90% to 10%. Copyright (c) 2010-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV 7 LMP8640, LMP8640-Q1, LMP8640HV SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 7.8 Electrical Characteristics 12 V www.ti.com (1) Unless otherwise specified, all limits ensured for at TA = 25C, VS= V+ - V-, VSENSE= +IN-(-IN), V+ = 12 V, V- = 0V, -2 V < VCM < 76 V, RL = 10 M. LMP8640 electrical limits also apply to the LMP8640-Q1 unless noted. PARAMETER VCM = 2.1 V VOS Input Offset Voltage TCVOS Input Offset Voltage Drift (4) Input Bias Current eni Input Voltage Noise Gain AV VCM = 2.1 V, Over Temperature (5) (5) BW Common Mode Rejection Ratio (5) (6) (7) 8 V V/C A V/V 100 -0.25% 0.25% VCM = 2.1 V, Over Temperature -0.51% 0.51% -40C to 125C, VCM= 2.1 V 26.2 ppm/C VCM = 2.1 V, 2.7 V < V+ < 12 V, 85 LMP8640HV 2.1 V < VCM < 42 V LMP8640 2.1 V < VCM< 42 V 103 LMP8640HV 2.1 V < VCM < 76 V 95 -2 V < VCM < 2 V, 60 dB dB DC VSENSE = 67.5 mV, CL = 30 pF, RL= 1 M 950 Fixed Gain LMP8640-F LMP8640HV-F (5) DC VSENSE =27 mV, CL = 30 pF, RL= 1 M 450 Fixed Gain LMP8640-H LMP8640HV-H (5) DC VSENSE = 13.5 mV, CL = 30 pF, RL= 1 M 230 VCM =5 V, CL = 30 pF, RL = 1 M, LMP8640-T LMP8640HV-T VSENSE = 500 mVpp, LMP8640-F LMP8640HV-F VSENSE =200 mVpp, LMP8640-H LMP8640HV-H VSENSE =100 mVpp, 1.8 (7) (5) UNIT nV/Hz VCM = 2.1 V Fixed Gain LMP8640-T LMP8640HV-T (5) Differential Mode Input Impedance (5) (4) 117 Gain LMP8640-H LMP8640HV-H Power Supply Rejection Ratio 22 28 50 RIN (3) 2.6 13 Gain LMP8640-F LMP8640HV-F Slew Rate (2) VCM = 2.1 V f > 10 kHz SR (1) 1160 20 Accuracy over temperature CMRR -1160 Gain LMP8640-T LMP8640HV-T (5) MAX (2) 900 VCM = 2.1 V, Over Temperature, VSENSE = 0 V Gain error PSRR TYP (3) -900 VCM = 2.1 V, VSENSE = 0 V (6) IB MIN (2) TEST CONDITIONS 5 kHz V/s k Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. This parameter is ensured by design and/or characterization and is not tested in production. Positive Bias Current corresponds to current flowing into the device. Spec does not include input signal dependent currents on the positive input of approximately Vsense / 5K due to topology feedback action. The number specified is the average of rising and falling slew rates and measured at 90% to 10%. Submit Documentation Feedback Copyright (c) 2010-2014, Texas Instruments Incorporated Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV LMP8640, LMP8640-Q1, LMP8640HV www.ti.com SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 Electrical Characteristics 12 V (1) (continued) Unless otherwise specified, all limits ensured for at TA = 25C, VS= V+ - V-, VSENSE= +IN-(-IN), V+ = 12 V, V- = 0V, -2 V < VCM < 76 V, RL = 10 M. LMP8640 electrical limits also apply to the LMP8640-Q1 unless noted. PARAMETER MIN (2) TEST CONDITIONS VCM = 2.1 V IS TYP (3) MAX (2) 720 1050 VCM = 2.1 V, Over Temperature Supply Current 1250 VCM = -2 V 2300 VCM = -2 V, Over Temperature Maximum Output Voltage VOUT CLOAD 11.85 V LMP8640-T LMP8640HV-T VCM = 2.1 V 18.2 LMP8640-F LMP8640HV-F VCM = 2.1 V 40 LMP8640-H LMP8640HV-H VCM = 2.1 V 80 Max Output Capacitance Load (5) Copyright (c) 2010-2014, Texas Instruments Incorporated A 3000 VCM = 2.1 V Minimum Output Voltage 2800 UNIT 30 Submit Documentation Feedback Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV mV pF 9 LMP8640, LMP8640-Q1, LMP8640HV SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 www.ti.com 7.9 Typical Characteristics Unless otherwise specified: TA = 25C, VS=V+-V-, VSENSE= +IN - (-IN), RL = 10 M. 2300 2400 2100 VCM=-2V 2500 2200 2100 IS (PA) 125C 700 600 500 5.3 8.0 10.6 125C 1300 1100 25C -40C 900 700 500 400 300 2.7 1500 300 -2 -1 0 13.2 1 2 3 Figure 1. Supply Curent vs. Supply Voltage Figure 2. Supply Current vs. VCM 2300 2500 VS = 5V 1900 2100 1700 1900 1500 125C 1300 1100 1700 -40C 900 1100 900 500 700 | 700 1 2 3 125 C 1500 1300 25C 300 -2 -1 0 VS = 12V 2300 IS (PA) IS (PA) 2100 25C -40C 500 -2 -1 0 4 16 28 40 52 64 76 1 2 VCM (V) 140 130 130 120 CMRR (dB) 25C 125 C 110 4 16 28 40 52 64 76 Figure 4. Supply Current vs. VCM 140 120 3 VCM (V) Figure 3. Supply Current vs. VCM CMRR (dB) 4 16 28 40 52 64 76 VCM (V) VS (V) | | 800 25C -40C 1700 VCM = 2.1V 1900 | IS (PA) 2000 1900 | 2300 VS = 2.7V -40C 100 -40C 25C 110 100 90 90 VS = 5V 80 -2 11 24 37 50 63 VS = 5V 76 80 -2 11 Figure 5. CMRR vs. VCM (Gain 20 V/V) Submit Documentation Feedback 24 37 50 63 76 V CM (V) VCM (V) 10 125C Figure 6. CMRR vs. VCM (Gain 50 V/V) Copyright (c) 2010-2014, Texas Instruments Incorporated Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV LMP8640, LMP8640-Q1, LMP8640HV www.ti.com SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 Typical Characteristics (continued) Unless otherwise specified: TA = 25C, VS=V+-V-, VSENSE= +IN - (-IN), RL = 10 M. 200 140 VS = 5V -40C 150 130 CMRR (dB) 25C VOS (PV) 100 120 125C 110 125 C 50 0 25C -50 100 -100 90 -40C -150 V S = 5V 80 -2 11 24 37 50 63 -200 -2 76 11 24 37 Figure 7. CMRR vs. VCM (Gain 100 V/V) 76 100 0 0 -100 -100 -200 -40C -400 -40C -200 125C -300 (A) IB (PV) (A) IB (PV) 63 Figure 8. Input Voltage Offset vs. VCM 100 25C 125 C -300 -400 -500 -500 -600 -600 25C -700 -700 -800 -800 VS = 2.7V -900 -2 -1 0 1 2 3 VS = 5V -900 -2 -1 0 4 16 28 40 52 64 76 1 2 3 4 16 28 40 52 64 76 VCM (V) VCM (V) Figure 9. Ibias vs. VCM Figure 10. Ibias vs. VCM 50 100 0 -100 50 V CM (V) V CM (V) VS =5V, VCM=5V GAIN 100V/V -40C 40 125C -300 -400 GAIN (dB) IB (PV) (A) -200 25C -500 30 GAIN 50V/V -600 20 GAIN 20V/V -700 -800 VS = 12V -900 -2 -1 0 1 2 3 4 16 28 40 52 64 76 10 100 1k 10k 100k 1M 10M VCM (V) FREQUENCY (Hz) Figure 11. Ibias vs. VCM Figure 12. Gain vs. Frequency Copyright (c) 2010-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV 11 LMP8640, LMP8640-Q1, LMP8640HV SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 www.ti.com Typical Characteristics (continued) 13.0 12.0 11.0 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0 300 VS =12V, VCM =12V V S=12V, VCM=12V 250 GAIN 100V/V 200 VOUT (mV) VOUT (V) Unless otherwise specified: TA = 25C, VS=V+-V-, VSENSE= +IN - (-IN), RL = 10 M. GAIN 100V/V GAIN 50V/V 150 100 GAIN 20V/V GAIN 50V/V 50 GAIN 20V/V 100 200 300 400 500 0 -3 600 -2 -1 0 1 2 3 VSENSE (mV) VSENSE (mV) Figure 13. Output voltage vs. VSENSE Figure 14. Output Voltage vs. VSENSE (ZOOM Close to 0 V) VSENSE GAIN 50V/V GAIN 20V/V VSENS E (10 mV/DIV) GAIN 100 VOUT (100 mV/DIV) VS ENS E (20 mV/DIV) VOUT (500 mV/DIV) V SENSE GAIN 100V/V GAIN 50V/V GAIN 20V/V V S = 5V, VCM = 12V VS =12V, VCM =12V TIME (2 Ps/DIV) TIME (2 Ps/DIV) Figure 16. Small Step Response Figure 15. Large Step Response VS = 5V, VCM = 12V GAIN 100V/V GAIN 100 V/V V SENSE GAIN 20V/V GAIN 50V/V GAIN 20V/V VSE NSE (10 mV/DIV) GAIN 50V/V VOUT (100 mV/DIV) V SE NS E (10 mV/DIV) V OUT (100 mV/DIV) V SENSE VS = 5V, V CM = 12V TIME (400 ns /DIV) Figure 17. Settling Time (Fall) 12 Submit Documentation Feedback TIME (400 ns/DIV) Figure 18. Settling Time (Rise) Copyright (c) 2010-2014, Texas Instruments Incorporated Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV LMP8640, LMP8640-Q1, LMP8640HV www.ti.com SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 Typical Characteristics (continued) V OUT VCM VCM (5V/DIV) VCM (5V/DIV) V CM VOUT (50 mV/DIV) V OUT (20 mV/DIV) Unless otherwise specified: TA = 25C, VS=V+-V-, VSENSE= +IN - (-IN), RL = 10 M. VOUT VS = 5V, GAIN 20 V/V VS = 5V, GAIN 20 V/V TIME (4 es/DIV) TIME (4 es/DIV) Figure 19. Common Mode Step Response (Rise) Figure 20. Common Mode Step Response (Fall) 2.505 2.6 VS =5V, VCM=12V 2.504 2.5 GAIN 100 V/V 2.4 2.502 V OUT (V) V OUT (V) 2.503 GAIN 50 2.501 GAIN 20V/V 2.500 GAIN 100V/V 2.3 2.2 GAIN 50 2.1 2.499 2.0 GAIN 20V/V VS =5V, VCM=12V 2.498 0 1 2 3 4 5 6 7 8 9 1.9 0 10 1 2 3 4 I OUT (mA) 5 Figure 21. Load Regulation (Sinking) 7 8 9 10 Figure 22. Load Regulation (Sourcing) 110 100 V S = 5V, V CM = 12V VS = 5V, VCM = 12V 80 90 CMRR (dB) PSRR (dB) 6 I OUT (mA) 60 GAIN 20V/V 40 70 GAIN 100V/V 50 GAIN 50V/V GAIN 100 V/V 20 30 GAIN 20V/V GAIN 50V/V 0 10 100 1k 10k 100k 1M 10 1 10 FREQUENCY (Hz) Figure 23. AC PSRR vs. Frequency Copyright (c) 2010-2014, Texas Instruments Incorporated 100 1k 10k 100k Frequency (Hz) Figure 24. AC CMRR vs. Frequency Submit Documentation Feedback Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV 13 LMP8640, LMP8640-Q1, LMP8640HV SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 www.ti.com 8 Detailed Description 8.1 Overview The LMP8640 and LMP8640HV are single supply high side current sense amplifiers with a fixed gain of 20 V/V, 50 V/V, 100 V/V and a common mode voltage range of -2 V to 42 V (LMP8640-x) or -2 V to 76 V (LMP8640HVx) with a buffered voltage output. 8.2 Functional Block Diagram +IN -IN RIN LMP8640 RIN LMP8640HV + + V G VOUT RG = 2*RIN V - 8.3 Feature Description As seen in Figure 25, the current flowing through sense resistor RS develops a voltage drop equal to VSENSE across RS. The voltage at the -IN pin will now be less than +IN by an amount proportional to the VSENSE voltage. VSENSE Is + Rs +IN -IN RIN + LMP8640 RIN L o a d + V IG G VOUT RG = 2*RIN V - Figure 25. Simple Current Monitor The low bias currents of the error amplifier cause little voltage drop through RIN-, so the negative input of the internal error amplifier is at essentially the same potential as the -IN input. The RIN resistors are 5 K each. 14 Submit Documentation Feedback Copyright (c) 2010-2014, Texas Instruments Incorporated Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV LMP8640, LMP8640-Q1, LMP8640HV www.ti.com SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 Feature Description (continued) The error amplifier will detect this voltage error between it's inputs and drive the MOSFET gate to conduct more current, increasing the voltage drop across RIN+, until the servo amplifiers positive input matches the negative input. At this point, the voltage drop across RIN+ now matches VSENSE. IG, a current proportional to IS, will flow according to the following relation: IG = VSENSE/RIN = RS* IS/RIN (1) IG also flows through the internal gain resistor RG developing a voltage drop equal to: VRG = IG * RG = (VSENSE/RIN) * RG = ((RS* IS)/ RIN )* RG VOUT = 2*(RS*IS)*G, (2) (3) where G=RG/RIN = 10 V/V, 25 V/V or 50 V/V, according to the gain option selected. The voltage on RG is then amplified by a gain of 2 by the output gain stage to create the final overall gain of x20, x50 and x100. The output stage has a low impedance drive allowing the LMP8640 to easily interface with other IC's (ADC, Mux, C...). No external buffering is required. 8.3.1 Selection of Sense Resistor The value chosen for the shunt resistor, RS, depends on the application. It plays a big role in a current sensing system and must be chosen with care. The selection of the shunt resistor needs to take in account the tradeoffs in small-signal accuracy, the power dissipated and the voltage loss across the shunt itself. In applications where a small current is sensed, a bigger value of RS is selected to minimize the error in the proportional output voltage. Higher resistor value improves the signal-to-noise ratio (SNR) at the input of the current sense amplifier and hence gives a more accurate output. Similarly when high current is sensed, the power losses in RS can be significant so a smaller value of RS is desired. In this condition it is also required to take in account also the power rating of RS resistor. The low input offset of the LMP8640 allows the use of small sense resistors to reduce power dissipation still providing a good input dynamic range. The input dynamic range is the ratio between the maximum signal that can be measured and the minimum signal that can be detected, where usually the input offset is the principal limiting factor. Figure 26. Example of a Kelvin (4-Wire) Connection to a Two-Terminal Resistor The amplifier inputs should be directly connected to the sense resistor pads using "Kelvin" or "4-wire" connection techniques. The paths of the input traces should be identical, including connectors and vias, so that these errors will be equal and cancel. Copyright (c) 2010-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV 15 LMP8640, LMP8640-Q1, LMP8640HV SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 www.ti.com Feature Description (continued) 8.3.1.1 Resistor Power Rating and Thermal Issues The power dissipated by the sense resistor can be calculated from: PD = IMAX2 * RS where * * * PD is the power dissipated by the resistor in Watts IMAX is the maximum load current in Amps RS is the sense resistor value in ohms. (4) The resistor must be rated for more than the expected maximum power (PD), with margin for temperature derating. Be sure to observe any power derating curves provided by the resistor manufacturer. Running the resistor at higher temperatures will also affect the accuracy. As the resistor heats up, the resistance generally goes up, which will cause a change in the measurement. The sense resistor should have as much heat-sinking as possible to remove this heat through the use of heatsinks or large copper areas coupled to the resistor pads. A reading drifting slightly after turn-on can usually be traced back to sense resistor heating. 8.3.1.2 Using PCB Trace as a Sense Resistor While it may be tempting to use the resistance of a known area of PCB trace or copper area as a sense resistor, it is not recommended for precision measurements. The tempco of copper is typically 3300-4000ppm/K (0.33% to 0.4% per C), which can vary with PCB processes. A typical surface mount sense resistor temperature coefficient (tempco) is in the 50ppm to 500ppm per C range offering more measurement consistency and accuracy over the copper trace. Special low tempco resistors are available in the 0.1 to 50ppm range, but at a much higher cost. 8.3.2 Sense Line Inputs The sense lines should be connected to a point on the resistor that is not shared with the main current path, as shown in Figure 26 above. For lowest drift, the amplifier should be mounted away from any heat generating devices, which may include the sense resistor. The traces should be one continuous trace of copper from the sense resistor pad to the amplifier input pin pad, and ideally on the same copper layer with minimal vias or connectors. This can be important around the sense resistor if it is generating any significant heat gradients. Vias in the sense lines should be formed from continuous plated copper and routing through connectors should be avoided. It is better to extend the sense lines than to place the amplifier in a hostile environment. To minimize noise pickup and thermal errors, the input traces should be treated like a high-speed differential signal pair and routed tightly together with a direct path to the input pins on the same copper layer. They do not need to be "impedance matched", but should follow the same matching rules about vias, spacing and equal lengths. The input traces should be run away from noise sources, such as digital lines, switching supplies or motor drive lines. Remember that these input traces can contain high voltage, and should have the appropriate trace routing clearances to other traces and layers. Since the sense traces only carry the amplifier bias current (typically about 12A per input at room temp), the connecting input traces can be thin traces running close together. This can help with routing or creating the required spacings. It should also be noted that, due to the nature of the device topology, the positive input bias current will vary with VSENSE with an extra current approximately equivalent to VSENSE / 5 k on top of the typical 12 uA bias current. The negative input bias current is not in the feedback path and will not change over VSENSE. High or missmatched source impedances should be avoided as this imbalance will create an additional error over input voltage. 8.3.3 Effects of Series Resistance on Sense Lines Because the input stage uses precision 5 K resistors internally to convert the voltage on the input pin to a current, any resistance added in series with the input pins will change this resistance, and thus alter the gain. If a resistance is added in series with an input, the gain of that input will not track that of the other input, causing a constant gain error. 16 Submit Documentation Feedback Copyright (c) 2010-2014, Texas Instruments Incorporated Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV LMP8640, LMP8640-Q1, LMP8640HV www.ti.com SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 Feature Description (continued) It is not recommended to use external resistance to alter the gain, as external resistors will not have the same thermal matching as the internal thin film resistors. Any added resistance will severely degrade the offset and CMRR specifications. It is recommended that the total trace resistance be less than 10 ohms. If resistors are purposely added for filtering, resistance should be added equally to both inputs and the user should be aware that the gain will change slightly. 8.4 Device Functional Modes 8.4.1 Bias Current at Low Common Mode Voltage At common mode voltages below +2 V, the input bias current starts to reverse and crosses through zero at about +1.8 V. This can be seen in the Input Bias Current graphs in Figure 9 through Figure 11. Negative currents on the graph show curent flow out of the input and into the load. The graphs show the current for each input, so the actual "bias" current will be twice graph value. This total current could be as high as 1mA, depending on the point of equilibrium. While this will not affect the vast majority of applications, it may cause MOSFET switched designs with non-linear loads (like LED's or diode-isolated loads) to "float" above ground where the load leakage and bias currents attain equilibrium. A small resistor to ground (on the load supply side) can bleed-off this current. 8.4.2 Applying Input Voltage with No Supply Voltage The full specified input common mode voltage range may be applied to the inputs while the LMP8640 power is off (V+ = 0 V). When the LMP8640 is powered off, the RIN resistors are disconnected internally by MOSFETS and the leakage currents are very low (sub uA). The 6 V input differential limit still applies, so at no time should the two inputs be more than 6 V apart. There are also Zener clamps on the inputs to ground, so do not exceed the input limits specified in the Absolute Maximum Ratings. 8.4.3 Driving an ADC The input stage of an Analog to Digital converter can be modeled with a resistor and a capacitance to ground. So if the voltage source doesn't have a low impedance, an error in amplitude measurement will occur. In this case, a buffer is needed to drive the ADC. The LMP8640 has an internal output buffer able to directly drive a capacitive load up to 30 pF, or, the input stage of an ADC. It is recommended that an external low pass RC filter be added to the output of the LMP8640 to reduce the noise and limit the bandwidth of the current sense measurement. If the supply voltage of the LMP8640 is higher than the ADC supply voltage, care should be taken to prevent the LMP8640 output from over-driving the ADC input. This can be accomplished with a series resistance (which should be present when driving a ADC) and a clamping diode to the ADC's power supply. The diode will clamp the ADC input to a safe level. Do not completely rely on a calculated maximum output voltage. Transients or fault conditions outside the normal conditions area can cause the output to swing to a higher than expected voltage. Copyright (c) 2010-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV 17 LMP8640, LMP8640-Q1, LMP8640HV SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LMP8640x amplifies the voltage developed across a current-sensing resistor. 9.2 Typical Application IS RS + +IN -IN RIN + L o a d LMP8640 RIN + V + VA RF G ADC VOUT CF RG = 2*RIN - V Figure 27. Typical Application Example 9.2.1 Design Requirements In this example, a current monitor application is required to measure the current into a load (peak current 10 A) with a resolution of 10 mA and 0.5% of accuracy. The 10bit analog to digital converter accepts a max input voltage of 4.1 V. In order to not burn too much power on the shunt resistor, it needs to be less than 10 m. Table 1 below summarizes the other design conditions. Table 1. Example Design Requirements WORKING CONDITION VALUE MIN MAX Supply Voltage 5V 5.5 V Common mode Voltage 48 V 70 V Temperature 0C 70C Signal BW 50 kHz 9.2.2 Design Procedure 9.2.2.1 First Step - LMP8640 or LMP8640HV Selection The required common mode voltage of the application implies that the right choice is the LMP8640HV (High common mode voltage up tp 76 V). 18 Submit Documentation Feedback Copyright (c) 2010-2014, Texas Instruments Incorporated Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV LMP8640, LMP8640-Q1, LMP8640HV www.ti.com SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 9.2.2.2 Second Step - Gain Option Selection We can choose between three gain option (20 V/V, 50 V/V, 100 V/V). Considering the max input voltage of the ADC (4.1 V) , the max Sense voltage across the shunt resistor is evaluated according the following formula: VSENSE= (MAX Vin ADC) / Gain; (5) hence the max VSENSE will be 205 mV, 82 mV, 41 mV respectively. The shunt resistor are then evaluated considering the maximum monitored current : RS = (max VSENSE) / I_MAX (6) For each gain option the max shunt resistors are the following : 20.5 m, 8.2 m, 4.1 m respectively. One of the project constraints requires RS<10 m, it means that the 20.5 m will be discarded and hence the 50 V/V and 100 V/V gain options are still in play. 9.2.2.3 Third Step - Shunt Resistor Selection At this point an error budget calculation, considering the calibration of the Gain, Offset, CMRR, and PSRR, helps in the selection of the shunt resistor. In the table below the contribution of each error source is calculated considering the values of the Electrical Characteristics table at 5 V supply. Table 2. Resolution Calculation RS = 4.1 m RS = 8.1 m CMRR calibrated at mid VCM range ERROR SOURCE 77.9 V 77.9 V PSRR calibrated at 5 V 8.9 V 8.9 V Total error (squared sum of contribution) Resolution (Total error / RS) 78 V 78 V 19.2 mA 9.6 mA Table 3. Accuracy Calculation ERROR SOURCE RS = 4.1 m RS = 8.1 m Tc Vos 182 V 182 V Nosie 216 V 216 V Gain drift 75.2 V 151 V Total error (squared sum of contribution) 293 V 320 V 0.7% 0.4% Accuracy 100*(Max_VSENSE / Total Error) From the tables above is clear that the 8.2 m shunt resistor allows the respect of the project's constraints. The power burned on the Shunt is 820 mW at 10 A. 9.2.3 Application Performance Plot 5 VOUT (V) 4 3 2 1 Vout 0 0 2 4 6 LOAD CURRENT (A) 8 10 C001 Figure 28. Application Example Results using 8.2 m Resistor Copyright (c) 2010-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV 19 LMP8640, LMP8640-Q1, LMP8640HV SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 www.ti.com 9.3 Do's and Don'ts Do properly bypass the power supplies. Do add series resistance to the output when driving capacitive loads, cables, long traces, muxes and ADC inputs. Do not exceed the input common mode range. 10 Power Supply Recommendations The input circuitry of the device can accurately measure signals on common-mode voltages beyond its power supply voltage, V+. For example, the voltage applied to the VS power supply terminal can be 5 V, whereas the load power-supply voltage being monitored (the common-mode voltage) can be as high as +76 V. Power-supply bypass capacitors are required for stability and should be placed as closely as possible to the supply and ground terminals of the device. A typical value for this supply bypass capacitor is 0.1 F close to the V+ pin. The capacitors should be rated for at least twice the maximum expected applied voltage. Applications with noisy or high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise. 11 Layout 11.1 Layout Guidelines * * * * * * * * * * * 20 Use 4-wire (Kelvin) connections to the sense resistor. Connect to the resistor at a point that is not within a direct high-current path (See Figure 29). Do not "share" part of the sense trace path with the load current. Maintain proper clearance and spacings around the input traces, as they may be at a higher voltage (up to 76 V) than the surrounding traces and planes. Input traces from the sense resistor pads should follow the same path, be spaced tightly together, and ideally on the same copper layer. Vias used in the input traces should be of continuous plated copper to avoid creating thermocouples. Avoid routing inputs through jumpers and connectors. Even the best connectors introduce thermal errors ("thermocouples"). Each input trace should have the same number of "thermocouples" if they cannot be avoided. Keep the amplifier away from heat generating devices. The copper-solder-lead junction on the input pins will form a thermocouple. The copper mass should be equal on both input pins. Avoid temperature gradients across the input pins. Input pins should be equal distance to the heat source. Place the LMP8640 in the most temperature-stable area possible and away from high-velocity air flows. It is better to carefully extend the input traces than to place the amplifier in a less-than-ideal environment. Give the sense resistor as much copper trace area as possible to dissipate heat as the resistor value will change slightly with temperature. Also see the resistor manufacturers datasheet or application notes for further layout guidelines. The power-supply bypass capacitor should be placed as closely as possible to the supply and ground terminals. The recommended value of this bypass capacitor is 0.1 F. Additional decoupling capacitance can be added to compensate for noisy or high-impedance power supplies. Submit Documentation Feedback Copyright (c) 2010-2014, Texas Instruments Incorporated Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV LMP8640, LMP8640-Q1, LMP8640HV www.ti.com SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 11.2 Layout Example Figure 29. Layout Example - Kelvin Connection to a Two-Terminal Resistor Copyright (c) 2010-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV 21 LMP8640, LMP8640-Q1, LMP8640HV SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 www.ti.com Layout Example (continued) Figure 30. Layout Example - Four-Wire (Kelvin) Resistor Connection 22 Submit Documentation Feedback Copyright (c) 2010-2014, Texas Instruments Incorporated Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV LMP8640, LMP8640-Q1, LMP8640HV www.ti.com SNOSB28G - AUGUST 2010 - REVISED NOVEMBER 2014 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support * Evaluation Board for LMP8640HV-F, http://www.ti.com/tool/lmp8640hv-feval * Evaluation Board for LMP8640HV-H, http://www.ti.com/tool/lmp8640hv-heval * Evaluation Board for LMP8640HV-T, http://www.ti.com/tool/lmp8640hv-teval * TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti 12.2 Documentation Support 12.2.1 Related Documentation For related documantation, see the following: * AN-1975 LMP8640 / LMP8645 Evaluation Board User Guide, SNOA546 * Absolute Maximum Ratings for Soldering, SNOA549 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 4. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMP8640 Click here Click here Click here Click here Click here LMP8640-Q1 Click here Click here Click here Click here Click here LMP8640HV Click here Click here Click here Click here Click here 12.4 Trademarks All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright (c) 2010-2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMP8640 LMP8640-Q1 LMP8640HV 23 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMP8640HVMK-F/NOPB ACTIVE SOT-23-THIN DDC 6 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AD6A LMP8640HVMK-H/NOPB ACTIVE SOT-23-THIN DDC 6 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AF6A LMP8640HVMK-T/NOPB ACTIVE SOT-23-THIN DDC 6 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AB6A LMP8640HVMKE-F/NOPB ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AD6A LMP8640HVMKE-H/NOPB ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AF6A LMP8640HVMKE-T/NOPB ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AB6A LMP8640HVMKX-F/NOPB ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AD6A LMP8640HVMKX-H/NOPB ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AF6A LMP8640HVMKX-T/NOPB ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AB6A LMP8640MK-F/NOPB ACTIVE SOT-23-THIN DDC 6 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AC6A LMP8640MK-H/NOPB ACTIVE SOT-23-THIN DDC 6 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AE6A LMP8640MK-T/NOPB ACTIVE SOT-23-THIN DDC 6 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AA6A LMP8640MKE-F/NOPB ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AC6A LMP8640MKE-H/NOPB ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AE6A LMP8640MKE-T/NOPB ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AA6A LMP8640MKX-F/NOPB ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AC6A LMP8640MKX-H/NOPB ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AE6A LMP8640MKX-T/NOPB ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AA6A LMP8640QMKE-T/NOPB ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AUAA LMP8640QMKX-T/NOPB ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM -40 to 125 AUAA Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LMP8640, LMP8640-Q1 : * Catalog: LMP8640 * Automotive: LMP8640-Q1 NOTE: Qualified Version Definitions: Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 25-Aug-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LMP8640HVMK-F/NOPB SOT23-THIN DDC 6 1000 178.0 8.4 LMP8640HVMK-H/NOPB SOT23-THIN DDC 6 1000 178.0 LMP8640HVMK-T/NOPB SOT23-THIN DDC 6 1000 LMP8640HVMKE-F/NOPB SOT23-THIN DDC 6 LMP8640HVMKE-H/NOP B SOT23-THIN DDC LMP8640HVMKE-T/NOPB SOT23-THIN LMP8640HVMKX-F/NOPB 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DDC 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP8640HVMKX-H/NOP B SOT23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP8640HVMKX-T/NOPB SOT23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP8640MK-F/NOPB SOT23-THIN DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP8640MK-H/NOPB SOT- DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 25-Aug-2018 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 23-THIN LMP8640MK-T/NOPB SOT23-THIN DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP8640MKE-F/NOPB SOT23-THIN DDC 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP8640MKE-H/NOPB SOT23-THIN DDC 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP8640MKE-T/NOPB SOT23-THIN DDC 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP8640MKX-F/NOPB SOT23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP8640MKX-H/NOPB SOT23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP8640MKX-T/NOPB SOT23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP8640QMKE-T/NOPB SOT23-THIN DDC 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP8640QMKX-T/NOPB SOT23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP8640HVMK-F/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 25-Aug-2018 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP8640HVMK-H/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0 LMP8640HVMK-T/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0 LMP8640HVMKE-F/NOPB SOT-23-THIN DDC 6 250 210.0 185.0 35.0 LMP8640HVMKE-H/NOPB SOT-23-THIN DDC 6 250 210.0 185.0 35.0 LMP8640HVMKE-T/NOPB SOT-23-THIN DDC 6 250 210.0 185.0 35.0 LMP8640HVMKX-F/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 LMP8640HVMKX-H/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 LMP8640HVMKX-T/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 LMP8640MK-F/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0 LMP8640MK-H/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0 LMP8640MK-T/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0 LMP8640MKE-F/NOPB SOT-23-THIN DDC 6 250 210.0 185.0 35.0 LMP8640MKE-H/NOPB SOT-23-THIN DDC 6 250 210.0 185.0 35.0 LMP8640MKE-T/NOPB SOT-23-THIN DDC 6 250 210.0 185.0 35.0 LMP8640MKX-F/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 LMP8640MKX-H/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 LMP8640MKX-T/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 LMP8640QMKE-T/NOPB SOT-23-THIN DDC 6 250 210.0 185.0 35.0 LMP8640QMKX-T/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 Pack Materials-Page 3 PACKAGE OUTLINE DDC0006A SOT - 1.1 max height SCALE 4.000 SOT 3.05 2.55 1.75 1.45 PIN 1 INDEX AREA 1.100 0.847 B 1 0.1 C A 6 4X 0.95 3.05 2.75 1.9 4 3 0.5 0.3 0.2 0.1 TYP 0.0 6X C 0 -8 TYP 0.20 TYP 0.12 C A B SEATING PLANE 0.6 TYP 0.3 0.25 GAGE PLANE 4214841/B 11/2020 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC MO-193. www.ti.com EXAMPLE BOARD LAYOUT DDC0006A SOT - 1.1 max height SOT SYMM 6X (1.1) 1 6 6X (0.6) SYMM 4X (0.95) 4 3 (R0.05) TYP (2.7) LAND PATTERN EXAMPLE EXPLOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED SOLDER MASK DEFINED SOLDERMASK DETAILS 4214841/B 11/2020 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DDC0006A SOT - 1.1 max height SOT SYMM 6X (1.1) 1 6 6X (0.6) SYMM 4X(0.95) 4 3 (R0.05) TYP (2.7) SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X 4214841/B 11/2020 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. 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