QT3-R-5-M-FREQ2 - Q-TECH Corporation

Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com

Q-TECH

CORPORATION

TRANSISTOR OUTLINE PACKAGES

TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS

1.8 to 15Vdc - 0.045Hz to 125MHz

Transistor Outline Packages (Revision A, May 2008) (ECO# 9304)

Description

Q-Tech’s Transistor Outline package crystal oscillators

consist of a source clock square wave generator, logic

output buffers and/or logic divider stages, and a round AT

high-precision quartz crystal built in an all metal TO

package.

Features

• Made in the USA

• ECCN: EAR99

• DFARS (Berry Amendment) Compliant

• USML Registration # M17677

• Wide frequency range from 0.045Hz to 125MHz

• Available as QPL MIL-PRF-55310/09 and/10 (TTL)

and /12 (CMOS)

• Choice of TO packages and pin outs

• Choice of supply voltages

• Choice of output logic options ( CMOS, ACMOS,

HCMOS, LVHCMOS, and TTL)

• AT-Cut crystal

• All metal hermetically sealed package

• Tight or custom symmetry available

• Low height available

• External tuning capacitor option

• Fundamental and third overtone designs

• Tristate function option D

• Three-point crystal mounts

• Custom design available tailors to meet customer’s

needs

• Q-Tech does not use pure lead or pure tin in its

products

• RoHS compliant

Applications

• Designed to meet today’s requirements for all voltage

applications

• Wide military clock applications

• Industrial controls

• Microcontroller driver

Model #

Ordering Information

QTXX — XX — D — XX — M — 60.000MHz

Output frequency

Screened to

MIL-PRF-55310,level B

(Left blank if no screening)

1 = ± 100ppm at 0ºC to +70ºC

3** = ± 5ppm at 0ºC to +50ºC

4 = ± 50ppm at 0ºC to +70ºC

5 = ± 25ppm at -20ºC to +70ºC

6 = ± 50ppm at -55ºC to +105ºC

9 = ± 50ppm at -55ºC to +125ºC

10 = ± 100ppm at -55ºC to +125ºC

11 = ± 50ppm at -40ºC to +85ºC

12 = ± 100ppm at -40ºC to +85ºC

Tristate Option D

(Left blank if no Tristate)

For Non-Standard requirements, contact Q-Tech Corporation at

Sales@Q-Tech.com

C = CMOS +5V to +15V *

AC = ACMOS +5V

HC = HCMOS +5V

T = TTL +5V

L = LVHCMOS + 3.3V

N = LVHCMOS + 2.5V

R = LVHCMOS + 1.8V

Z = Z output

Specifications subject to change without prior notice.

All Transistor Outline packages are available in surface mount form.

Packaging Options

Other Options Available For An Additional Charge

• Standard packaging in black foam

• Solder Dip Sn/Pb 60/40%

• P. I. N. D. test

• Lead trimming

For frequency stability vs. temperature options not listed herein, please request a

custom part number.

(*) Please specify supply voltage when ordering CMOS

(**) Require an external capacitor

Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com

Q-TECH

CORPORATION

TRANSISTOR OUTLINE PACKAGES

TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS

1.8 to 15Vdc - 0.045Hz to 125MHz

Transistor Outline Packages (Revision A, May 2008) (ECO# 9304)

Electrical Characteristics

Parameters CAC HC T L (*)

Output freq. range (Fo)

QT1, 14

244Hz — 15MHz

732.4Hz — 85MHz 732.4Hz — 125MHz

QT2 0.045Hz — 85MHz 0.045Hz — 85MHz

QT3 732.4Hz — 85MHz 732.4Hz — 85MHz

Supply voltage (Vdd) 5V ~ 15Vdc ± 10% 5.0Vdc ± 10% 3.3Vdc ± 10%

Freq. stability (∆F/∆T) See Option codes

Operating temp. (Topr) See Option codes

Storage temp. (Tsto) -62ºC to + 125ºC

Operating supply current

(Idd) (No Load)

F and Vdd dependent

3 mA max. at 5V up to 5MHz

25 mA max. at 15V up to 15MHz

20 mA max. - 0.045Hz ~ < 16MHz

25 mA max. - 16MHz ~ < 40MHz

35 mA max. - 40MHz ~ < 60MHz

45 mA max. - 60MHz ~ 85MHz

3 mA max. - 0.045Hz ~ < 500kHz

6 mA max. - 500kHz ~ < 16MHz

10 mA max. - 16MHz ~ < 32MHz

20 mA max. - 32MHz ~ < 60MHz

30 mA max. - 60MHz ~ < 100MHz

40 mA max. - 100MHz ~ 125MHz

Symmetry

(50% of ouput waveform or 1.4Vdc for

TTL)

45/55% max. Fo < 4MHz

40/60% max. Fo ≥ 4MHz

45/55% max. Fo < 12MHz

40/60% max. Fo ≥ 12MHz

Rise and Fall times

(with typical load)

30ns max.

(Measured from 10% to 90%)

15ns max. Fo < 15kHz

6ns max. Fo 15kHz ~ 39.999MHz

3ns max. Fo 40MHz ~ 125 MHz

(Measured from 10% to 90% CMOS or from 0.8V to 2.0V TTL)

Output Load 15pF // 10kΩ 10TTL Fo < 20MHz

6TTL Fo ≥ 20MHz

15pF // 10kΩ

Start-up time (Tstup) 10ms max.

Output voltage (Voh/Vol) 0.9 x Vdd min.; 0.1 x Vdd max. 2.4V min.; 0.4V max. 0.9 x Vdd min.; 0.1 x Vdd max.

Output Current (Ioh/Iol) ± 1mA typ. at 5V

± 6.8mA typ. at 15V

± 24mA ±8 mA -1.6mA / TTL

+40µA / TTL

± 4mA .

Enable/Disable

Tristate function Pin 1 Call for details VIH ≥ 2.2V Oscillation;

VIL ≤ 0.8V High Impedance

VIH ≥ 0.7 x Vdd Oscillation;

VIL ≤ 0.3 x Vdd High Impedance

Jitter RMS 1σ (at 25ºC) 8ps typ. - < 40MHz

5ps typ. - ≥ 40MHz

15ps typ. - < 40MHz

8ps typ. - ≥ 40MHz

Aging (at 70ºC) ± 5ppm max. first year / ± 2ppm typ. per year thereafter

(*) Available in 2.5Vdc (N) or 1.8Vdc (R)

Z Output logic can drive up to 200 pF load with typical 6ns rise & fall times (tr, tf)

ECL, PECL, LVPECL are available. Please contact Q-Tech for details.

Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com

Q-TECH

CORPORATION

TRANSISTOR OUTLINE PACKAGES

TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS

1.8 to 15Vdc - 0.045Hz to 125MHz

Transistor Outline Packages (Revision A, May 2008) (ECO# 9304)

Package Configuration Versus Pin Connections

(6.60)

.260

.500

(12.70)

(.457)

.018

(5.08)

.200

PIN No. 1

(9.14)

.360

FREQ.

D/C S/N

P/N

Q-TECH

MAX.

MIN.

QT1

MIN.

Q-TECH

P/N

FREQ.

D/C S/N

.360

(9.14)

PIN No. 1

.200

(5.08)

.018

(.457)

(12.70)

.500

.175

(4.45)

QT14

Q-TECH

P/N

PIN No. 1

.500

(12.70)

.075

(1.91)

.300

(7.62)

(5.08)

.200

FREQ.

D/C S/N

.018

(.457)

.500

(12.70)

MIN.

MAX.

QT2

PIN No. 1

(7.16)

.282

(13.72)

.540

Q-TECH

P/N

FREQ.

D/C S/N

.500

(12.70)MIN.

(.457)

.018

MAX.

(7.62)

.300

QT3

QT # Conf Vcc GND Case Output E/D Ext. Cap

Equivalent

MIL-PRF-55310

Configuration

QT1 A 8 4 4 5 1 1 & 2 /09 = QT1T

/12 = QT1C

QT2 B 12 6 6 5 3 9 & 10 N/A

QT3 C 8 4 4 5 1 1&2 /10 = QT3T

/13 = QT3C

QT14 D 8 4 4 5 1 1 & 2 N/A

Dimensions are in inches (mm)

Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com

Q-TECH

CORPORATION

TRANSISTOR OUTLINE PACKAGES

TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS

1.8 to 15Vdc - 0.045Hz to 125MHz

Transistor Outline Packages (Revision A, May 2008) (ECO# 9304)

1 2

QT1T3

+5VDC

GND

OUTPUT

0.01uF

20pF(*)

270

Cext

D1-D4: 1N4148 or equivalent

(*) CL includes scope probe capacitance

TYPICAL TEST CIRCUIT FOR QT1T3 (10TTL)

Frequency vs. Temperature Curve

-50

-40

-30

-20

-10

-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0510 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125

SN2 SN3 SN4 SN1

Frequency Stability (PPM)

FREQUENCY STABILITY VERSUS TEMPERATURE QT1L -36MHz

Temperature (°C)

Vdd

GND

0.1xVdd

0.9xVdd

VOH

VOL

TrTf

0.5xVdd

SYMMETRY = x 100%

Start-up box

Oscilloscope

DUT

Variable Ramp

54616B Agilent

TYPICAL SET-UP FOR START-UP TIME

Output Waveform (Typical)

Startup Time

Supply Current

Test Circuit

Output

Ground

Vdd Out

GND

0.1µF

15pF

E/D

Tristate Function

Power

supply 10k

Vdc

(*)

0.01µF

(*) CL includes probe and jig capacitance

Typical test circuit for CMOS logic

0.5 2816 24 27 32 36 40 48 50 55 65 70 75 85 100 125 133 150 160

Freq(MHz)

Icc (mA)

TYPICAL SUPPLY CURRENT ICC (mA) AT 3.3Vdc & 5.0Vdc CMOS Logic NO LOAD

Icc 3.3V Icc 5V

POWER

SUPPLY

0.1µF

Vdc

Vdd OUT

OUT

GND

Typical test circuit for TTL logic.

0.01µF Rs

(*) CL inclides the loading effect of the oscilloscope probe.

E/D

LOAD

6 TTL

10 TTL

CL(*)

12pF

20pF

430Ω

270Ω

10kΩ

6kΩ

Vdd

The Tristate function on pin 1 has a built-in pull-up resistor typical 50kΩ, so it

can be left floating or tied to Vdd without deteriorating the electrical performance.

Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com

Q-TECH

CORPORATION

TRANSISTOR OUTLINE PACKAGES

TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS

1.8 to 15Vdc - 0.045Hz to 125MHz

Transistor Outline Packages (Revision A, May 2008) (ECO# 9304)

45º 45º

Hybrid Case

Substrate

Die

D/A epoxy

Heat

Die

D/A epoxy Substrate D/A epoxy Hybrid Case

R2 R3 R4 R5

Thermal Characteristics

JA JC CA

Die

(Figure 1)

(Figure 2)

The heat transfer model in a hybrid package is described in

figure 1.

Heat spreading occurs when heat flows into a material layer of

increased cross-sectional area. It is adequate to assume that

spreading occurs at a 45° angle.

The total thermal resistance is calculated by summing the

thermal resistances of each material in the thermal path

between the device and hybrid case.

RT=R1+R2+R3+R4+R5

The total thermal resistance RT (see figure 2) between the heat

source (die) to the hybrid case is the Theta Junction to Case

(Theta JC) in°C/W.

• Theta junction to case (Theta JC) for this product is 30°C/W.

• Theta case to ambient (Theta CA) for this part is 100°C/W.

• Theta Junction to ambient (Theta JA) is 130°C/W.

Maximum power dissipation PD for this package at 25°C is:

• PD(max) = (TJ (max) – TA)/Theta JA

• With TJ = 175°C (Maximum junction temperature of die)

• PD(max) = (175 – 25)/130 = 1.15W

Environmental Specifications

Q-Tech Standard Screening/QCI (MIL-PRF55310) is available for all of our Transistor Outline packages. Q-Tech can also customize

screening and test procedures to meet your specific requirements. The Transistor Outline packages are designed and processed to

exceed the following test conditions:

Environmental Test Test Conditions

Temperature cycling MIL-STD-883, Method 1010, Cond. B

Constant acceleration MIL-STD-883, Method 2001, Cond. A, Y1

Seal Fine Leak MIL-STD-883, Method 1014, Cond. A

Burn-in 160 hours, 125°C with load

Aging 30 days, 70°C

Vibration sinusoidal MIL-STD-202, Method 204, Cond. D

Shock, non operating MIL-STD-202, Method 213, Cond. I

Thermal shock, non operating MIL-STD-202, Method 107, Cond. B

Ambient pressure, non operating MIL-STD-202, 105, Cond. C, 5 minutes dwell time minimum

Resistance to solder heat MIL-STD-202, Method 210, Cond. C

Moisture resistance MIL-STD-202, Method 106

Terminal strength MIL-STD-202, Method 211, Cond. C

Resistance to solvents MIL-STD-202, Method 215

Solderability MIL-STD-202, Method 208

Please contact Q-Tech for higher shock requirements

Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com

Q-TECH

CORPORATION

TRANSISTOR OUTLINE PACKAGES

TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS

1.8 to 15Vdc - 0.045Hz to 125MHz

Transistor Outline Packages (Revision A, May 2008) (ECO# 9304)

Phase noise is measured in the frequency domain, and is expressed as a ratio of signal power to noise power measured in a 1Hz

bandwidth at an offset frequency from the carrier, e.g. 10Hz, 100Hz, 1kHz, 10kHz, 100kHz, etc. Phase noise measurement is made

with an Agilent E5052A Signal Source Analyzer (SSA) with built-in outstanding low-noise DC power supply source. The DC source

is floated from the ground and isolated from external noise to ensure accuracy and repeatability.

In order to determine the total noise power over a certain frequency range (bandwidth), the time domain must be analyzed in the

frequency domain, and then reconstructed in the time domain into an rms value with the unwanted frequencies excluded. This may be

done by converting L(f) back to Sφ(f) over the bandwidth of interest, integrating and performing some calculations.

The value of RMS jitter over the bandwidth of interest, e.g. 10kHz to 20MHz, 10Hz to 20MHz, represents 1 standard deviation of

phase jitter contributed by the noise in that defined bandwidth.

Figure below shows a typical Phase Noise/Phase jitter of a QT1ACD10M, 5.0Vdc, 40MHz clock at offset frequencies 10Hz to 5MHz,

and phase jitter integrated over the bandwidth of 12kHz to 1MHz.

Phase Noise and Phase Jitter Integration

Period Jitter

As data rates increase, effects of jitter become critical with

its budgets tighter. Jitter is the deviation of a timing event of

a signal from its ideal position. Jitter is complex and is

composed of both random and deterministic jitter

components. Random jitter (RJ) is theoretically unbounded

and Gaussian in distribution. Deterministic jitter (DJ) is

bounded and does not follow any predictable distribution.

DJ is also referred to as systematic jitter. A technique to

measure period jitter (RMS) one standard deviation (1σ) and

peak-to-peak jitter in time domain is to use a high sampling

rate (>8G samples/s) digitizing oscilloscope. Figure shows

an example of peak-to-peak jitter and RMS jitter (1σ) of a

QT1ACD-40MHz, at 5.0Vdc.

RMS jitter (1σ): 4.89ps Peak-to-peak jitter: 44.4ps

Symbol

Definition

∫L(f) Integrated single side band phase noise (dBc)

Sφ (f)=(180/Π)x√2 ∫L(f)df Spectral density of phase modulation, also known as RMS phase error (in degrees

RMS jitter = Sφ (f)/(fosc.360°) Jitter(in seconds) due to phase noise. Note Sφ (f) in degrees.

QT1ACD10M, 5.0Vdc - 40MHz