1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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CA-3083
General Purpose High Current NPN
Transistor Array
The CA3083 is a versatile array of five high current (to
100mA) NPN transistors on a common monolithic substrate.
In addition, two of these transistors (Q1 and Q2) are
matched at low current (i.e., 1mA) for applications in which
offset para meters are of special importance.
Independent connections for each transistor plus a separate
terminal for the substrate permit maximum flexibility in circuit
design.
Features
• High IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA (Max)
•Low V
CE sat (at 50mA). . . . . . . . . . . . . . . . . . . 0.7V (Max)
• Matched Pair (Q1 and Q2)
-V
IO (VBE Match). . . . . . . . . . . . . . . . . . . . . ±5mV (Max)
-I
IO (at 1mA) . . . . . . . . . . . . . . . . . . . . . . . . 2.5μA (Max)
• 5 Independent Transistors Plus Separate Substrate
Connection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Signal Processing and Switching Systems Operating from
DC to VHF
• Lamp and Relay Driver
• Differential Amplifier
• Temperature Compensated Amplifier
• Thyristor Firing
• See Application Note AN5296 “Applications of the
CA3018 Circuit Transistor Array” for Suggested
Applications
Pinout
CA3083
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART
NUMBER PART
MARKING
TEMP.
RANGE
(°C) PACKAGE PKG.
DWG. #
CA3083 CA3083 -55 to 125 16 Ld PDIP E16.3
CA3083Z
(Note) CA3083Z -55 to 125 16 Ld PDIP* (Pb-free) E16.3
CA3083M96 3083 -55 to 125 16 Ld SOIC
Tape and Reel M16.15
CA3083MZ
(Note) 3083MZ -55 to 125 16 Ld SOIC (Pb-Free) M16.15
CA3083MZ96
(Note) 3083MZ -55 to 125 16 Ld SOIC (Pb-Free)
Tape and Reel M16.15
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
NOTE: Intersil Pb-free plus anneal product s employ spe cial Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish , which a r e RoHS com plia nt a nd com patible
with both SnPb and Pb-f ree solder in g op erations. Int ersil Pb-free
products are MSL cla ssified at Pb-fre e peak reflow temperatu res that
meet or exceed the Pb-f ree re quireme nts of IPC/JEDEC J STD-020.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
SUBSTRATE
Q1
Q2
Q3
Q4
Q5
Data Sheet December 15, 2011 FN481.7
2FN481.7
December 15, 2011
Absolute Maximum Ratings Thermal Information
The following ratings apply for each transistor in the device:
Collector-to-Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . . . 15V
Collector-to-Base Voltage, VCBO. . . . . . . . . . . . . . . . . . . . . . . . 20V
Collector-to-Substrate Voltage, VCIO (Note 1). . . . . . . . . . . . . . 20V
Emitter-to-Base Voltage, VEBO . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Collector Current (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Base Current (IB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to 125°C
Thermal Resistance (Typical, Note 2) θJA (°C/W) θJC (°C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . 135 N/A
SOIC Package . . . . . . . . . . . . . . . . . . . 200 N/A
Maximum Power Dissipation (Any One Transistor). . . . . . . 500mW
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3083 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage
which is more negative than any collector voltage in order to maintain isolation between transistors and provide normal transistor action. To
avoid undesired coupling between transistors, the substrate Terminal (5) should be maintained at either DC or signal (AC) ground. A suitable
bypass capacitor can be used to establish a signal ground.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications For Equipment Design, TA = 25°C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
FOR EACH TRANSISTOR
Collector-to-Base Breakdown Voltage V(BR)CBO IC = 100μA, IE = 0 20 60 - V
Collector-to-Emitter Breakdown Voltage V(BR)CEO IC = 1mA, IB = 0 15 24 - V
Collector-to-Substrate Breakdown Voltage V(BR)CIO ICI = 100μA, IB = 0, IE = 0 20 60 - V
Emitter-to-Base Breakdown Voltage V(BR)EBO IE = 500μA, IC = 0 5 6.9 - V
Collector-Cutoff-Current ICEO VCE = 10V, IB = 0 - - 10 μA
Collector-Cutoff-Current ICBO VCB = 10V, IE = 0 - - 1 μA
DC Forward-Current Transfer Ratio (Note 3) (Figure 1) hFE VCE = 3V IC = 10mA 40 76 -
IC = 50mA 40 75 -
Base-to-Emitter Voltage (Figure 2) VBE VCE = 3V, IC = 10mA 0.65 0.74 0.85 V
Collector-to-E mitte r Satu rati on Voltag e (Figu res 3, 4) VCE SAT IC = 50mA, IB = 5mA - 0.40 0.70 V
Gain Bandwidth Product fTVCE = 3V, IC = 10mA - 450 - MHz
FOR TRANSISTORS Q1 AND Q2(As a Differential Amplifier)
Absolute Input Offset Voltage (Figure 6) |VIO|V
CE = 3V, IC = 1mA - 1.2 5 mV
Absolute Input Offset Current (Figure 7) |IIO|V
CE = 3V, IC = 1mA - 0.7 2.5 μA
NOTE:
3. Actual forcing current is via the emitter for this test.
CA-3083
3FN481.7
December 15, 2011
Typical Performance Curves
FIGURE 1. hFE vs ICFIGURE 2. VBE vs IC
FIGURE 3. VCE SAT vs ICFIGURE 4. VCE SAT vs IC
FIGURE 5. VBE SAT vs ICFIGURE 6. VIO vs IC (TRANSISTORS Q1 AND Q2 AS A
DIFFERENTIAL AMPLIFIER)
VCE = 3V
COLLECTOR CURRENT (mA)
DC FORWARD CURRENT TRANSFER RATIO
TA = 0°C
TA = 25°C
0.1 1 10 100
60
50
70
80
90
100
TA = 70°C
VCE = 3V
COLLECTOR CURRENT (mA)
BASE-TO-EMITTER VOLTAGE (V)
TA = 70°C
TA = 25°C
0.1 1 10 100
0.6
0.5
0.7
0.8
0.9
TA = 0°C
hFE = 10, TA = 25oC
COLLECTOR CURRENT (mA)
COLLECTOR-TO-EMITTER
1 10 100
0.2
0
0.4
0.6
0.8
1
MAXIMUM
TYPICAL
SATURATION VOLTAGE (V)
COLLECTOR CURRENT (mA)
COLLECTOR-TO-EMITTER
110100
0.2
0
0.4
0.6
0.8
1
1.2
MAXIMUM
hFE = 10, TA = 70°C
TYPICAL
SATURATION VOLTAGE (V)
hFE = 10, TA = 25°C
COLLECTOR CURRENT (mA)
BASE-TO-EMITTER
110100
0.6
0.5
0.7
0.8
0.9
1
SATURATION VOLT AGE (V)
VCE = 3V, TA = 25°C
COLLECTOR CURRENT (mA)
ABSOLUTE INPUT OFFSET VOLTAGE (mV)
0.1 1 10
1
0
2
3
4
5
6
CA-3083
4
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of I nter sil or its subsidiaries.
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FN481.7
December 15, 2011
FIGURE 7. IIO vs IC (TRANSISTORS Q1 AND Q2 AS A DIFFERENTIAL AMPLIFIER)
Typical Performance Curves (Continued)
VCE = 3V, TA = 25°C
COLLECTOR CURRENT (mA)
ABSOLUTE INPUT OFFSET CURRENT (μA)
0.1 1 10
1
10
0.1
CA-3083
