IBM11M4730C4M x 72 E12/10, 5.0V, Au. IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE Features * 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-line Memory Module * 16Mx64, 16Mx72 Extended Data Out Page Mode DIMMS * Performance: -60 * System Performance Benefits: -Non buffered for increased performance -Reduced noise (35 VSS/VCC pins) -Byte write, byte read accesses -Serial PDs * Extended Data Out (EDO) Mode, Read-ModifyWrite Cycles tRAC RAS Access Time 60ns tCAC CAS Access Time 15ns tAA Access Time From Address 30ns * Refresh Modes: RAS-Only, CBR and Hidden Refresh tRC Cycle Time 104ns * CAS before RAS Refresh - 4096 cycles tHPC EDO Mode Cycle Time 25ns * All inputs and outputs are LVTTL (3.3V) compatible * Single 3.3V 0.3V Power Supply * Au contacts * Optimized for byte-write non-parity, or ECC applications * RAS only Refresh - 4096 cycles (12/12 addressing) - 8192 cycles (13/11 addressing) * 12/12 or 13/11 addressing (Row/Column) * Card size: 5.25" x 1.5" x 0.354" * DRAMS in SOJ Package Description IBM11N16645B IBM11N16645C are industry standard 168-pin 8-byte Dual In-line Memory Modules (DIMMs) which are organized as 16Mx64 and 16Mx72 high speed memory arrays designed with EDO DRAMs for non-parity or ECC applications. The DIMMs use 16 (x64) or 18 (x72) 16Mx4 EDO DRAMs in SOJ packages. The use of EDO DRAMs allows for a reduction in Page Mode Cycle time from 40ns (Fast Page) to 25ns for 60ns DRAM modules. The DIMMs use serial presence detects implemented via a serial EEPROM using the two pin I2C protocol. This communication protocol uses Clock (SCL) and Data I/O (SDA) lines to synchronously clock data between the master (system logic) and the slave EEPROM device (DIMM). The EEPROM device address pins (SA0-2) are brought out to the DIMM tabs to allow 8 unique DIMM/EEPROM addresses. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes of serial PD data are available to the customer. All IBM 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 5.25" long space-saving footprint. Related products include the buffered DIMMs (x64, x72 parity and x72 ECC Optmized) for applications which can benefit from the on-card buffers. Card Outline (Front) (Back) 1 85 75H1640 SA14-4626-01 Released 5/96 10 11 94 95 40 41 124 125 84 168 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE Pin Description RAS0, RAS2 Row Address Strobe VCC Power (3.3V) CAS0 - CAS7 Column Address Strobe VSS Ground WE0, WE2 Read/write Input NC No Connect OE0, OE2 Output Enable DU Don't Use A0 - A12 Address Inputs SCL Serial Presence Detect Clock Input DQx Data Input/Output CBx Check Bit Data Input/Output SDA Serial Presence Detect Data Input SA0-2 Serial Presence Detect Address Inputs Pinout Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Front Side Pin# VSS 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 Back Side Pin# Front Side VSS 22 DQ32 DQ33 DQ34 DQ35 VCC 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 CB1 VSS NC NC VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 WE0 CAS0 CAS1 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 A12 VCC VCC DU Pin# Back Side Pin# 106 CB5 VSS NC NC VCC 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 DU CAS4 CAS5 NC DU VSS A1 A3 A5 A7 A9 A11 NC VCC DU DU Front Side Pin# Back Side VSS 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 VSS 64 VSS 148 VSS DU NC CAS6 CAS7 DU VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ21 DQ22 DQ23 VSS 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ53 DQ54 DQ55 VSS OE2 RAS2 CAS2 CAS3 WE2 VCC NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC DU NC DQ52 NC DU NC Pin# Front Side DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS NC NC NC SDA SCL VCC Pin# Back Side DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS NC NC SA0 SA1 SA2 VCC Note: All pin assignments are consistent for all 8 Byte unbuffered versions. Ordering Information Part Number Organization Speed IBM11N16645BB-60 16Mx64 60ns IBM11N16645CB-60 16Mx64 60ns IBM11N16735BB-60 16Mx72 60ns IBM11N16735CB-60 16Mx72 60ns (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 30 Addr. 12/12 13/11 Leads Dimension Power Au 5.25"x1.0"x 0.354" 3.3V Au 5.25"x1.0"x 0.354" 3.3V Au 5.25"x1.0"x 0.354" 3.3V Au 5.25"x1.0"x 0.354" 3.3V 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE x64 DIMM Block Diagram (1 Bank, x4 DRAMs) OE0 WE0 CAS0 OE2 WE2 RAS0 CAS4 CAS RAS WE I/O 0 I/O 1 D0 I/O 2 I/O 3 OE DQ0 DQ1 DQ2 DQ3 CAS RAS WE I/O 0 I/O 1 D1 I/O 2 I/O 3 OE DQ4 DQ5 DQ6 DQ7 OE DQ8 DQ9 DQ10 DQ11 CAS RAS WE I/O 0 I/O 1 D2 I/O 2 I/O 3 CAS RAS WE I/O 0 I/O 1 D3 I/O 2 I/O 3 OE DQ12 DQ13 DQ14 DQ15 OE DQ16 DQ17 DQ18 DQ19 CAS RAS WE I/O 0 I/O 1 D4 I/O 2 I/O 3 CAS RAS WE I/O 0 I/O 1 D5 I/O 2 I/O 3 OE DQ20 DQ21 DQ22 DQ23 CAS1 RAS2 CAS RAS WE I/O 0 I/O 1 D8 I/O 2 I/O 3 OE DQ32 DQ33 DQ34 DQ35 CAS RAS WE I/O 0 I/O 1 D9 I/O 2 I/O 3 OE DQ36 DQ37 DQ38 DQ39 CAS RAS WE I/O 0 I/O 1 D10 I/O 2 I/O 3 OE DQ40 DQ41 DQ42 DQ43 CAS RAS WE I/O 0 I/O 1 D11 I/O 2 I/O 3 OE DQ44 DQ45 DQ46 DQ47 CAS RAS WE I/O 0 I/O 1 D12 I/O 2 I/O 3 OE DQ48 DQ49 DQ50 DQ51 CAS RAS WE I/O 0 I/O 1 D13 I/O 2 I/O 3 OE DQ52 DQ53 DQ54 DQ55 CAS5 CAS2 CAS6 SERIAL PD CAS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 75H1640 SA14-4626-01 Released 5/96 SCL CAS7 CAS RAS WE OE I/O 0 I/O 1 D6 I/O 2 I/O 3 CAS RAS WE I/O 0 I/O 1 D7 I/O 2 I/O 3 DQ56 DQ57 DQ58 DQ59 OE DQ60 DQ61 DQ62 DQ63 CAS RAS WE OE I/O 0 I/O 1 D14 I/O 2 I/O 3 CAS RAS WE I/O 0 I/O 1 D15 I/O 2 I/O 3 OE A0-AN SDA A0 A1 A2 SA0 SA1 SA2 A0 - AN: DRAMS D0 - D15 VCC D0 - D15 VSS D0 - D15 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE x72 ECC DIMM Block Diagram (1 Bank, x4 DRAMs) OE0 WE0 CAS0 OE2 WE2 RAS0 CAS4 CAS RAS WE I/O 0 I/O 1 D0 I/O 2 I/O 3 OE DQ0 DQ1 DQ2 DQ3 CAS RAS WE I/O 0 I/O 1 D1 I/O 2 I/O 3 OE DQ4 DQ5 DQ6 DQ7 CAS RAS WE I/O 0 I/O 1 D2 I/O 2 I/O 3 OE DQ8 DQ9 DQ10 DQ11 CAS RAS WE I/O 0 I/O 1 D3 I/O 2 I/O 3 OE DQ12 DQ13 DQ14 DQ15 CAS RAS WE I/O 0 I/O 1 D4 I/O 2 I/O 3 OE CB0 CB1 CB2 CB3 OE DQ16 DQ17 DQ18 DQ19 CAS RAS WE I/O 0 I/O 1 D5 I/O 2 I/O 3 CAS RAS WE I/O 0 I/O 1 D6 I/O 2 I/O 3 OE DQ20 DQ21 DQ22 DQ23 CAS1 CAS RAS WE I/O 0 I/O 1 D10 I/O 2 I/O 3 OE DQ36 DQ37 DQ38 DQ39 CAS RAS WE I/O 0 I/O 1 D11 I/O 2 I/O 3 OE DQ40 DQ41 DQ42 DQ43 CAS RAS WE I/O 0 I/O 1 D12 I/O 2 I/O 3 OE DQ44 DQ45 DQ46 DQ47 CAS RAS WE I/O 0 I/O 1 D13 I/O 2 I/O 3 OE CB4 CB5 CB6 CB7 CAS RAS WE I/O 0 I/O 1 D14 I/O 2 I/O 3 OE DQ48 DQ49 DQ50 DQ51 CAS RAS WE I/O 0 I/O 1 D15 I/O 2 I/O 3 OE DQ52 DQ53 DQ54 DQ55 CAS6 CAS3 DQ28 DQ29 DQ30 DQ31 CAS RAS WE I/O 0 I/O 1 D9 I/O 2 I/O 3 OE DQ32 DQ33 DQ34 DQ35 CAS5 CAS2 DQ24 DQ25 DQ26 DQ27 RAS2 CAS RAS WE I/O 0 I/O 1 D8 I/O 2 I/O 3 DQ56 DQ57 DQ58 DQ59 OE DQ60 DQ61 DQ62 DQ63 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 30 SERIAL PD CAS7 CAS RAS WE OE I/O 0 I/O 1 D7 I/O 2 I/O 3 CAS RAS WE OE I/O 0 I/O 1 D16 I/O 2 I/O 3 CAS RAS WE I/O 0 I/O 1 D17 I/O 2 I/O 3 SCL SDA A0 A1 A2 SA0 SA1 SA2 OE A0-AN A0 - AN: DRAMS D0 - D17 VCC D0 - D17 VSS D0 - D17 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE Truth Table Function RAS CAS WE OE Row Address Column Address DQx Standby H HX X X X X High Impedance Read L L H L Row Col Valid Data Out Early-Write L L L X Row Col Valid Data In Late-Write L L HL H Row Col Valid Data In Valid Data In/Out RMW L L HL LH Row Col EDO Page Mode - Read 1st Cycle L HL H L Row Col Valid Data Out Subsequent Cycles L HL H L N/A Col Valid Data Out EDO Page Mode - Write 1st Cycle L HL L X Row Col Valid Data In Subsequent Cycles L HL L X N/A Col Valid Data In EDO Page Mode - RMW 1st Cycle L HL HL LH Row Col Valid Data In/Out Subsequent Cycles L HL HL LH N/A Col Valid Data In/Out RAS-Only Refresh L H X X Row N/A High Impedance HL L H X X X High Impedance Read LHL L H L Row Col Data Out Write LHL L H X Row Col Data In HL L H X X X High Impedance CAS-Before-RAS Refresh Hidden Refresh Self Refresh Serial Presence Detect SPD Entry Byte # SPD Entry Value Description Binary Bit 7 Bit 6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex 0 Number of SPD Bytes 128 1 0 0 0 0 0 0 0 80 1 Total # Bytes in Serial PD 256 0 0 0 0 1 0 0 0 08 2 Memory Type EDO 0 0 0 0 0 0 1 0 02 12 0 0 0 0 1 1 0 0 0C 3 # of Row Addresses 4 # of Column Addresses 5 # of DIMM Banks 13 0 0 0 0 1 1 0 1 0D 12 0 0 0 0 1 1 0 0 0C 11 0 0 0 0 1 0 1 1 0B 1 0 0 0 0 0 0 0 1 01 x64 0 1 0 0 0 0 0 0 40 x72 0 1 0 0 1 0 0 0 48 0 0 0 0 0 0 0 0 0 00 LVTTL 0 0 0 0 0 0 0 1 01 60 0 0 1 1 1 1 0 0 3C 6 Module Data Width 7 Module Data Width (Cont.) 8 Module Interface Levels 9 RAS Access 60ns 10 CAS Access 15ns 15 0 0 0 0 1 1 1 1 0F x64 None 0 0 0 0 0 0 0 0 00 x72 ECC 0 0 0 0 0 0 1 0 02 Normal 15.6 s 0 0 0 0 0 0 0 0 00 x4 0 0 0 0 0 1 0 0 04 undefined 0 0 0 0 0 0 0 0 00 11 Dimm Config(Error Det/Corr.) 12 Refresh Rate/Type 13 Primary DRAM Organization 14 Secondary DRAM Organization 75H1640 SA14-4626-01 Released 5/96 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE Absolute Maximum Ratings Symbol Parameter VCC Power Supply Voltage VIN Input Voltage VIN/OUT (SPD) Output Voltage TOPR Operating Temperature TSTG Storage Temperature IOUT Notes -0.5 to +4.6 V 1 -0.5 to min (VCC + 0.5, 4.6) V 1 Input Voltage (Serial PD Device) VOUT PD Units Rating (3.3V) Power Dissipation -0.3 to +6.5 V 1 -0.5 to min (VCC + 0.5, 4.6) V 1 0 to +70 C 1 -55 to +125 C 1 W 1 mA 1 12/12 Addressing 13/11 Addressing x64 7.5 6.9 x72 8.5 7.8 Short Circuit Output Current 50 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated is not implied. Exposure to absolute maximum rating condition for extended periods may affect reliability. Recommended DC Operating Conditions (TA = 0 to 70C) 3.3V Symbol Parameter Min Typ Max Units Notes VCC Supply Voltage 3.0 3.3 3.6 V 1 VIH Input High Voltage 2.0 -- VCC + 0.3 V 1, 2 VIL Input Low Voltage -0.3 -- 0.8 V 1, 2 1. All voltages referenced to VSS. 2. VIH may overshoot to VCC + 1.2V for pulse widths of 4.0ns (or VCC + 1.0V for 8.0ns). Additionally, VIL may undershoot to -2.0V for pulse widths 4.0ns (or -1.0V for 8.0ns). Pulse widths measured at 50% points with amplitude measured peak to DC reference. Capacitance (TA = 0 to +70C, VCC = 3.3V 0.3V) Max Symbol Parameter x64 x72 Units CI1 Input Capacitance (A0-A11) 90 100 pF CI2 Input Capacitance (RAS, WE, OE) 70 75 pF CI3 Input Capacitance (CAS) 20 25 pF CI4 Input Capacitance (SCL, SA0-3) 8 8 pF CIO1 Input/Output Capacitance (DQX, CBX) 11 11 pF CIO2 Input/Output Capacitance (SDA) 10 10 pF (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 30 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE DC Electrical Characteristics Symbol (TA= 0 to +70C, VCC= 3.3V 0.3V) 12/12 Addressing 13/11 Addressing x64 x64 Parameter x72 x72 Units Notes Min. Max. Min. Max. Min. Max. Min. Max. ICC1 Operating Current Average Power Supply Operating Current (RAS, CAS, Address Cycling: tRC = tRC min.) ICC2 Standby Current (TTL) Power Supply Standby Current (RAS = CAS = VIH) ICC3 RAS Only Refresh Current Average Power Supply Current, RAS Only Mode (RAS Cycling, CAS = VIH: tRC = tRC min) ICC4 EDO Page Mode Current Average Power Supply Current, EDO Page Mode (RAS = VIL, CAS, Address Cycling: tHPC = tHPC min) ICC5 Standby Current (CMOS) Power Supply Standby Current (RAS = CAS = VCC - 0.2V) ICC6 CAS Before RAS Refresh Current Average Power Supply Current, CAS Before RAS Mode (RAS, CAS, Cycling: tRC = tRC min) II(L) Input Leakage Current Input Leakage Current, any input (0.0 VIN (VCC + 0.3V)), All Other Pins Not Under Test = 0V -60 1, 2, 3 -- 2080 -- 2349 -- 1680 -- 1890 mA -- 32 -- 36 -- 32 -- 36 mA -60 -- 1760 -- 1980 -- 1360 -- 1530 mA 1, 3 -60 -- 1040 -- 1170 -- 1280 -- 1440 mA 1, 2, 3 -- 16 -- 18 -- 16 -- 18 mA -60 -- 1920 -- 2160 -- 1920 -- 2160 mA RAS, WE, OE -16 +16 -18 +18 -16 +16 -18 +18 CAS -4 +4 -6 +6 -4 +4 -6 +6 Address -32 +32 -36 +36 -32 +32 -36 +36 1, 3 A IO(L) Output Leakage Current (DOUT is disabled, 0.0 VOUT VCC) -2 +2 -2 +2 -2 +2 -2 +2 A VOH Output Level (TTL) Output "H" Level Voltage ( IOUT = -2mA) 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V VOL Output Level (TTL) Output "L" Level Voltage ( IOUT = +2mA) 0.0 0.4 0.0 0.4 0.0 0.4 0.0 0.4 V 1. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 3. Address can be changed once or less while RAS =VIL. In the case of ICC4, it can be changed once or less when CAS =VIH. 75H1640 SA14-4626-01 Released 5/96 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE AC Characteristics (TA = 0 to +70C, VCC = 3.3V 0.3V) 1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 2. An initial pause of 200s is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh cycles is required.. 3. AC measurements assume tT = 2ns. . Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) -60 Symbol Parameter Unit Min Max Notes tRC Random Read or Write Cycle Time 104 -- ns tRP RAS Precharge Time 40 -- ns tCP CAS Precharge Time 10 -- ns tRAS RAS Pulse Width 60 100K ns tCAS CAS Pulse Width 10 100K ns tASR Row Address Setup Time 0 -- ns tRAH Row Address Hold Time 10 -- ns tASC Column Address Setup Time 0 -- ns tCAH Column Address Hold Time 10 -- ns tRCD RAS to CAS Delay Time 14 45 ns 1 tRAD RAS to Column Address Delay Time 12 30 ns 2 tRSH RAS Hold Time 10 -- ns tCSH CAS Hold Time 50 -- ns tCRP CAS to RAS Precharge Time 5 -- ns tODD OE to DIN Delay Time 15 -- ns 3 tDZO OE Delay Time from DIN 0 -- ns 4 tDZC CAS Delay Time from DIN 0 -- ns 4 Transition Time (Rise and Fall) 1 50 ns tT 1. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. The tRCD(max) is specified as a reference point only: If tRCD is greater than the specified tRCD(max) limit, then access time is controlled by tCAC. 2. Operation within the tRAD(max) limit ensures that tRAC(max) can be met. The tRAD(max) is specified as a reference point only: If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 3. Either tCDD or tODD must be satisfied. 4. Either tDZC or tDZO must be satisfied. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 30 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE Write Cycle -60 Symbol Parameter Min Max Unit Notes 1 tWCS Write Command Set Up Time 0 -- ns tWCH Write Command Hold Time 10 -- ns tWP Write Command Pulse Width 10 -- ns tRWL Write Command to RAS Lead Time 10 -- ns tCWL Write Command to CAS Lead Time 10 -- ns tDS DIN Setup Time 0 -- ns 2 tDH DIN Hold Time 10 -- ns 2 1. tWCS, tRWD, tCWD, and tAWD are not restrictive parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; If tRWD tRWD(min.), tCWD tCWD(min.) and tAWD tAWD(min.), the cycle is a Read-Modify-Write cycle and the data will contain read from the selected cell: If neither of the above sets of conditions are met, the condition of the data (at access time) is indeterminate. 2. Data-in set-up and hold is measured from the latter of the two timings, CAS or WE. 75H1640 SA14-4626-01 Released 5/96 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE Read Cycle -60 Symbol Parameter Min Max Unit Notes tRAC Access Time from RAS -- 60 ns 1, 2 tCAC Access Time from CAS -- 15 ns 1, 2 tAA Access Time from Address -- 30 ns 1, 2 tOEA Access Time from OE -- 15 ns 1, 2 tRCS Read Command Setup Time 0 -- ns tRCH Read Command Hold Time to CAS 0 -- ns 3 tRRH Read Command Hold Time to RAS 0 -- ns 3 tRAL Column Address to RAS Lead Time 30 -- ns tCLZ CAS to Output in Low-Z 0 -- ns tOES OE setup time prior to CAS 5 -- ns tORD OE setup time prior to RAS (Hidden Refresh) 0 -- ns tCDD CAS to DIN Delay Time 15 -- ns 5 tOEZ Output Buffer Turn-off Delay from OE -- 15 ns 4 tOFF Output Buffer Turn-off Delay -- 15 ns 4, 6 1. 2. 3. 4. Measured with the specified current load and 100pF. Access time is determined by the latter of tRAC, tCAC, tCPA, tAA, tOEA. Either tRCH or tRRH must be satisfied. tOFF (max) and tOEZ (max) define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 5. Either tCDD or tODD must be satisfied. 6. tOFF is referenced from the rising edge of RAS or CAS , whichever is last. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 30 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE Read-Modify-Write Cycle -60 Symbol Parameter Unit Min Max Notes tRWC Read-Modify-Write Cycle Time 135 -- ns tRWD RAS to WE Delay Time 79 -- ns 1 tCWD CAS to WE Delay Time 34 -- ns 1 tAWD Column Address to WE Delay Time 49 -- ns 1 tOEH OE Command Hold Time 10 -- ns 1. tWCS, tRWD, tCWD, and tAWD are not restrictive parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; If tRWD tRWD(min.), tCWD tCWD(min.) and tAWD tAWD(min.), the cycle is a Read-Modify-Write cycle and the data will contain read from the selected cell: If neither of the above sets of conditions are met, the condition of the data (at access time) is indeterminate. EDO Mode Cycle -60 Symbol Parameter Units Min. Max. tHCAS CAS Pulse Width (EDO Page Mode) 10 10K ns tHPC EDO Page Mode Cycle Time (Read/Write) 25 -- ns EDO Page Mode Read Modify Write Cycle Time 60 -- ns tDOH Data-out Hold Time from CAS 5 -- ns tWHZ Output buffer Turn-Off Delay from WE 0 10 ns tWPZ WE Pulse Width to Output Disable at CAS High 10 -- ns tCPRH RAS Hold Time from CAS Precharge 35 -- ns tCPA Access Time from CAS Precharge -- 35 ns tRASP EDO Page Mode RAS Pulse Width 60 200K ns tOEP OE High Pulse Width 10 -- ns tOEHC OE High Hold Time from CAS High 10 -- ns tHPRWC Notes 1 1. Measured with the specified current load and 100pF at VOL = 0.8V and VOH = 2.0V. 75H1640 SA14-4626-01 Released 5/96 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE Refresh Cycle -60 Symbol Parameter Unit Min Max Notes tCHR CAS Hold Time (CAS before RAS Refresh Cycle) 10 -- ns tCSR CAS Setup Time (CAS before RAS Refresh Cycle) 5 -- ns tWRP WE Setup Time (CAS before RAS Refresh Cycle) 10 -- ns tWRH WE Hold Time (CAS before RAS Refresh Cycle) 10 -- ns tRPC RAS Precharge to CAS Hold Time 5 -- ns -- 64 ms 1 tREF Refresh Period -- 128 ms 2 1. 12/12 addressing: 4096 refreshes are required every 64ms. 2. 13/11 addressing: 4096 refreshes for CBR and 8192 refreshes for RAS Only Refresh. Presence Detect Read and Write Cycle Symbol fSCL Parameter Min Max Unit SCL Clock Frequency 100 kHZ TI Noise Suppression Time Constant at SCL, SDA Inputs 100 ns tAA SCL Low to SDA Data Out Valid 0.3 3.5 s tBUF Time the Bus Must Be Free before a New Transmission Can Start 4.7 s Start Condition Hold Time 4.0 s tLOW Clock Low Period 4.7 s tHIGH Clock High Period 4.0 s tHD:STA tSU:STA Start Condition Setup Time(for a Repeated Start Condition) 4.7 s tHD:DAT Data in Hold Time 0 s tSU:DAT Data in Setup Time 250 ns tr SDA and SCL Rise Time 1 s tf SDA and SCL Fall Time 300 ns Stop Condition Setup Time 4.7 s tDH Data Out Hold Time 300 ns tWR Write Cycle Time tSU:STO Notes 15 ms 1 1. The write cycle time(tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 30 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE Read Cycle tRC tRAS tRP VIH RAS VIL tCSH tRCD CAS tRSH VIH tCRP tCAS VIL tRAD tRAL tASR tRAH tASC tCAH VIH Address VIL Row Column tWRP tWRH tRCH tRRH tRCS VIH NOTE 1 WE VIL tAA tOES OE VIH tOEA VIL tDZC tCDD tDZO tODD VIH DIN Hi-Z VIL tCAC tCLZ tOFF tOEZ VOH DOUT Hi-Z VOL Valid Data Out Hi-Z tRAC : "H": or "L" 75H1640 SA14-4626-01 Released 5/96 NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE Write Cycle (Early Write) tRC tRAS tRP VIH RAS VIL tCSH tRCD tRSH CAS VIH tCRP tCAS VIL tRAD tASR tASC tRAH tCAH VIH Address VIL Row tWRP tWRH Column tWCS VIH WE VIL tWCH tWP NOTE 1 VIH OE VIL tDS tDH VIH DIN Valid Data In VIL VOH DOUT Hi-Z VOL : "H" or "L" NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 30 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE Write Cycle (Late Write) tRC tRAS tRP VIH RAS VIL tCSH tRCD CAS tCRP tRSH VIH tCAS VIL tRAD tASR tASC tRAH tCAH VIH Address VIL Row tWRP Column tWRH tRCS tCWL VIH WE tWP NOTE 1 VIL tRWL VIH OE tOEH VIL tDH tODD tDZO VIH DIN tDS tWRP tDZC Valid Data In Hi-Z VIL tOEZ tCLZ tOEA VOH DOUT Hi-Z VOL : "H" or "L" Hi-Z* * tOEH greater than or equal to tCWL NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. 75H1640 SA14-4626-01 Released 5/96 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE Read-Modify-Write-Cycle tRWC tRAS tRP VIH RAS VIL tCSH tRCD CAS tCRP tRSH VIH tCAS tRAD VIL tASR tASC tRAH tCAH VIH Address Row Column VIL tCWD tRWL tAWD tWRP tWRH tCWL tRWD tWP VIH WE tAA NOTE 1 VIL tRCS tOEH VIH OE tOEA VIL tDZC tDH tDS tDZO VIH DIN Hi-Z tCAC VIL tCLZ DIN tODD tOEZ VOH DOUT Hi-Z VOL DOUT tRAC : "H" or "L" * * tOEH greater than or equal to tCWL NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 30 Hi-Z 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE EDO Page Mode Read Cycle tRP tRASP VIH RAS tCPRH VIL tCRP tHPC tRCD tCP tCP tHCAS tHCAS CAS VIH tRSH tHCAS VIL tCSH tASR Address tRAH tASC tRAL tCAH tASC tCAH tASC tCAH VIH VIL Row Column 1 Column 2 Column N tRAD tRCH tRRH tWRP tWRH tRCS VIH WE VIL NOTE 1 tCAC tCAC tCPA tOES tCPA tWP tOFF tAA tAA tOEA VIH OE VIL tOEZ tRAC tAA tDOH tCAC tDOH tCLZ DOUT VOH VOL Hi-Z : "H" or "L" 75H1640 SA14-4626-01 Released 5/96 Data Out 1 Data Out 2 Data Out N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE EDO Page Mode Read Cycle (OE Control) tRP tRASP VIH RAS tCPRH VIL tCRP tHPC tRCD tCP tHCAS tCP tHCAS CAS VIH tRSH tHCAS VIL tCSH tASR Address tRAH tRAL tASC tASC tCAH tCAH tASC tCAH VIH VIL Row Column 1 Column 2 Column N tRAD tWRP tWRH tRCH tRRH tRCS VIH WE VIL NOTE 1 tCAC tCAC tCPA tOES tOEA tOEHC tAA tOES tCPA tOFF tAA tOES tOEHC VIH tOEP OE VIL tRAC tOEP tOEA tOEA tAA tCAC tOEZ tOEZ tOEZ tCLZ VOH DOUT Hi-Z VOL : "H" or "L" Data Out 1 Data Out N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 30 Data Out 2 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE EDO Page Mode Read Cycle (WE Control) tRP tRASP VIH RAS tCPRH VIL tCRP tHPC tRCD tCP tCP tHCAS tRSH tHCAS tHCAS CAS VIH VIL tCSH tASR Address tRAH tRAL tASC tASC tCAH tCAH tCAH VIH VIL Row Column 1 Column 2 tRCH tWRP tWRH tRCS tRCH tRCS tRCH tRRH tCAC tOFF tRCS tWPZ VIH VIL Column N tAA tAA tRAD WE tASC tWPZ NOTE 1 tCAC tOES tCPA tCPA tOEA VIH OE VIL tOEZ tRAC tAA tCAC tWHZ tWHZ tCLZ VOH DOUT Hi-Z VOL : "H" or "L" 75H1640 SA14-4626-01 Released 5/96 Data Out 1 Data Out 2 Data Out N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE EDO Page Mode Early Write Cycle tRP tRASP VIH RAS VIL tCRP tHPC tRCD tCP tCP tHCAS CAS VIH tHCAS tRSH tHCAS VIL tRAD tCSH tASR Address tRAH tASC tCAH tRAL tASC tCAH tASC tCAH VIH Row VIL Column 1 Column 2 Column N tCWL tWRP tWRH VIH WE VIL tWCS tWCS tWP tWCH tWCS tWP tWCH tWP NOTE 1 tDS DIN tRWL tWCH tDH tDS tDH tDS tDH VIH Data In 1 VIL : "H" or "L" Data In 2 Data In N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. OE = Don't care (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 30 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE EDO Page Mode Late Write Cycle tRP tRASP VIH RAS VIL tHPC tRCD tCRP tCP tHCAS CAS VIH tCP tRSH tHCAS tHCAS VIL tRAD tCSH tASR Address tRAH tASC tCAH tASC tCAH tCAH VIH Row VIL Column 1 Column 2 tCWL tWRP tWRH VIL Column N tCWL tRCS tRCS tCWL tRCS tWP VIH WE tASC tRWL tWP tWP NOTE 1 tOEH tOEH tOEH VIH OE VIL tODD DIN tDS tDH tODD tDS tDH tODD tDS tDH VIH Hi-Z VIL : "H" or "L" 75H1640 SA14-4626-01 Released 5/96 Data In 1 Data In 2 Data In N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 21 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE EDO Page Mode Read Modify Write Cycle tRP tRASP VIH RAS VIL tHPRWC tCRP tCP tRCD CAS VIH tCP tCAS tCAS tCAS VIL tCSH tASC tASC tRAD tASR Address tRAH tRAL tASC tCAH tCAH tCAH VIH VIL Row Column 1 Column 2 Column N tCPA tCWL tCWL tCPA tAA tAA tRWL tRWD tWRP tAWD tWRH tRCS tCWD VIH WE VIL NOTE 1 tRCS tWP VIH tAWD tCWD tWP tCAC tOEH tOEA tODD tODD tOEZ tCLZ tOEH tOEH tOEA tOEA VIL tCLZ tODD tOEZ tCLZ tOEZ VOH Hi-Z VOL DOUT tDS DIN tWP tCAC tAA DOUT tRCS tCAC tRAC OE tAWD tCWD DOUT DOUT tDS tDH tDS tDH tDH VIH Hi-Z VIL : "H" or "L" DIN DIN NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 22 of 30 DIN 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE RAS Only Refresh Cycle tRC tRAS tRP VIH RAS VIL tRPC tCRP VIH CAS VIL tRAH tASR VIH Address Row VIL VOH Hi-Z DOUT VOL : "H" or "L" Note: WE, OE, DIN are "H" or "L" 75H1640 SA14-4626-01 Released 5/96 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 23 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE CAS Before RAS Refresh Cycle t RC tRAS tRP VIH RAS VIL t RPC tRPC tCSR tCSR tCP t CHR VIH CAS VIL tWRH tWRH tWRP tWRP VIH WE VIL VIH OE VIL tODD tCDD VOH DIN Hi-Z VOL tOEZ tOFF DOUT VOH Hi-Z VOL : "H" or "L" NOTE: Address is "H" or "L" (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 24 of 30 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE Hidden Refresh Cycle (Read) tRC tRC tRP tRP tRAS tRAS VIH RAS VIL tRCD tRSH tCRP tCHR VIH CAS VIL tRAL tRAD tASR tWRH tWRP tASC tRAH tCAH VIH Address Row Column VIL tRRH tRCS VIH WE tORD VIL tAA VIH tOEA OE VIL tDZC tDZO VIH DIN tCDD tODD Hi-Z VIL tCAC tCLZ tOEZ tOFF VOH DOUT Valid Data Out Hi-Z VOL Hi-Z tRAC : "H" or "L" 75H1640 SA14-4626-01 Released 5/96 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 25 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE Hidden Refresh Cycle (Write) tRC tRC tRP tRP tRAS tRAS VIH RAS VIL t RSH tRCD tCHR tCRP CAS VIH VIL tASR tASC tRAH tCAH VIH Address Row Column VIL t WRP tWCS VIH tWRH tWCH tWP WE VIL VIH OE VIL t DS tDH VIH DIN Valid Data VIL VOH DOUT Hi-Z VOL : "H" or "L" (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 26 of 30 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE Presence Detect (EEPROM) Bus Timing tF tLOW tR tHIGH SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Presence Detect Operation Clock and Data Conventions: Data states on the SDA line can change only during SCL low. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figure 1 & Figure 2). Start Condition: All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is high. The serial PD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. Figure 1. Data Window SCL SDA Data Stable Data Data Stable Stop Condition: All communications are termiChange nated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop con- Figure 2. Definition of Start & Stop dition is also used to place the serial PD device into standby power mode. SCL Acknowledge: Acknowledge is a software convenSDA tion used to indicate successful data transfers. The Stop transmitting device, either master or slave, will Start Bit Bit release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA Figure 3. Acknowledge Response From Receiver line LOW to acknowledge that it received the eight bits of data (Figure 3). The PD device will always respond with an acknowl- SCL from 8 9 edge after recognition of a start condition and its Master M slave address. If both the device and a write opera- Data Output tion have been selected, The PD device, will re- from Trans spond with an acknowledge after the receipt of each Output subsequent eight bit word. In the read mode the PD Data from Receiver device will transmit eight bits of data, release the Acknowledge SDA line and monitor the line for an acknowledge. If an acknowledge is detected and 75H1640 SA14-4626-01 Released 5/96 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 27 of 30 IBM11N16645B IBM11N16735B IBM11N16645C IBM11N16735C 16M x 64/72 DRAM MODULE Layout Drawing 133.35 5.25 131.35 5.171 127.35 5.014 (2X) 4.00 .157 Front 38.1 1.50 * 6.35 .250 3.0 .118 (2) 0 3.1877 .1255 42.18 1.661 17.78 .700 1.27 PITCH .050 1.00 WIDTH .039 66.68 2.63 SEE DETAIL A * On x72 only (CBx) Side 9.00 Detail A SCALE 4/1 .354 MAX. 2.0 .078 3.0 .118 7.289 .287 MIN. R 1.00 .0393 _ 0.10 1.27 + _ .004 .050 + Note: All dimensions are typical unless otherwise stated. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 28 of 30 Millimeters Inches 75H1640 SA14-4626-01 Released 5/96 IBM11N16735B IBM11N16645B IBM11N16735C IBM11N16645C 16M x 64/72 DRAM MODULE Revision Log Rev 3/96 5/96 75H1640 SA14-4626-01 Released 5/96 Contents of Modification Initial Release. Updated ICC currents: ICC3, ICC5 Updated Refresh period for CBR and RAS Only Refresh (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 29 of 30 International Business Machines Corp.1996 Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. 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