IBM11N16735BB-60 - IBM Microelectronics

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 1 of 30

Features

• 168 Pin JEDEC Standard, Unbuffered 8 Byte

Dual In-line Memory Module

• 16Mx64, 16Mx72 Extended Data Out Page

Mode DIMMS

• Performance:

• All inputs and outputs are LVTTL (3.3V) compat-

ible

• Single 3.3V ± 0.3V Power Supply

• Au contacts

• Optimized for byte-write non-parity, or ECC

applications

• System Performance Beneﬁts:

-Non buffered for increased performance

-Reduced noise (35 VSS/VCC pins)

-Byte write, byte read accesses

-Serial PDs

• Extended Data Out (EDO) Mode, Read-Modify-

Write Cycles

• Refresh Modes: RAS-Only, CBR and Hidden

Refresh

• CAS before RAS Refresh - 4096 cycles

• RAS only Refresh

- 4096 cycles (12/12 addressing)

- 8192 cycles (13/11 addressing)

• 12/12 or 13/11 addressing (Row/Column)

• Card size: 5.25" x 1.5" x 0.354"

• DRAMS in SOJ Package

Description

IBM11N16645B IBM11N16645C are industry stan-

dard 168-pin 8-byte Dual In-line Memory Modules

(DIMMs) which are organized as 16Mx64 and

16Mx72 high speed memory arrays designed with

EDO DRAMs for non-parity or ECC applications.

The DIMMs use 16 (x64) or 18 (x72) 16Mx4 EDO

DRAMs in SOJ packages. The use of EDO DRAMs

allows for a reduction in Page Mode Cycle time from

40ns (Fast Page) to 25ns for 60ns DRAM modules.

The DIMMs use serial presence detects imple-

mented via a serial EEPROM using the two pin I2C

protocol. This communication protocol uses Clock

(SCL) and Data I/O (SDA) lines to synchronously

clock data between the master (system logic) and

the slave EEPROM device (DIMM). The EEPROM

device address pins (SA0-2) are brought out to the

DIMM tabs to allow 8 unique DIMM/EEPROM

addresses. The first 128 bytes are utilized by the

DIMM manufacturer and the second 128 bytes of

serial PD data are available to the customer.

All IBM 168-pin DIMMs provide a high performance,

flexible 8-byte interface in a 5.25” long space-saving

footprint. Related products include the buffered

DIMMs (x64, x72 parity and x72 ECC Optmized) for

applications which can benefit from the on-card buff-

ers.

-60

tRAC RAS Access Time 60ns

tCAC CAS Access Time 15ns

tAA Access Time From Address 30ns

tRC Cycle Time 104ns

tHPC EDO Mode Cycle Time 25ns

Card Outline

85 10

94 11

95 40

124 41

125 84

168

(Front)

(Back)

IBM11M4730C4M x 72 E12/10, 5.0V, Au.

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 2 of 30

75H1640

SA14-4626-01

Released 5/96

Ordering Information

Pin Description

RAS0, RAS2 Row Address Strobe VCC Power (3.3V)

CAS0 - CAS7 Column Address Strobe VSS Ground

WE0, WE2 Read/write Input NC No Connect

OE0, OE2 Output Enable DU Don’t Use

A0 - A12 Address Inputs SCL Serial Presence Detect Clock Input

DQx Data Input/Output SDA Serial Presence Detect Data Input

CBx Check Bit Data Input/Output SA0-2 Serial Presence Detect Address Inputs

Pinout

Pin# Front

Side Pin# Back

Side Pin# Front

Side Pin# Back

Side Pin# Front

Side Pin# Back

Side Pin# Front

Side Pin# Back

Side

1VSS 85 VSS 22 CB1 106 CB5 43 VSS 127 VSS 64 VSS 148 VSS

2 DQ0 86 DQ32 23 VSS 107 VSS 44 OE2 128 DU 65 DQ21 149 DQ53

3 DQ1 87 DQ33 24 NC 108 NC 45 RAS2 129 NC 66 DQ22 150 DQ54

4 DQ2 88 DQ34 25 NC 109 NC 46 CAS2 130 CAS6 67 DQ23 151 DQ55

5 DQ3 89 DQ35 26 VCC 110 VCC 47 CAS3 131 CAS7 68 VSS 152 VSS

6VCC 90 VCC 27 WE0 111 DU 48 WE2 132 DU 69 DQ24 153 DQ56

7 DQ4 91 DQ36 28 CAS0 112 CAS4 49 VCC 133 VCC 70 DQ25 154 DQ57

8 DQ5 92 DQ37 29 CAS1 113 CAS5 50 NC 134 NC 71 DQ26 155 DQ58

9 DQ6 93 DQ38 30 RAS0 114 NC 51 NC 135 NC 72 DQ27 156 DQ59

10 DQ7 94 DQ39 31 OE0 115 DU 52 CB2 136 CB6 73 VCC 157 VCC

11 DQ8 95 DQ40 32 VSS 116 VSS 53 CB3 137 CB7 74 DQ28 158 DQ60

12 VSS 96 VSS 33 A0 117 A1 54 VSS 138 VSS 75 DQ29 159 DQ61

13 DQ9 97 DQ41 34 A2 118 A3 55 DQ16 139 DQ48 76 DQ30 160 DQ62

14 DQ10 98 DQ42 35 A4 119 A5 56 DQ17 140 DQ49 77 DQ31 161 DQ63

15 DQ11 99 DQ43 36 A6 120 A7 57 DQ18 141 DQ50 78 VSS 162 VSS

16 DQ12 100 DQ44 37 A8 121 A9 58 DQ19 142 DQ51 79 NC 163 NC

17 DQ13 101 DQ45 38 A10 122 A11 59 VCC 143 VCC 80 NC 164 NC

18 VCC 102 VCC 39 A12 123 NC 60 DQ20 144 DQ52 81 NC 165 SA0

19 DQ14 103 DQ46 40 VCC 124 VCC 61 NC 145 NC 82 SDA 166 SA1

20 DQ15 104 DQ47 41 VCC 125 DU 62 DU 146 DU 83 SCL 167 SA2

21 CB0 105 CB4 42 DU 126 DU 63 NC 147 NC 84 VCC 168 VCC

Note: All pin assignments are consistent for all 8 Byte unbuffered versions.

Part Number Organization Speed Addr. Leads Dimension Power

IBM11N16645BB-60 16Mx64 60ns 12/12 Au 5.25”x1.0”x 0.354” 3.3V

IBM11N16645CB-60 16Mx64 60ns Au 5.25”x1.0”x 0.354” 3.3V

IBM11N16735BB-60 16Mx72 60ns 13/11 Au 5.25”x1.0”x 0.354” 3.3V

IBM11N16735CB-60 16Mx72 60ns Au 5.25”x1.0”x 0.354” 3.3V

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 3 of 30

x64 DIMM Block Diagram (1 Bank, x4 DRAMs)

CAS2

CAS3

CAS1

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ28

DQ29

DQ30

DQ31

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

VCC

VSS

D0 - D15

A0-AN A0 - AN: DRAMS D0 - D15

CAS0

WE0 RAS0

OE0

DQ24

DQ25

DQ26

DQ27

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS6

CAS7

CAS5

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ60

DQ61

DQ62

DQ63

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS4

WE2 RAS2

OE2

D10

D11

D12

D13

D15

DQ56

DQ57

DQ58

DQ59

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

D14

SERIAL PD

A1 A2

SA0 SA1 SA2

SCL SDA

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 4 of 30

75H1640

SA14-4626-01

Released 5/96

x72 ECC DIMM Block Diagram (1 Bank, x4 DRAMs)

CAS2

CAS3

CAS1

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ28

DQ29

DQ30

DQ31

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

VCC

VSS

D0 - D17

A0-AN A0 - AN: DRAMS D0 - D17

CAS0

WE0 RAS0

OE0

DQ24

DQ25

DQ26

DQ27

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS6

CAS7

CAS5

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ60

DQ61

DQ62

DQ63

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

CAS4

WE2 RAS2

OE2

D10

D11

D12

D14

D15

D17

DQ56

DQ57

DQ58

DQ59

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

D16

CB0

CB1

CB2

CB3

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

D4 CB4

CB5

CB6

CB7

CAS RAS WE OE

I/O 0

I/O 1

I/O 2

I/O 3

D13

SERIAL PD

A1 A2

SA0 SA1 SA2

SCL SDA

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 5 of 30

Truth Table

Function RAS CAS WE OE Row

Address Column

Address DQx

Standby H H→XX X X X High Impedance

Read L L H L Row Col Valid Data Out

Early-Write L L L X Row Col Valid Data In

Late-Write L L H→LH Row Col Valid Data In

RMW L L H→LL→HRow Col Valid Data In/Out

EDO Page Mode - Read 1st Cycle L H→LH L Row Col Valid Data Out

Subsequent Cycles L H→LH L N/A Col Valid Data Out

EDO Page Mode - Write 1st Cycle L H→LL X Row Col Valid Data In

Subsequent Cycles L H→LL X N/A Col Valid Data In

EDO Page Mode - RMW 1st Cycle L H→LH→LL→HRow Col Valid Data In/Out

Subsequent Cycles L H→LH→LL→HN/A Col Valid Data In/Out

RAS-Only Refresh L H X X Row N/A High Impedance

CAS-Before-RAS Refresh H→LL H X X X High Impedance

Hidden Refresh Read L→H→LL H L Row Col Data Out

Write L→H→LL H X Row Col Data In

Self Refresh H→LL H X X X High Impedance

Serial Presence Detect

SPD Entry

Value

SPD Entry

Binary Hex

Byte # Description Bit 7 Bit 6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

0 Number of SPD Bytes 128 1 0 0 00000

1 Total # Bytes in Serial PD 256 0 0 0 01000

2 Memory Type EDO 0 0 0 00010

3 # of Row Addresses 12 00001100

13 00001101

4 # of Column Addresses 12 00001100

11 00001011

5 # of DIMM Banks 1 0 0 0 00001

6 Module Data Width x64 01000000

x72 01001000

7 Module Data Width (Cont.) 0 0 0 0 00000

8 Module Interface Levels LVTTL 0 0 0 00001

9 RAS Access 60ns 60 0 0 1 11100

10 CAS Access 15ns 15 0 0 0 01111

11 Dimm Config(Error Det/Corr.) x64 None 0 0 0 00000

x72ECC 00000010

12 Refresh Rate/Type Normal 15.6 µs00000000

13 Primary DRAM Organization x4 0 0 0 00100

14 Secondary DRAM Organization undefined 0 0 0 00000

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 6 of 30

75H1640

SA14-4626-01

Released 5/96

Absolute Maximum Ratings

Symbol Parameter Rating (3.3V) Units Notes

VCC Power Supply Voltage -0.5 to +4.6 V 1

VIN Input Voltage -0.5 to min (VCC + 0.5, 4.6) V1

IN/OUT (SPD) Input Voltage (Serial PD Device) -0.3 to +6.5 V 1

VOUT Output Voltage -0.5 to min (VCC + 0.5, 4.6) V1

OPR Operating Temperature 0 to +70 °C1

TSTG Storage Temperature -55 to +125 °C1

PDPower Dissipation

12/12 Addressing 13/11 Addressing

x64 7.5 6.9

x72 8.5 7.8

IOUT Short Circuit Output Current 50 mA 1

1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and functional opera-

tion of the device at these or any other conditions above those indicated is not implied. Exposure to absolute maximum rating con-

dition for extended periods may affect reliability.

Recommended DC Operating Conditions (TA = 0 to 70°C)

Symbol Parameter 3.3V Units Notes

Min Typ Max

VCC Supply Voltage 3.0 3.3 3.6 V 1

VIH Input High Voltage 2.0 — VCC + 0.3 V1, 2

VIL Input Low Voltage -0.3 — 0.8 V 1, 2

1. All voltages referenced to VSS.

2. VIH may overshoot to VCC + 1.2V for pulse widths of ≤4.0ns (or VCC + 1.0V for ≤8.0ns). Additionally, VIL may undershoot to -2.0V

for pulse widths ≤ 4.0ns (or -1.0V for ≤ 8.0ns). Pulse widths measured at 50% points with amplitude measured peak to DC refer-

ence.

Capacitance (TA = 0 to +70°C, VCC = 3.3V ± 0.3V)

Max

Symbol Parameter x64 x72 Units

CI1 Input Capacitance (A0-A11) 90 100 pF

CI2 Input Capacitance (RAS, WE, OE) 70 75 pF

CI3 Input Capacitance (CAS) 20 25 pF

CI4 Input Capacitance (SCL, SA0-3) 8 8 pF

CIO1 Input/Output Capacitance (DQX,CBX)1111pF

CIO2 Input/Output Capacitance (SDA) 10 10 pF

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 7 of 30

DC Electrical Characteristics (TA= 0 to +70˚C, VCC= 3.3V ±0.3V)

Symbol Parameter

12/12 Addressing 13/11 Addressing

Units Notes

x64 x72 x64 x72

Min. Max. Min. Max. Min. Max. Min. Max.

ICC1

Operating Current

Average Power Supply Operating Current

(RAS, CAS, Address Cycling: tRC = tRC min.) -60 — 2080 — 2349 — 1680 — 1890 mA 1, 2, 3

ICC2

Standby Current (TTL)

Power Supply Standby Current

(RAS = CAS = VIH)— 32 — 36 — 32 — 36 mA

ICC3

RAS Only Refresh Current

Average Power Supply Current, RAS Only Mode

(RAS Cycling, CAS = VIH: tRC = tRC min) -60 — 1760 — 1980 — 1360 —1530 mA 1, 3

ICC4

EDO Page Mode Current

Average Power Supply Current, EDO Page

Mode

(RAS = VIL, CAS, Address Cycling: tHPC = tHPC

min)

-60 — 1040 — 1170 — 1280 — 1440 mA 1, 2, 3

ICC5

Standby Current (CMOS)

Power Supply Standby Current

(RAS = CAS = VCC - 0.2V) —16 —18 —16 —18 mA

ICC6

CAS Before RAS Refresh Current

Average Power Supply Current, CAS Before

RAS Mode

(RAS, CAS, Cycling: tRC = tRC min)

-60 — 1920 — 2160 — 1920 — 2160 mA 1, 3

II(L)

Input Leakage Current

Input Leakage Current, any input

(0.0 ≤ VIN ≤ (VCC + 0.3V)), All Other Pins Not

Under Test = 0V

RAS,

WE, OE -16 +16 -18 +18 -16 +16 -18 +18

µA

CAS -4 +4 -6 +6 -4 +4 -6 +6

Address -32 +32 -36 +36 -32 +32 -36 +36

IO(L) Output Leakage Current

(DOUT is disabled, 0.0 ≤ VOUT ≤ VCC)-2 +2 -2 +2 -2 +2 -2 +2 µA

VOH

Output Level (TTL)

Output “H” Level Voltage

( IOUT = -2mA) 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V

VOL

Output Level (TTL)

Output “L” Level Voltage

( IOUT = +2mA) 0.0 0.4 0.0 0.4 0.0 0.4 0.0 0.4 V

1. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.

2. ICC1 and ICC4 depend on output loading. Speciﬁed values are obtained with the output open.

3. Address can be changed once or less while RAS =VIL. In the case of ICC4, it can be changed once or less when CAS =VIH.

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 8 of 30

75H1640

SA14-4626-01

Released 5/96

AC Characteristics (TA = 0 to +70°C, VCC =3.3V ±0.3V)

1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and

VIL.

2. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is

achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh

cycles is required..

3. AC measurements assume tT = 2ns.

Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)

Symbol Parameter -60 Unit Notes

Min Max

tRC Random Read or Write Cycle Time 104 — ns

tRP RAS Precharge Time 40 — ns

tCP CAS Precharge Time 10 — ns

tRAS RAS Pulse Width 60 100K ns

tCAS CAS Pulse Width 10 100K ns

tASR Row Address Setup Time 0 — ns

tRAH Row Address Hold Time 10 — ns

tASC Column Address Setup Time 0 — ns

tCAH Column Address Hold Time 10 — ns

tRCD RAS to CAS Delay Time 14 45 ns 1

tRAD RAS to Column Address Delay Time 12 30 ns 2

tRSH RAS Hold Time 10 — ns

tCSH CAS Hold Time 50 — ns

tCRP CAS to RAS Precharge Time 5 — ns

tODD OE to DIN Delay Time 15 — ns 3

tDZO OE Delay Time from DIN 0—ns 4

DZC CAS Delay Time from DIN 0 — ns 4

tTTransition Time (Rise and Fall) 1 50 ns

1. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. The tRCD(max) is specified as a reference point only: If tRCD

is greater than the specified tRCD(max) limit, then access time is controlled by tCAC.

2. Operation within the tRAD(max) limit ensures that tRAC(max) can be met. The tRAD(max) is speciﬁed as a reference point only: If tRAD

is greater than the speciﬁed tRAD(max) limit, then access time is controlled by tAA.

3. Either tCDD or tODD must be satisﬁed.

4. Either tDZC or tDZO must be satisﬁed.

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 9 of 30

Write Cycle

Symbol Parameter -60 Unit Notes

Min Max

tWCS Write Command Set Up Time 0 — ns 1

tWCH Write Command Hold Time 10 — ns

tWP Write Command Pulse Width 10 — ns

tRWL Write Command to RAS Lead Time 10 — ns

tCWL Write Command to CAS Lead Time 10 — ns

tDS DIN Setup Time 0 — ns 2

tDH DIN Hold Time 10 — ns 2

1. tWCS, tRWD, tCWD, and tAWD are not restrictive parameters. They are included in the data sheet as electrical characteristics only. If

tWCS ≥tWCS(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the

entire cycle; If tRWD ≥tRWD(min.), tCWD ≥tCWD(min.) and tAWD ≥tAWD(min.), the cycle is a Read-Modify-Write cycle and the data will

contain read from the selected cell: If neither of the above sets of conditions are met, the condition of the data (at access time) is

indeterminate.

2. Data-in set-up and hold is measured from the latter of the two timings, CAS or WE.

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 10 of 30

75H1640

SA14-4626-01

Released 5/96

Read Cycle

Symbol Parameter -60 Unit Notes

Min Max

tRAC Access Time from RAS — 60 ns 1, 2

tCAC Access Time from CAS — 15 ns 1, 2

tAA Access Time from Address — 30 ns 1, 2

tOEA Access Time from OE — 15 ns 1, 2

tRCS Read Command Setup Time 0 — ns

tRCH Read Command Hold Time to CAS 0 — ns 3

tRRH Read Command Hold Time to RAS 0 — ns 3

tRAL Column Address to RAS Lead Time 30 — ns

tCLZ CAS to Output in Low-Z 0 — ns

tOES OE setup time prior to CAS 5 — ns

tORD OE setup time prior to RAS (Hidden Refresh) 0 — ns

tCDD CAS to DIN Delay Time 15 — ns 5

tOEZ Output Buffer Turn-off Delay from OE — 15 ns 4

tOFF Output Buffer Turn-off Delay — 15 ns 4, 6

1. Measured with the speciﬁed current load and 100pF.

2. Access time is determined by the latter of tRAC, tCAC, tCPA, tAA, tOEA.

3. Either tRCH or tRRH must be satisﬁed.

4. tOFF (max) and tOEZ (max) deﬁne the time at which the output achieves the open circuit condition and is not referenced to output

voltage levels.

5. Either tCDD or tODD must be satisﬁed.

6. tOFF is referenced from the rising edge of RAS or CAS , whichever is last.

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 11 of 30

Read-Modify-Write Cycle

Symbol Parameter -60 Unit Notes

Min Max

tRWC Read-Modify-Write Cycle Time 135 — ns

tRWD RAS to WE Delay Time 79 — ns 1

tCWD CAS to WE Delay Time 34 — ns 1

tAWD Column Address to WE Delay Time 49 — ns 1

tOEH OE Command Hold Time 10 — ns

1. tWCS, tRWD, tCWD, and tAWD are not restrictive parameters. They are included in the data sheet as electrical characteristics only. If

tWCS ≥tWCS(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the

entire cycle; If tRWD ≥tRWD(min.), tCWD ≥tCWD(min.) and tAWD ≥tAWD(min.), the cycle is a Read-Modify-Write cycle and the data will

contain read from the selected cell: If neither of the above sets of conditions are met, the condition of the data (at access time) is

indeterminate.

EDO Mode Cycle

Symbol Parameter -60 Units Notes

Min. Max.

tHCAS CAS Pulse Width (EDO Page Mode) 10 10K ns

tHPC EDO Page Mode Cycle Time (Read/Write) 25 — ns

tHPRWC EDO Page Mode Read Modify Write Cycle Time 60 — ns

tDOH Data-out Hold Time from CAS 5 — ns

tWHZ Output buffer Turn-Off Delay from WE 0 10 ns

tWPZ WE Pulse Width to Output Disable at CAS High 10 — ns

tCPRH RAS Hold Time from CAS Precharge 35 — ns

tCPA Access Time from CAS Precharge — 35 ns 1

tRASP EDO Page Mode RAS Pulse Width 60 200K ns

tOEP OE High Pulse Width 10 — ns

tOEHC OE High Hold Time from CAS High 10 — ns

1. Measured with the specified current load and 100pF at VOL = 0.8V and VOH = 2.0V.

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 12 of 30

75H1640

SA14-4626-01

Released 5/96

Refresh Cycle

Symbol Parameter -60 Unit Notes

Min Max

tCHR CAS Hold Time

(CAS before RAS Refresh Cycle) 10 — ns

tCSR CAS Setup Time

(CAS before RAS Refresh Cycle) 5—ns

WRP WE Setup Time

(CAS before RAS Refresh Cycle) 10 — ns

tWRH WE Hold Time

(CAS before RAS Refresh Cycle) 10 — ns

tRPC RAS Precharge to CAS Hold Time 5 — ns

tREF Refresh Period —64ms 1

— 128 ms 2

1. 12/12 addressing: 4096 refreshes are required every 64ms.

2. 13/11 addressing: 4096 refreshes for CBR and 8192 refreshes for RAS Only Refresh.

Presence Detect Read and Write Cycle

Symbol Parameter Min Max Unit Notes

fSCL SCL Clock Frequency 100 kHZ

TINoise Suppression Time Constant at SCL, SDA Inputs 100 ns

tAA SCL Low to SDA Data Out Valid 0.3 3.5 µs

tBUF Time the Bus Must Be Free before a New Transmission Can Start 4.7 µs

tHD:STA Start Condition Hold Time 4.0 µs

tLOW Clock Low Period 4.7 µs

tHIGH Clock High Period 4.0 µs

tSU:STA Start Condition Setup Time(for a Repeated Start Condition) 4.7 µs

tHD:DAT Data in Hold Time 0 µs

tSU:DAT Data in Setup Time 250 ns

trSDA and SCL Rise Time 1 µs

tfSDA and SCL Fall Time 300 ns

tSU:STO Stop Condition Setup Time 4.7 µs

tDH Data Out Hold Time 300 ns

tWR Write Cycle Time 15 ms 1

1. The write cycle time(tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.

During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and

the device does not respond to its slave address.

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 13 of 30

Read Cycle

RAS VIH

VIL

VIH

VIL

Address VIH

VIL

WE VIH

VIL

OE VIH

VIL

VIH

VIL

DOUT

VOH

VOL

DIN

Row Column

Valid Data Out

tRAS tRP

tRC

tCAS

tCSH tCRP

tRAH tASC tCAH

tASR

tRAD

tRCS

tDZC

tCLZ

tCAC

tRAC

Hi-Z Hi-Z

tRRH

: “H”: or “L”

tRCD

tOEZ

Hi-Z

tRSH

tRAL

tDZO

tAA

tOEA

CAS

tODD

tCDD

tRCH

tOFF

tWRP tWRH

NOTE 1

NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.

Doing so will facilitate compatibility with future EDO DRAMs.

tOES

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 14 of 30

75H1640

SA14-4626-01

Released 5/96

Write Cycle (Early Write)

tRC

RAS VIH

VIL

VIH

VIL

Address VIH

VIL

WE VIH

VIL

OE VIH

VIL

VIH

VIL

DOUT

VOH

VOL

DIN

Row Column

tRAS tRP

tRCD

tCSH tCRP

tRAH

tASC

tCAH

tASR

tRAD

tWCS

Hi-Z

: “H” or “L”

Valid Data In

tWCH

tDS tDH

tCAS

tRSH

tWP

CAS

tWRP tWRH

NOTE 1

NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.

Doing so will facilitate compatibility with future EDO DRAMs.

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 15 of 30

Write Cycle (Late Write)

RAS VIH

VIL

VIH

VIL

Address VIH

VIL

WE VIH

VIL

OE VIH

VIL

VIH

VIL

DOUT

VOH

VOL

DIN

Row Column

tRAS tRP

tRC

tCAS

tCSH tCRP

tRAH

tASC

tCAH

tASR

tRAD

tRWL

: “H” or “L”

tWP

tCWL

Valid Data In

Hi-Z

tDZO

tOEZ

tCLZ

tDS

tRCD

tDH

tRCS

*tOEH greater than or equal to tCWL

Hi-Z

tRSH

tDZC

tOEA

tOEH

tODD

CAS

tWRP

NOTE 1

tWRP

tWRH

NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.

Doing so will facilitate compatibility with future EDO DRAMs.

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 16 of 30

75H1640

SA14-4626-01

Released 5/96

Read-Modify-Write-Cycle

DIN

tOEH

VOL

VOH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

tRCD

tRWC

tRAS

tCSH

tCAS

tRP

tRAH

tASC

tASR

tCAH

tCWD

tRCS

tOEA

tRWL

tCWL

tWP

tDH

tDS

tDZC

tCAC

tCLZ tODD tOEZ

tRAC

RAS

Address

DIN

DOUT

Hi-Z

Hi-Z DOUT

Row Column

: “H” or “L”

tOEH greater than or equal to tCWL

Hi-Z

tCRP

tAWD

tAA

tRWD

tRSH

tRAD

tDZO

CAS

tWRP

NOTE 1

tWRH

NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.

Doing so will facilitate compatibility with future EDO DRAMs.

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 17 of 30

EDO Page Mode Read Cycle

tRP

tHCAS

Data Out 1 Data Out 2

RAS

Row

Address Column 1 Column 2 Column N

tOEA

tDOH tDOH

tOEZ

tCLZ

tCAC

VIH

VIL

tASR tRAH tASC tASC tCAH

tCAH

DOUT

tRASP

tCPRH

tCRP

tRSH

tHCAS

tHPC

tASC

tCSH

tRAD

tRCS

tCAC tCPA

tCPA

tAA

tRAC

tAA

Hi-Z

: “H” or “L”

tRAL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

tRCD tCP tCP

tRRH

tRCH

tWP

tCAC

Data Out N

tOFF

CAS

tWRP

NOTE 1

tWRH

NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.

Doing so will facilitate compatibility with future EDO DRAMs.

tOES

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 18 of 30

75H1640

SA14-4626-01

Released 5/96

EDO Page Mode Read Cycle (OE Control)

tRP

Data Out 1 Data Out 2

RAS

Row

Address Column 1 Column 2 Column N

tOEA

tOEZ

tCLZ

tCAC

VIH

VIL

tASR tRAH tASC tASC tCAH

tCAH

DOUT

tRASP

tCPRH

tCRP

tRSH

tHCAS

tHPC

tASC

tCSH

tRAD

tRCS

tCAC tCPA

tCPA

tAA

tRAC

tAA

Hi-Z

: “H” or “L”

tRAL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

tRCD tCP tCP

tRRH

tRCH

tCAC

Data Out N

tOFF

tOEA

tOEZ tOEZ

tOEA

CAS

tWRP

NOTE 1

tWRH

NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.

Doing so will facilitate compatibility with future EDO DRAMs.

tOES

tHCAS

tOES

tOEHC

tOEP

tOEHC

tOEP

tOES

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 19 of 30

EDO Page Mode Read Cycle (WE Control)

tRP

Data Out 1 Data Out 2

RAS

Row

Address Column 1 Column 2 Column N

tOEA

tOEZ

tCLZ

tCAC

VIH

VIL

tASR tRAH tASC tASC tCAH

tCAH

DOUT

tRASP

tCPRH

tCRP

tRSH

tHCAS

tHPC

tASC

tCSH

tRAD

tRCS

tCAC tCPA

tCPA

tAA

tRAC

tAA

Hi-Z

: “H” or “L”

tRAL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

tRCD tCP tCP

tRRH

tRCH

tCAC

Data Out N

tOFF

CAS

tWRP

NOTE 1

tWRH

NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.

Doing so will facilitate compatibility with future EDO DRAMs.

tOES

tHCAS

tWPZ tWPZ

tRCH tRCS tRCS

tRCH

tWHZ tWHZ

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 20 of 30

75H1640

SA14-4626-01

Released 5/96

EDO Page Mode Early Write Cycle

tHCAS

tRP

RAS

Row

Address

Column 1 Column 2 Column N

Data In 1 Data In 2 Data In N

tASR tRAH tCAH

tWCH

tDH

DIN

tRASP

tRSH

tHCAS

tHPC

tRAD

tASC tASC

tCSH

tCAH tASC tCAH

tWCH

tWCS

tWCH

tWCS

tDS tDS tDH tDH

tDS

: “H” or “L”

tCWL

tRWL

tWP

OE = Don’t care

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tRCD tCP tCP

tCRP

CAS

tWRP

NOTE 1

tWRH

NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.

Doing so will facilitate compatibility with future EDO DRAMs.

tRAL

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 21 of 30

EDO Page Mode Late Write Cycle

tHCAS

tRP

RAS

Row

Address

Column 1 Column 2 Column N

Data In 1 Data In 2 Data In N

tASR tRAH tASC tASC tASC tCAH

tCAH

tCWL

tWP

tCWL

tWP

tCWL

tWP

tOEH

tDS tDH tODD tDS tDH tODD tDS tDH

DIN

: “H” or “L”

tRASP

tRSH

tHCAS

tHPC

tCSH

tODD

Hi-Z

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tRCD tCP tCP

tCRP

tRAD

tRCS tRCS tRCS tRWL

CAS

tWRP

NOTE 1

tWRH

NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.

Doing so will facilitate compatibility with future EDO DRAMs.

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 22 of 30

75H1640

SA14-4626-01

Released 5/96

EDO Page Mode Read Modify Write Cycle

Address

RAS

DOUT

DIN

tRP

tCP tCP

tASR

tRAD

tRAH tCAH

tASC

tASC tCAH

tASC

tCAH

tWP

tCWL

tWP

tRCS tRCS

tWP

tCWL

tRWL

tCAC

tOEH tOEH tOEH

DOUT

tCLZ tCLZ

tODD

tDH tDH

tCLZ

tODD

tDH

DIN

DOUT

: “H” or “L”

Hi-Z

tRASP

tCAS

tHPRWC

tCAS

tRAL

tAWD

tCWD

tAA

tCPA

tAA

tAWD

tCWD

tRWD

tAWD

tCWD

tRCS

tRAC

tAA

tOEA tOEA

tCAC tCAC

tOEA

tOEZ

tDS tDS tDS

Column 1

Row Column 2 Column N

tCSH

tOEZ

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

tRCD

tCAS

tCRP

tCPA

CAS

tWRP

NOTE 1

tWRH

NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.

Doing so will facilitate compatibility with future EDO DRAMs.

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 23 of 30

RAS Only Refresh Cycle

RAS

VIH

VIL

VIH

VIL

Address

VIH

VIL

DOUT

VOH

VOL

Row

tRAS tRP

tRC

tRAH

tASR

Hi-Z

: “H” or “L”

Note: WE, OE, DIN are “H” or “L”

tRPC tCRP

CAS

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 24 of 30

75H1640

SA14-4626-01

Released 5/96

CAS Before RAS Refresh Cycle

RAS VIH

VIL

VIH

VIL

WE VIH

VIL

DIN VOH

VOL

tRAS tRP

OE VIH

VIL

DOUT VOH

VOL Hi-Z

: “H” or “L”

tOFF

tOEZ

Hi-Z

tODD

tCHR

tWRH

tWRP

NOTE: Address is “H” or “L”

RPC

tCP

tCDD

tRPC

tCSR

tWRH

tWRP

tCSR

CAS

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 25 of 30

Hidden Refresh Cycle (Read)

RAS VIH

VIL

VIH

VIL

Address VIH

VIL

WE VIH

VIL

OE VIH

VIL

VIH

VIL

DOUT

VOH

VOL

DIN

Row Column

Valid Data Out

tRAS

tRP

tRC

tCRP

tRAH

tASC tCAH

tASR

tRAD

tRCS

tDZC

tODD

tOEZ

tCDD

tCLZ

tCAC

tRAC

Hi-Z

: “H” or “L”

tRP

tCHR

RSH

RCD

tRRH

tWRP

tWRH

tRC

tDZO

tRAL

tOFF

CAS

tOEA

tORD

tAA

Hi-Z

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 26 of 30

75H1640

SA14-4626-01

Released 5/96

Hidden Refresh Cycle (Write)

RAS VIH

VIL

VIH

VIL

Address VIH

VIL

WE VIH

VIL

OE VIH

VIL

VIH

VIL

DOUT

VOH

VOL

DIN

Row Column

Valid Data

tRAS

tRP

tRC

tCRP

tRAH

tASC tCAH

tASR

Hi-Z

: “H” or “L”

tRP

tCHR

RSH

tDS tDH

tWCH

WCS

ttWRP tWRH

tRC

tWP

tRCD

CAS

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 27 of 30

Presence Detect (EEPROM) Bus Timing

SCL

SDA IN

tSU:STO

tHD:STA

tSU:STA

tAA

SDA OUT

tFtLOW tHIGH tR

tSU:DAT

tHD:DAT

tBUF

tDH

Presence Detect Operation

Clock and Data Conventions: Data states on the

SDA line can change only during SCL low. SDA

state changes during SCL HIGH are reserved for

indicating start and stop conditions (Figure 1 & Fig-

ure 2).

Start Condition: All commands are preceded by

the start condition, which is a HIGH to LOW transi-

tion of SDA when SCL is high. The serial PD device

continuously monitors the SDA and SCL lines for

the start condition and will not respond to any com-

mand until this condition has been met.

Stop Condition: All communications are termi-

nated by a stop condition, which is a LOW to HIGH

transition of SDA when SCL is HIGH. The stop con-

dition is also used to place the serial PD device into

standby power mode.

Acknowledge: Acknowledge is a software conven-

tion used to indicate successful data transfers. The

transmitting device, either master or slave, will

release the bus after transmitting eight bits. During

the ninth clock cycle the receiver will pull the SDA

line LOW to acknowledge that it received the eight

bits of data (Figure 3).

The PD device will always respond with an acknowl-

edge after recognition of a start condition and its

slave address. If both the device and a write opera-

tion have been selected, The PD device, will re-

spond with an acknowledge after the receipt of each

subsequent eight bit word. In the read mode the PD

device will transmit eight bits of data, release the

SDA line and monitor the line for an

acknowledge. If an acknowledge is detected and

no stop condition is generated by the master, the

slave will continue to transmit data. If an acknowledge

is not detected, the slave will terminate further data

transmissions and await the stop condition to return to

standby power mode.

Figure 1. Data Window

Figure 2. Deﬁnition of Start & Stop

Figure 3. Acknowledge Response From Receiver

SCL

SDA Data

Data Stable Data Stable

Change

SCL

SDA

Start Stop

Bit Bit

Acknowledge

SCL from

Data Output

from Trans

Data Output

from Receiver

MasterM

IBM11N16645B IBM11N16735B

IBM11N16645C IBM11N16735C

16M x 64/72 DRAM MODULE

Use is further subject to the provisions at the end of this document.

Page 28 of 30

75H1640

SA14-4626-01

Released 5/96

Layout Drawing

* On x72 only (CBx)

6.35

.250

R 1.00

.0393

1.27 PITCH

.050

1.00 WIDTH

.039

Note: All dimensions are typical unless otherwise stated.

9.00

.354 MAX.

Side

1.27 0.10

.050 .004

2.0

.078

3.0

.118

SEE DETAIL A

Detail A

SCALE 4/1

1.50

38.1

(2) 0

3.1877

.1255

133.35

5.25

131.35

5.171

127.35

5.014

.118

3.0 (2X) 4.00

.157

.700

17.78

Front

7.289

.287 MIN.

Millimeters

Inches

66.68

2.63

42.18

1.661

IBM11N16735B IBM11N16645B

IBM11N16735C IBM11N16645C

16M x 64/72 DRAM MODULE

75H1640

SA14-4626-01

Released 5/96

Use is further subject to the provisions at the end of this document.

Page 29 of 30

Revision Log

Rev Contents of Modiﬁcation

3/96 Initial Release.

5/96 Updated ICC currents: ICC3, ICC5

Updated Refresh period for CBR and RAS Only Refresh

International Business Machines Corp.1996

Printed in the United States of America

IBM and the IBM logo are registered trademarks of the IBM Corporation.

This document may contain preliminary information and is subject to change by IBM without notice . IBM assumes no responsibility or

liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or

indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for

use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons.

NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY

OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.

For more information contact your IBM Microelectronics sales representative or

visit us on World Wide Web at http://www.chips.ibm.com

IBM Microelectronics manufacturing is ISO 9000 compliant.

SA14-4626-01

