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About Cypress
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automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
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MB9B160R Series
32-bit ARM® Cortex®-M4F
FM4 Microcontroller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-04918 Rev.*D Revised September 25, 2017
The MB9B160R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance
and competitive cost.
These series are based on the ARM® Cortex®-M4F Processor with on-chip Flash memory and SRAM, and has peripheral functions
such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I2C, LIN).
Features
32-bit ARM® Cortex®-M4F Core
Processor version: r0p1
Up to 160 MHz Frequency Operation
FPU built-in
Support DSP instruction
Memory Protection Unit (MPU): improves the reliability of an
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
[Flash memory]
These series are based on two independent on-chip Flash
memories.
MainFlash memory
Up to 1024 Kbytes
Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
The read access to Flash memory can be achieved without
wait-cycle up to operation frequency of 72 MHz. Even at
the operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash
Accelerator System.
Security function for code protection
WorkFlash memory
32 Kbytes
Read cycle:
• 6 wait-cycle: the operation frequency more than 120 MHz,
and up to 160 MHz
• 4 wait-cycle: the operation frequency more than 72 MHz,
and up to 120 MHz
• 2 wait-cycle: the operation frequency more than 40 MHz,
and up to 72 MHz
• 0 wait-cycle: the operation frequency up to 40 MHz
Security function is shared with code protection
[SRAM]
This is composed of three independent SRAMs (SRAM0,
SRAM1 and SRAM2). SRAM0 is connected to I-code bus or
D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to System bus of Cortex-M4F core.
SRAM0: Up to 64 Kbytes
SRAM1: Up to 32 Kbytes
SRAM2: Up to 32 Kbytes
External Bus Interface
Supports SRAM, NOR, NAND Flash and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-bit Data width
Up to 25-bit Address bit
Maximum Access size: 256M byte
Supports Address/Data multiplex
Supports external RDY function
Supports scramble function
Possible to set the validity/invalidity of the scramble function
for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4
Mbytes units.
Possible to set two kinds of the scramble key
Note: It is necessary to prepare the dedicated software
library to use the scramble function.
Multi-function Serial Interface (Max 8 channels)
64 bytes with FIFO (the FIFO step numbers are variable
depending on the settings of the communication mode or bit
length.)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
I2C
Document Number: 002-04918 Rev.*D Page 2 of 160
MB9B160R Series
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)
Various error detect functions available (parity errors, framing
errors, and overrun errors)
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
Serial chip select function (ch.6 and ch.7 only)
Supports high-speed SPI (ch.4 and ch.6 only)
Data length 5 to 16-bit
[LIN]
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generation (can change to 13 to 16-bit length)
LIN break delimiter generation (can change to 1 to 4-bit
length)
Various error detect functions available (parity errors, framing
errors, and overrun errors)
[I2C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
Fast-mode Plus (Fm+) (Max 1000 kbps, only for ch.3 = ch.A
and ch.7 = ch.B) supported
DMA Controller (8 channels)
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: bytes/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
DSTC (Descriptor System data Transfer Controller)
(128 channels)
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the Descriptor system and,
following the specified contents of the Descriptor which has
already been constructed on the memory, can access directly
the memory /peripheral device and performs the data transfer
operation.
It supports the software activation, the hardware activation and
the chain activation functions.
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 3 units
Conversion time: 0.5 μs @ 5 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4 steps)
DA converter (Max 2 channels)
R-2R type
12-bit resolution
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General Purpose I/O Port
This series can use its pins as general purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set which I/O port the
peripheral function can be allocated.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 100 high-speed general-purpose I/O ports @ 120 pin
Package
Some pin is 5V tolerant I/O.
See “Pin Description” and “I/O Circuit Type” for the
corresponding pins.
Document Number: 002-04918 Rev.*D Page 3 of 160
MB9B160R Series
Multi-function Timer (Max 2 units)
The Multi-function timer is composed of the following blocks.
Minimum resolution: 6.25 ns
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Output compare × 6 ch./unit
A/D activation compare × 6 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
The following function can be used to achieve the motor
control.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Quadrature Position/Revolution Counter (QPRC)
(Max 2 channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Free-running
Periodic ( = Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from the low-power
consumption mode. It is possible to select the main clock, sub
clock, built-in high-speed CR clock or built-in low-speed CR
clock as the clock source.
Interval timer: up to 64s (Max) @ Sub Clock: 32.768 kHz
External Interrupt Controller Unit
External interrupt input pin: Max 16 pins
Include one non-maskable interrupt (NMI)
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, "Hardware" watchdog is active in any
power saving mode except STOP.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
SD Card Interface
It is possible to use the SD card that conforms to the following
standards.
Part 1 Physical Layer Specification version 3.01
Part E1 SDIO Specification version 3.00
Part A2 SD Host Controller Standard Specification version
3.00
1-bit or 4-bit data bus
Document Number: 002-04918 Rev.*D Page 4 of 160
MB9B160R Series
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
Main clock: 4 MHz to 48 MHz
Sub Clock: 32.768 kHz
High-speed internal CR Clock: 4 MHz
Low-speed internal CR Clock: 100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low voltage detector reset
Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-power Consumption Mode
Six low-power consumption modes are supported.
SLEEP
TIMER
RTC
STOP
Deep standby RTC (selectable from with/without RAM
retention)
Deep standby stop (selectable from with/without RAM
retention)
VBAT
The consumption power during the RTC operation can be
reduced by supplying the power supply independent from the
RTC (calendar circuit)/32 kHz oscillation circuit. The following
circuits can also be used.
RTC
32 kHz oscillation circuit
Power-on circuit
Back up register: 32 bytes
Port circuit
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Two Power Supplies
Wide range voltage: VCC = 2.7 V to 5.5 V
Power supply for VBAT: VBAT = 2.7 V to 5.5 V
Document Number: 002-04918 Rev.*D Page 5 of 160
MB9B160R Series
Contents
1. Product Lineup .................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. Pin Description ................................................................................................................................................................ 15
5. I/O Circuit Type................................................................................................................................................................ 43
6. Handling Precautions ..................................................................................................................................................... 50
6.1 Precautions for Product Design ................................................................................................................................... 50
6.2 Precautions for Package Mounting .............................................................................................................................. 51
6.3 Precautions for Use Environment ................................................................................................................................ 52
7. Handling Devices ............................................................................................................................................................ 53
8. Block Diagram ................................................................................................................................................................. 56
9. Memory Size .................................................................................................................................................................... 57
10. Memory Map .................................................................................................................................................................... 57
11. Pin Status in Each CPU State ........................................................................................................................................ 60
12. Electrical Characteristics ............................................................................................................................................... 67
12.1 Absolute Maximum Ratings ......................................................................................................................................... 67
12.2 Recommended Operating Conditions.......................................................................................................................... 68
12.3 DC Characteristics....................................................................................................................................................... 71
12.3.1 Current Rating .............................................................................................................................................................. 71
12.3.2 Pin Characteristics ....................................................................................................................................................... 79
12.4 AC Characteristics ....................................................................................................................................................... 81
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 81
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 82
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 82
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL) ......................................... 83
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input clock of main PLL) .... 83
12.4.6 Reset Input Characteristics .......................................................................................................................................... 83
12.4.7 Power-on Reset Timing ................................................................................................................................................ 84
12.4.8 GPIO Output Characteristics ........................................................................................................................................ 84
12.4.9 External Bus Timing ..................................................................................................................................................... 85
12.4.10 Base Timer Input Timing ........................................................................................................................................... 96
12.4.11 CSIO/UART Timing .................................................................................................................................................. 97
12.4.12 External Input Timing .............................................................................................................................................. 130
12.4.13 Quadrature Position/Revolution Counter Timing .................................................................................................... 131
12.4.14 I2C Timing ............................................................................................................................................................... 133
12.4.15 SD Card Interface Timing ....................................................................................................................................... 135
12.4.16 ETM Timing ............................................................................................................................................................ 137
12.4.17 JTAG Timing ........................................................................................................................................................... 138
12.5 12-bit A/D Converter .................................................................................................................................................. 139
12.6 12-bit D/A Converter .................................................................................................................................................. 142
12.7 Low-Voltage Detection Characteristics ...................................................................................................................... 143
12.7.1 Low-Voltage Detection Reset ..................................................................................................................................... 143
12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 143
12.8 MainFlash Memory Write/Erase Characteristics ........................................................................................................ 144
12.9 WorkFlash Memory Write/Erase Characteristics ....................................................................................................... 144
12.10 Standby Recovery Time ............................................................................................................................................ 145
12.10.1 Recovery cause: Interrupt/WKUP ........................................................................................................................... 145
Document Number: 002-04918 Rev.*D Page 6 of 160
MB9B160R Series
12.10.2 Recovery cause: Reset ........................................................................................................................................... 147
13. Ordering Information .................................................................................................................................................... 149
14. Package Dimensions .................................................................................................................................................... 150
15. Major Changes .............................................................................................................................................................. 157
Document History ............................................................................................................................................................... 158
Sales, Solutions, and Legal Information ........................................................................................................................... 160
Document Number: 002-04918 Rev.*D Page 7 of 160
MB9B160R Series
1. Product Lineup
Memory Size
Product name
MB9BF166M/N/R
MB9BF167M/N/R
MainFlash memory
512 Kbytes
768 Kbytes
WorkFlash memory
32 Kbytes
32 Kbytes
On-chip SRAM
64 Kbytes
96 Kbytes
SRAM0
32 Kbytes
48 Kbytes
SRAM1
16 Kbytes
24 Kbytes
SRAM1
16 Kbytes
24 Kbytes
Function
Product name
MB9BF166M
MB9BF167M
MB9BF168M
MB9BF166N
MB9BF167N
MB9BF168N
MB9BF166R
MB9BF167R
MB9BF168R
Pin count
80
100/112
120/144
CPU
Cortex-M4F, MPU, NVIC 128ch.
Freq.
160 MHz
Power supply voltage range
2.7 V to 5.5 V
DMAC
8 ch.
DSTC
128 ch.
External Bus Interface
Addr:19-bit (Max),
R/W data: 8-bit
(Max),
CS:5 (Max),
SRAM,
NOR Flash
Addr:25-bit (Max),
R/W data: 8-/16-bit
(Max),
CS:9 (Max),
SRAM,
NOR Flash,
SDRAM
Addr:25-bit (Max),
R/W data: 8-/16-bit
(Max),
CS:9 (Max),
SRAM,
NOR Flash,
NAND Flash, SDRAM
Multi-function Serial Interface (UART/CSIO/LIN/I2C)
8 ch. (Max)
Base Timer
(PWC/Reload timer/PWM/PPG)
8 ch. (Max)
MF Timer
A/D activation compare
6 ch.
2 units (Max)
Input capture
4 ch.
Free-run timer
3 ch.
Output compare
6 ch.
Waveform generator
3 ch.
PPG
3 ch.
SD Card Interface
1 unit
QPRC
2 ch. (Max)
Dual Timer
1 unit
Real-Time Clock
1 unit
Watch Counter
1 unit
CRC Accelerator
Yes
Watchdog Timer
1 ch. (SW) + 1 ch. (HW)
External Interrupts
16 pins (Max) + NMI × 1
I/O Ports
63 pins (Max)
80 pins (Max)
100 pins (Max)
12-bit A/D Converter
16 ch. (3 units)
24 ch. (3 units)
12-bit D/A Converter
2 units (Max)
CSV (Clock Super Visor)
Yes
LVD (Low-Voltage Detector)
2 ch.
Built-in CR
High-speed
4 MHz
Low-speed
100 kHz
Debug Function
SWJ-DP/ETM
Unique ID
Yes
Notes:
− All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
− See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Built-in CR Oscillation Characteristics” for accuracy of
built-in CR.
Document Number: 002-04918 Rev.*D Page 8 of 160
MB9B160R Series
2. Packages
Product name
Package
MB9BF166M
MB9BF167M
MB9BF168M
MB9BF166N
MB9BF167N
MB9BF168N
MB9BF166R
MB9BF167R
MB9BF168R
LQFP: LQH080 (0.5 mm pitch)
-
-
LQFP: LQJ080 (0.65 mm pitch)
-
-
QFP: PQH100 (0.65 mm pitch)
-
-
LQFP: LQI100 (0.5 mm pitch)
-
-
LQFP: LQM120 (0.5 mm pitch)
-
-
BGA: LDC112 (0.5 mm pitch)
-
-
BGA: LDC144 (0.5 mm pitch)
-
-
: Supported
Note:
− See "Package Dimensions" for detailed information on each package.
Document Number: 002-04918 Rev.*D Page 9 of 160
MB9B160R Series
3. Pin Assignment
LQH080/LQJ080
(TOP VIEW)
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
VSS
P81
P80
VCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/INT03_0/S_CD_0/MWEX_0
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P09/AN19/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VCC 1 60 VSS
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0 2 59 P21/AN17/SIN0_0/INT06_1
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 3 58 P22/CROUT_0/AN16/TIOB7_1/SOT0_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 4 57 P23/AN15/TIOA7_1/SCK0_0/RTO00_1
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 5 56 P1B/AN11/SCK4_1/IC02_1/MAD18_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 6 55 P1A/AN10/SOT4_1/IC01_1/MAD17_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 7 54 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 8 53 P18/AN08/SCK2_2/MAD15_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0 9 52 AVRH
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 10 51 AVRL
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 11 50 AVSS
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 12 49 AVCC
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2 13 48 P17/AN07/SOT2_2/WKUP3/MAD14_0
P3A/TIOA0_1/AIN0_0/RTO00_0 14 47 P16/AN06/SIN2_2/INT14_1/MAD13_0
P3B/TIOA1_1/BIN0_0/RTO01_0 15 46 P15/AN05/SCK0_1/MAD12_0
P3C/TIOA2_1/ZIN0_0/RTO02_0 16 45 P14/AN04/SOT0_1/IC03_2/MAD11_0
P3D/TIOA3_1/RTO03_0/MAD00_0 17 44 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
P3E/TIOA4_1/RTO04_0/MAD01_0 18 43 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
P3F/TIOA5_1/RTO05_0/MAD02_0 19 42 P11/AN01/SOT1_1/IC00_2/MAD08_0
VSS 20 41 P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P44/TIOA4_0/RTO14_1/DA0
P45/TIOB0_0/RTO15_1/DA1
INITX
P46/X0A
P47/X1A
P48/VREGCTL
P49/VWAKEUP
VBAT
C
VSS
VCC
P4B/TIOB1_0/SCS7_1/MAD03_0
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 80
Document Number: 002-04918 Rev.*D Page 10 of 160
MB9B160R Series
LQI100
(TOP VIEW)
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
VSS
P81
P80
VCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/INT03_0/S_CD_0/MWEX_0
VSS
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0
P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0
P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0
P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0
P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VCC 1 75 VSS
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0 2 74 P20/AN18/AIN1_1/INT05_0/MAD24_0
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 3 73 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 4 72 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 5 71 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 6 70 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 7 69 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 8 68 P1C/AN12/CTS4_1/IC03_1/MAD19_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0 9 67 P1B/AN11/SCK4_1/IC02_1/MAD18_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 10 66 P1A/AN10/SOT4_1/IC01_1/MAD17_0
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 11 65 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 12 64 P18/AN08/SCK2_2/MAD15_0
P34/TIOB4_1/FRCK0_0/MADATA11_0 13 63 AVRH
P35/TIOB5_1/IC03_0/INT08_1/MADATA12_0 14 62 AVRL
P36/SIN5_2/IC02_0/INT09_1/MADATA13_0 15 61 AVSS
P37/SOT5_2/IC01_0/INT05_2/MADATA14_0 16 60 AVCC
P38/SCK5_2/IC00_0/INT06_2/MADATA15_0 17 59 P17/AN07/SOT2_2/WKUP3/MAD14_0
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 18 58 P16/AN06/SIN2_2/INT14_1/MAD13_0
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 19 57 P15/AN05/SCK0_1/MAD12_0
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 20 56 P14/AN04/SOT0_1/IC03_2/MAD11_0
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 21 55 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
P3D/TIOA3_1/RTO03_0/MAD00_0 22 54 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
P3E/TIOA4_1/RTO04_0/MAD01_0 23 53 P11/AN01/SOT1_1/IC00_2/MAD08_0
P3F/TIOA5_1/RTO05_0/MAD02_0 24 52 P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0
VSS 25 51 VCC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
P40/TIOA0_0/RTO10_1/INT12_1
P41/TIOA1_0/RTO11_1/INT13_1
P42/TIOA2_0/RTO12_1/MSDWEX_0
P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0
P44/TIOA4_0/RTO14_1/DA0
P45/TIOB0_0/RTO15_1/DA1
INITX
P46/X0A
P47/X1A
P48/VREGCTL
P49/VWAKEUP
VBAT
C
VSS
VCC
P4B/TIOB1_0/SCS7_1/MAD03_0
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 100
Document Number: 002-04918 Rev.*D Page 11 of 160
MB9B160R Series
LQM120
(TOP VIEW)
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
VSS
P81
P80
VCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/SIN5_1/INT03_0/S_CD_0/MWEX_0
P64/TIOA7_0/SOT5_1/INT10_2
P65/TIOB7_0/SCK5_1
P66/ADTG_8/SIN3_0/INT11_2
P67/TIOA7_2/SOT3_0
P68/TIOB7_2/SCK3_0/INT00_2
VSS
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0
P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0
P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0
P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0
P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
VCC 1 90 VSS
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0 2 89 P20/AN18/AIN1_1/INT05_0/MAD24_0
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 3 88 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 4 87 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 5 86 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 6 85 P24/SIN2_1/RTO01_1/INT01_2
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 7 84 P25/TIOA5_0/SOT2_1/RTO02_1
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 8 83 P26/TIOB5_0/SCK2_1/RTO03_1
P57/SCK6_0/MADATA07_0 9 82 P27/TIOA6_2/RTO04_1/INT02_2
P58/SIN4_2/AIN1_0/INT04_2/MADATA08_0 10 81 P1F/ADTG_4/TIOB6_2/RTO05_1
P59/SOT4_2/BIN1_0/INT07_1/MADATA09_0 11 80 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
P5A/SCK4_2/ZIN1_0/MADATA10_0 12 79 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
P5B/CTS4_2/MADATA11_0 13 78 P1C/AN12/CTS4_1/IC03_1/MAD19_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA12_0 14 77 P1B/AN11/SCK4_1/IC02_1/MAD18_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA13_0 15 76 P1A/AN10/SOT4_1/IC01_1/MAD17_0
P32/TIOB2_1/SOT3_1/INT10_1/MADATA14_0 16 75 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA15_0 17 74 P18/AN08/SCK2_2/MAD15_0
P34/TIOB4_1/FRCK0_0/MNALE_0 18 73 AVRH
P35/TIOB5_1/IC03_0/INT08_1/MNCLE_0 19 72 AVRL
P36/SIN5_2/IC02_0/INT09_1/MNWEX_0 20 71 AVSS
P37/SOT5_2/IC01_0/INT05_2/MNREX_0 21 70 AVCC
P38/SCK5_2/IC00_0/INT06_2 22 69 P17/AN07/SOT2_2/WKUP3/MAD14_0
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 23 68 P16/AN06/SIN2_2/INT14_1/MAD13_0
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 24 67 P15/AN05/SCK0_1/MAD12_0
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 25 66 P14/AN04/SOT0_1/IC03_2/MAD11_0
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 26 65 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
P3D/TIOA3_1/RTO03_0/MAD00_0 27 64 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
P3E/TIOA4_1/RTO04_0/MAD01_0 28 63 P11/AN01/SOT1_1/IC00_2/MAD08_0
P3F/TIOA5_1/RTO05_0/MAD02_0 29 62 P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0
VSS 30 61 VCC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VCC
P40/TIOA0_0/RTO10_1/INT12_1
P41/TIOA1_0/RTO11_1/INT13_1
P42/TIOA2_0/RTO12_1/MSDWEX_0
P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0
P44/TIOA4_0/RTO14_1/DA0
P45/TIOB0_0/RTO15_1/DA1
INITX
P46/X0A
P47/X1A
P48/VREGCTL
P49/VWAKEUP
VBAT
C
VSS
VCC
P4B/TIOB1_0/SCS7_1/MAD03_0
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
P70/TIOA4_2/AIN0_1/IC13_1
P71/TIOB4_2/BIN0_1/IC12_1/INT15_1
P72/TIOA6_0/SIN2_0/ZIN0_1/IC11_1/INT14_2
P73/TIOB6_0/SOT2_0/IC10_1/INT03_2
P74/SCK2_0/DTTI1X_1
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 120
Document Number: 002-04918 Rev.*D Page 12 of 160
MB9B160R Series
PQH100
(TOP VIEW)
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
VCC
VSS
P81
P80
VCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/INT03_0/S_CD_0/MWEX_0
VSS
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0
P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0
P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0
P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0
P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
VSS
P20/AN18/AIN1_1/INT05_0/MAD24_0
P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 81 50 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 82 49 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 83 48 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 84 47 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 85 46 P1C/AN12/CTS4_1/IC03_1/MAD19_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 86 45 P1B/AN11/SCK4_1/IC02_1/MAD18_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0 87 44 P1A/AN10/SOT4_1/IC01_1/MAD17_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 88 43 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 89 42 P18/AN08/SCK2_2/MAD15_0
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 90 41 AVRH
P34/TIOB4_1/FRCK0_0/MADATA11_0 91 40 AVRL
P35/TIOB5_1/IC03_0/INT08_1/MADATA12_0 92 39 AVSS
P36/SIN5_2/IC02_0/INT09_1/MADATA13_0 93 38 AVCC
P37/SOT5_2/IC01_0/INT05_2/MADATA14_0 94 37 P17/AN07/SOT2_2/WKUP3/MAD14_0
P38/SCK5_2/IC00_0/INT06_2/MADATA15_0 95 36 P16/AN06/SIN2_2/INT14_1/MAD13_0
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 96 35 P15/AN05/SCK0_1/MAD12_0
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 97 34 P14/AN04/SOT0_1/IC03_2/MAD11_0
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 98 33 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 99 32 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
P3D/TIOA3_1/RTO03_0/MAD00_0 100 31 P11/AN01/SOT1_1/IC00_2/MAD08_0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P3E/TIOA4_1/RTO04_0/MAD01_0
P3F/TIOA5_1/RTO05_0/MAD02_0
VSS
VCC
P40/TIOA0_0/RTO10_1/INT12_1
P41/TIOA1_0/RTO11_1/INT13_1
P42/TIOA2_0/RTO12_1/MSDWEX_0
P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0
P44/TIOA4_0/RTO14_1/DA0
P45/TIOB0_0/RTO15_1/DA1
INITX
P46/X0A
P47/X1A
P48/VREGCTL
P49/VWAKEUP
VBAT
C
VSS
VCC
P4B/TIOB1_0/SCS7_1/MAD03_0
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
VCC
P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0
QFP - 100
Document Number: 002-04918 Rev.*D Page 13 of 160
MB9B160R Series
LDC112
(TOP VIEW)
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
VSS
X0
X1
VSS
VCC
MD1
MD0
VSS
N
VSS
P40
P41
VSS
X0A
X1A
VSS
VBAT
P49
VCC
P4D
C
VSS
AN01
AN00
M
VCC
VSS
P42
P44
VSS
INITX
P45
P48
P4B
P4C
P4E
AN03
AN02
L
P3E
P3F
P43
AN04
K
P3C
P3D
AN06
AN05
AN08
AN07
AVCC
J
P39
P3A
P3B
AN10
AN09
AVSS
H
VSS
P37
P38
G
P34
P35
P36
AN12
AN11
AVRL
AN14
AN13
AVRH
F
P31
P32
P33
AN16
AN15
E
P55
P56
P30
AN20
VSS
AN18
AN17
D
P53
P54
VCC
C
P50
P51
P52
P63
TDI
TDO/
SWO
AN23
TMS/
SWDIO
AN22
AN19
P0C
P0D
VSS
P0E
VSS
B
VCC
VSS
P60
P61
P62
TRSTX
TCK/
SWCLK
VSS
AN21
P0A
P0B
VSS
A
VSS
P81
P80
VCC
VSS
8
9
10
11
12
13
1
2
3
4
5
6
7
index
Document Number: 002-04918 Rev.*D Page 14 of 160
MB9B160R Series
LDC144
(TOP VIEW)
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
MD1
X0
X1
VSS
VCC
P73
MD0
VSS
N
VSS
P40
P42
INITX
X0A
VSS
VBAT
C
VSS
P4D
VCC
VSS
VSS
AN00
VSS
M
VCC
VSS
P43
VSS
X1A
VSS
VSS
P48
P4B
P4E
P71
P74
P72
VSS
AN02
AN01
AVCC
L
P3F
P41
VSS
P44
AVSS
K
VSS
P3D
P3E
VSS
P45
P49
P4C
P70
AN05
AN04
AN03
AN07
AN06
AVRL
J
P39
P3A
P3B
P3C
AN08
AN11
AN10
AN09
AVRH
H
P35
P36
P37
P38
G
P31
P32
P33
P34
P1F
AN14
AN13
AN12
P24
P25
P26
P27
F
P59
P5A
P5B
P30
AN17
AN16
AN15
E
P55
P56
P57
P58
P65
TRSTX
TMS/
SWDIO
AN22
P0A
VSS
AN19
P0D
VSS
AN18
VSS
D
P52
P53
P54
VSS
P0E
C
P50
P51
VSS
P62
P64
P68
TDI
AN23
TCK/
SWCLK
TDO/
SWO
AN20
P0B
VSS
VSS
VCC
VSS
B
VCC
VSS
P60
P61
P63
P67
P66
VSS
VSS
AN21
VSS
P0C
A
VSS
P81
P80
VCC
VSS
8
9
10
11
12
13
7
1
2
3
4
5
6
index
Document Number: 002-04918 Rev.*D Page 15 of 160
MB9B160R Series
4. Pin Description
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
1
1
1
79
B1
B1
VCC
-
-
2
2
2
80
C1
C1
P50
E
K
CTS4_0
AIN0_2
RTO10_0
(PPG10_0)
INT00_0
MADATA00_0
3
3
3
81
C2
C2
P51
E
K
RTS4_0
BIN0_2
RTO11_0
(PPG10_0)
INT01_0
MADATA01_0
4
4
4
82
C3
D1
P52
E
I
SCK4_0
(SCL4_0)
ZIN0_2
RTO12_0
(PPG12_0)
MADATA02_0
5
5
5
83
D1
D2
P53
E
I
TIOA1_2
SOT4_0
(SDA4_0)
RTO13_0
(PPG12_0)
MADATA03_0
6
6
6
84
D2
D3
P54
E
K
TIOB1_2
SIN4_0
RTO14_0
(PPG14_0)
INT02_0
MADATA04_0
7
7
7
85
E1
E1
P55
E
K
ADTG_1
SIN6_0
RTO15_0
(PPG14_0)
INT07_2
MADATA05_0
Document Number: 002-04918 Rev.*D Page 16 of 160
MB9B160R Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
8
8
8
86
E2
E2
P56
E
K
SOT6_0
(SDA6_0)
DTTI1X_0
INT08_2
MADATA06_0
9
-
-
-
-
E3
P57
E
I
SCK6_0
(SCL6_0)
MADATA07_0
10
-
-
-
-
E4
P58
E
K
SIN4_2
AIN1_0
INT04_2
MADATA08_0
11
-
-
-
-
F1
P59
E
K
SOT4_2
(SDA4_2)
BIN1_0
INT07_1
MADATA09_0
12
-
-
-
-
F2
P5A
E
I
SCK4_2
(SCL4_2)
ZIN1_0
MADATA10_0
13
-
-
-
-
F3
P5B
E
I
CTS4_2
MADATA11_0
14
9
9
87
E3
F4
P30
E
Q
TIOB0_1
RTS4_2
INT15_2
WKUP1
-
-
MADATA07_0
14
-
-
-
-
F4
MADATA12_0
15
10
10
88
F1
G1
P31
I
K
TIOB1_1
SIN3_1
INT09_2
-
-
MADATA08_0
15
-
-
-
-
G1
MADATA13_0
Document Number: 002-04918 Rev.*D Page 17 of 160
MB9B160R Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
16
11
11
89
F2
G2
P32
N
K
TIOB2_1
SOT3_1
(SDA3_1)
INT10_1
-
-
MADATA09_0
16
-
-
-
-
G2
MADATA14_0
17
12
12
90
F3
G3
P33
N
K
ADTG_6
TIOB3_1
SCK3_1
(SCL3_1)
INT04_0
-
-
MADATA10_0
17
-
-
-
-
G3
MADATA15_0
18
13
-
91
G1
G4
P34
E
I
TIOB4_1
FRCK0_0
-
-
MADATA11_0
18
-
-
-
-
G4
MNALE_0
19
14
-
92
G2
H1
P35
E
K
TIOB5_1
IC03_0
INT08_1
-
-
MADATA12_0
19
-
-
-
-
H1
MNCLE_0
Document Number: 002-04918 Rev.*D Page 18 of 160
MB9B160R Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
20
15
-
93
G3
H2
P36
E
K
SIN5_2
IC02_0
INT09_1
-
-
MADATA13_0
20
-
-
-
-
H2
MNWEX_0
21
16
-
94
H2
H3
P37
E
K
SOT5_2
(SDA5_2)
IC01_0
INT05_2
-
-
MADATA14_0
21
-
-
-
-
H3
MNREX_0
22
17
-
95
H3
H4
P38
E
K
SCK5_2
(SCL5_2)
IC00_0
INT06_2
-
-
MADATA15_0
23
18
13
96
J1
J1
P39
L
I
ADTG_2
DTTI0X_0
RTCCO_2
SUBOUT_2
-
MSDCLK_0
24
19
14
97
J2
J2
P3A
G
I
TIOA0_1
AIN0_0
RTO00_0
(PPG00_0)
-
MSDCKE_0
25
20
15
98
J3
J3
P3B
G
I
TIOA1_1
BIN0_0
RTO01_0
(PPG00_0)
-
MRASX_0
Document Number: 002-04918 Rev.*D Page 19 of 160
MB9B160R Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
26
21
16
99
K1
J4
P3C
G
I
TIOA2_1
ZIN0_0
RTO02_0
(PPG02_0)
-
MCASX_0
27
22
17
100
K2
K2
P3D
G
I
TIOA3_1
RTO03_0
(PPG02_0)
MAD00_0
28
23
18
1
L1
K3
P3E
G
I
TIOA4_1
RTO04_0
(PPG04_0)
MAD01_0
29
24
19
2
L2
L1
P3F
G
I
TIOA5_1
RTO05_0
(PPG04_0)
MAD02_0
30
25
20
3
N1
N1
VSS
-
-
31
26
-
4
M1
M1
VCC
-
-
32
27
-
5
N2
N2
P40
G
K
TIOA0_0
RTO10_1
(PPG10_1)
INT12_1
33
28
-
6
N3
L2
P41
G
K
TIOA1_0
RTO11_1
(PPG10_1)
INT13_1
34
29
-
7
M3
N3
P42
G
I
TIOA2_0
RTO12_1
(PPG12_1)
MSDWEX_0
35
30
-
8
L3
M3
P43
G
I
ADTG_7
TIOA3_0
RTO13_1
(PPG12_1)
MCSX8_0
Document Number: 002-04918 Rev.*D Page 20 of 160
MB9B160R Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
36
31
21
9
M4
L4
P44
R
J
TIOA4_0
RTO14_1
(PPG14_1)
DA0
37
32
22
10
L5
K5
P45
R
J
TIOB0_0
RTO15_1
(PPG14_1)
DA1
38
33
23
11
M6
N4
INITX
B
C
39
34
24
12
N5
N5
P46
P
S
X0A
40
35
25
13
N6
M5
P47
Q
T
X1A
41
36
26
14
L6
L6
P48
O
U
VREGCTL
42
37
27
15
M7
K6
P49
O
U
VWAKEUP
43
38
28
16
N8
N7
VBAT
-
-
44
39
29
17
N9
N8
C
-
-
45
40
30
18
N10
N9
VSS
-
-
46
41
31
19
M8
M9
VCC
-
-
47
42
32
20
L7
L7
P4B
E
I
TIOB1_0
SCS7_1
MAD03_0
48
43
33
21
L8
K7
P4C
N
I
TIOB2_0
SCK7_1
(SCL7_1)
AIN1_2
MAD04_0
49
44
34
22
M9
M8
P4D
N
K
TIOB3_0
SOT7_1
(SDA7_1)
BIN1_2
INT13_2
MAD05_0
50
45
35
23
L9
L8
P4E
I
Q
TIOB4_0
SIN7_1
ZIN1_2
FRCK1_1
INT11_1
WKUP2
MAD06_0
Document Number: 002-04918 Rev.*D Page 21 of 160
MB9B160R Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
51
-
-
-
-
K8
P70
E
I
TIOA4_2
AIN0_1
IC13_1
52
-
-
-
-
L9
P71
E
K
TIOB4_2
BIN0_1
IC12_1
INT15_1
53
-
-
-
-
K9
P72
E
K
TIOA6_0
SIN2_0
ZIN0_1
IC11_1
INT14_2
54
-
-
-
-
M10
P73
E
K
TIOB6_0
SOT2_0
(SDA2_0)
IC10_1
INT03_2
55
-
-
-
-
L10
P74
E
I
SCK2_0
(SCL2_0)
DTTI1X_1
56
46
36
24
M10
N10
PE0
C
E
MD1
57
47
37
25
M11
M11
MD0
J
D
58
48
38
26
N11
N11
PE2
A
A
X0
59
49
39
27
N12
N12
PE3
A
B
X1
60
50
40
28
N13
N13
VSS
-
-
61
51
-
29
M13
M13
VCC
-
-
62
52
41
30
L13
L12
P10
F
M
AN00
SIN1_1
FRCK0_2
INT02_1
MAD07_0
63
53
42
31
L12
K12
P11
F
L
AN01
SOT1_1
(SDA1_1)
IC00_2
MAD08_0
Document Number: 002-04918 Rev.*D Page 22 of 160
MB9B160R Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
64
54
43
32
K13
K11
P12
F
L
AN02
SCK1_1
(SCL1_1)
IC01_2
RTCCO_1
SUBOUT_1
MAD09_0
65
55
44
33
K12
J12
P13
F
M
AN03
SIN0_1
IC02_2
INT03_1
MAD10_0
66
56
45
34
J13
J11
P14
F
L
AN04
SOT0_1
(SDA0_1)
IC03_2
MAD11_0
67
57
46
35
J12
J10
P15
F
L
AN05
SCK0_1
(SCL0_1)
MAD12_0
68
58
47
36
J11
H12
P16
F
M
AN06
SIN2_2
INT14_1
MAD13_0
69
59
48
37
H12
H11
P17
F
P
AN07
SOT2_2
(SDA2_2)
WKUP3
MAD14_0
70
60
49
38
H13
K13
AVCC
-
-
71
61
50
39
G13
J13
AVSS
-
-
72
62
51
40
F13
H13
AVRL
-
-
73
63
52
41
E13
G13
AVRH
-
-
74
64
53
42
H11
H10
P18
F
L
AN08
SCK2_2
(SCL2_2)
MAD15_0
Document Number: 002-04918 Rev.*D Page 23 of 160
MB9B160R Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
75
65
54
43
G12
G12
P19
F
M
AN09
SIN4_1
IC00_1
INT05_1
MAD16_0
76
66
55
44
G11
G11
P1A
M
L
AN10
SOT4_1
(SDA4_1)
IC01_1
MAD17_0
77
67
56
45
F12
G10
P1B
M
L
AN11
SCK4_1
(SCL4_1)
IC02_1
MAD18_0
78
68
-
46
F11
F13
P1C
F
L
AN12
CTS4_1
IC03_1
MAD19_0
79
69
-
47
E12
F12
P1D
F
L
AN13
RTS4_1
DTTI0X_1
MAD20_0
80
70
-
48
E11
F11
P1E
F
L
AN14
ADTG_5
FRCK0_1
MAD21_0
81
-
-
-
-
F10
P1F
E
I
ADTG_4
TIOB6_2
RTO05_1
(PPG04_1)
82
-
-
-
-
E13
P27
E
K
TIOA6_2
RTO04_1
(PPG04_1)
INT02_2
Document Number: 002-04918 Rev.*D Page 24 of 160
MB9B160R Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
83
-
-
-
-
E12
P26
E
I
TIOB5_0
SCK2_1
(SCL2_1)
RTO03_1
(PPG02_1)
84
-
-
-
-
E11
P25
E
I
TIOA5_0
SOT2_1
(SDA2_1)
RTO02_1
(PPG02_1)
85
-
-
-
-
E10
P24
E
K
SIN2_1
RTO01_1
(PPG00_1)
INT01_2
86
71
57
49
D13
D13
P23
F
L
AN15
TIOA7_1
SCK0_0
(SCL0_0)
RTO00_1
(PPG00_1)
-
MAD22_0
87
72
58
50
D12
D12
P22
F
L
CROUT_0
AN16
TIOB7_1
SOT0_0
(SDA0_0)
-
ZIN1_1
88
73
59
51
C13
D11
P21
F
M
AN17
SIN0_0
-
BIN1_1
59
INT06_1
-
MAD23_0
89
74
-
52
C12
C12
P20
F
M
AN18
AIN1_1
INT05_0
MAD24_0
90
75
60
53
A13
A13
VSS
-
-
91
76
61
54
B13
A12
VCC
-
-
Document Number: 002-04918 Rev.*D Page 25 of 160
MB9B160R Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
92
77
62
55
A12
B13
P0E
L
I
TIOB5_2
SCS6_1
IC13_0
S_CLK_0
MDQM1_0
93
78
63
56
B11
C10
P0D
L
I
TIOA5_2
SCK6_1
(SCL6_1)
IC12_0
S_CMD_0
MDQM0_0
94
79
64
57
B10
A11
P0C
L
I
TIOA6_1
SOT6_1
(SDA6_1)
IC11_0
S_DATA1_0
MALE_0
95
80
65
58
A10
B10
P0B
L
K
TIOB6_1
SIN6_1
IC10_0
INT00_1
S_DATA0_0
MCSX0_0
96
81
66
59
A9
D9
P0A
L
K
SIN1_0
FRCK1_0
INT12_2
S_DATA3_0
MCSX1_0
97
82
67
60
B9
C9
P09
M
N
AN19
-
TRACED0
67
TIOA3_2
SOT1_0
(SDA1_0)
S_DATA2_0
MCSX5_0
98
83
-
61
C9
B9
P08
F
N
AN20
TRACED1
TIOB3_2
SCK1_0
(SCL1_0)
MCSX4_0
Document Number: 002-04918 Rev.*D Page 26 of 160
MB9B160R Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
99
84
-
62
A8
A9
P07
F
N
AN21
TRACED2
TIOA0_2
SCK7_0
(SCL7_0)
MCLKOUT_0
100
85
-
63
B8
D8
P06
F
N
AN22
TRACED3
TIOB0_2
SOT7_0
(SDA7_0)
MCSX3_0
101
86
-
64
C8
C8
P05
F
O
AN23
ADTG_0
TRACECLK
SIN7_0
INT01_1
MCSX2_0
102
87
68
65
C7
B8
P04
E
G
TDO
SWO
103
88
69
66
B7
D7
P03
E
G
TMS
SWDIO
104
89
70
67
C6
C7
P02
E
H
TDI
MCSX6_0
105
90
71
68
A6
B7
P01
E
G
TCK
SWCLK
106
91
72
69
B6
D6
P00
E
H
TRSTX
MCSX7_0
107
92
-
70
A5
A7
VSS
-
-
108
-
-
-
-
C6
P68
E
K
TIOB7_2
SCK3_0
(SCL3_0)
INT00_2
109
-
-
-
-
B6
P67
E
I
TIOA7_2
SOT3_0
(SDA3_0)
Document Number: 002-04918 Rev.*D Page 27 of 160
MB9B160R Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
110
-
-
-
-
A6
P66
E
K
ADTG_8
SIN3_0
INT11_2
111
-
-
-
-
D5
P65
E
I
TIOB7_0
SCK5_1
(SCL5_1)
112
-
-
-
-
C5
P64
E
K
TIOA7_0
SOT5_1
(SDA5_1)
INT10_2
113
93
73
71
C5
B5
P63
E
K
CROUT_1
-
-
-
-
SIN5_1
93
73
71
C5
INT03_0
S_CD_0
MWEX_0
114
94
74
72
B5
C4
P62
I
K
ADTG_3
SIN5_0
INT04_1
S_WP_0
MOEX_0
115
95
75
73
B4
B4
P61
E
I
TIOB2_2
SOT5_0
(SDA5_0)
RTCCO_0
SUBOUT_0
116
96
76
74
B3
B3
P60
I
F
TIOA2_2
SCK5_0
(SCL5_0)
NMIX
WKUP0
MRDY_0
117
97
77
75
A4
A4
VCC
-
-
118
98
78
76
A3
A3
P80
H
R
119
99
79
77
A2
A2
P81
H
R
Document Number: 002-04918 Rev.*D Page 28 of 160
MB9B160R Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
120
100
80
78
A1
A1
VSS
-
-
-
-
-
-
A7
A5
-
-
-
-
-
-
B2
A8
-
-
-
-
-
-
B12
A10
-
-
-
-
-
-
C11
B2
-
-
-
-
-
-
H1
B11
-
-
-
-
-
-
N4
B12
-
-
-
-
-
-
M5
C3
-
-
-
-
-
-
N7
C11
-
-
-
-
-
-
L11
C13
-
-
-
-
-
-
A11
D4
-
-
-
-
-
-
M12
D10
-
-
-
-
-
-
M2
K1
-
-
-
-
-
-
-
K4
-
-
-
-
-
-
-
K10
-
-
-
-
-
-
-
L3
-
-
-
-
-
-
-
L5
-
-
-
-
-
-
-
L11
-
-
-
-
-
-
-
L13
-
-
-
-
-
-
-
M2
-
-
-
-
-
-
-
M4
-
-
-
-
-
-
-
M6
-
-
-
-
-
-
-
M7
-
-
-
-
-
-
-
M12
-
-
-
-
-
-
-
N6
-
-
Document Number: 002-04918 Rev.*D Page 29 of 160
MB9B160R Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
ADC
ADTG_0
A/D converter external trigger input pin
101
86
-
64
C8
C8
ADTG_1
7
7
7
85
E1
E1
ADTG_2
23
18
13
96
J1
J1
ADTG_3
114
94
74
72
B5
C4
ADTG_4
81
-
-
-
-
F10
ADTG_5
80
70
-
48
E11
F11
ADTG_6
17
12
12
90
F3
G3
ADTG_7
35
30
-
8
L3
M3
ADTG_8
110
-
-
-
-
A6
AN00
A/D converter analog input pin.
ANxx describes ADC ch.xx.
62
52
41
30
L13
L12
AN01
63
53
42
31
L12
K12
AN02
64
54
43
32
K13
K11
AN03
65
55
44
33
K12
J12
AN04
66
56
45
34
J13
J11
AN05
67
57
46
35
J12
J10
AN06
68
58
47
36
J11
H12
AN07
69
59
48
37
H12
H11
AN08
74
64
53
42
H11
H10
AN09
75
65
54
43
G12
G12
AN10
76
66
55
44
G11
G11
AN11
77
67
56
45
F12
G10
AN12
78
68
-
46
F11
F13
AN13
79
69
-
47
E12
F12
AN14
80
70
-
48
E11
F11
AN15
86
71
57
49
D13
D13
AN16
87
72
58
50
D12
D12
AN17
88
73
59
51
C13
D11
AN18
89
74
-
52
C12
C12
AN19
97
82
67
60
B9
C9
AN20
98
83
-
61
C9
B9
AN21
99
84
-
62
A8
A9
AN22
100
85
-
63
B8
D8
AN23
101
86
-
64
C8
C8
Base Timer
0
TIOA0_0
Base timer ch.0 TIOA pin
32
27
-
5
N2
N2
TIOA0_1
24
19
14
97
J2
J2
TIOA0_2
99
84
-
62
A8
A9
TIOB0_0
Base timer ch.0 TIOB pin
37
32
22
10
L5
K5
TIOB0_1
14
9
9
87
E3
F4
TIOB0_2
100
85
-
63
B8
D8
Base Timer
1
TIOA1_0
Base timer ch.1 TIOA pin
33
28
-
6
N3
L2
TIOA1_1
25
20
15
98
J3
J3
TIOA1_2
5
5
5
83
D1
D2
TIOB1_0
Base timer ch.1 TIOB pin
47
42
32
20
L7
L7
TIOB1_1
15
10
10
88
F1
G1
TIOB1_2
6
6
6
84
D2
D3
Base Timer
2
TIOA2_0
Base timer ch.2 TIOA pin
34
29
-
7
M3
N3
TIOA2_1
26
21
16
99
K1
J4
TIOA2_2
116
96
76
74
B3
B3
TIOB2_0
Base timer ch.2 TIOB pin
48
43
33
21
L8
K7
TIOB2_1
16
11
11
89
F2
G2
TIOB2_2
115
95
75
73
B4
B4
Document Number: 002-04918 Rev.*D Page 30 of 160
MB9B160R Series
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
Base Timer
3
TIOA3_0
Base timer ch.3 TIOA pin
35
30
-
8
L3
M3
TIOA3_1
27
22
17
100
K2
K2
TIOA3_2
97
82
67
60
B9
C9
TIOB3_0
Base timer ch.3 TIOB pin
49
44
34
22
M9
M8
TIOB3_1
17
12
12
90
F3
G3
TIOB3_2
98
83
-
61
C9
B9
Base Timer
4
TIOA4_0
Base timer ch.4 TIOA pin
36
31
21
9
M4
L4
TIOA4_1
28
23
18
1
L1
K3
TIOA4_2
51
-
-
-
-
K8
TIOB4_0
Base timer ch.4 TIOB pin
50
45
35
23
L9
L8
TIOB4_1
18
13
-
91
G1
G4
TIOB4_2
52
-
-
-
-
L9
Base Timer
5
TIOA5_0
Base timer ch.5 TIOA pin
84
-
-
-
-
E11
TIOA5_1
29
24
19
2
L2
L1
TIOA5_2
93
78
63
56
B11
C10
TIOB5_0
Base timer ch.5 TIOB pin
83
-
-
-
-
E12
TIOB5_1
19
14
-
92
G2
H1
TIOB5_2
92
77
62
55
A12
B13
Base Timer
6
TIOA6_0
Base timer ch.6 TIOA pin
53
-
-
-
-
K9
TIOA6_1
94
79
64
57
B10
A11
TIOA6_2
82
-
-
-
-
E13
TIOB6_0
Base timer ch.6 TIOB pin
54
-
-
-
-
M10
TIOB6_1
95
80
65
58
A10
B10
TIOB6_2
81
-
-
-
-
F10
Base Timer
7
TIOA7_0
Base timer ch.7 TIOA pin
112
-
-
-
-
C5
TIOA7_1
86
71
57
49
D13
D13
TIOA7_2
109
-
-
-
-
B6
TIOB7_0
Base timer ch.7 TIOB pin
111
-
-
-
-
D5
TIOB7_1
87
72
58
50
D12
D12
TIOB7_2
108
-
-
-
-
C6
Debugger
SWCLK
Serial wire debug interface clock input pin
105
90
71
68
A6
B7
SWDIO
Serial wire debug interface data input / output pin
103
88
69
66
B7
D7
SWO
Serial wire viewer output pin
102
87
68
65
C7
B8
TCK
JTAG test clock input pin
105
90
71
68
A6
B7
TDI
JTAG test data input pin
104
89
70
67
C6
C7
TDO
JTAG debug data output pin
102
87
68
65
C7
B8
TMS
JTAG test mode state input/output pin
103
88
69
66
B7
D7
TRACECLK
Trace CLK output pin of ETM
101
86
-
64
C8
C8
TRACED0
Trace data output pin of ETM
97
82
-
60
B9
C9
TRACED1
98
83
-
61
C9
B9
TRACED2
99
84
-
62
A8
A9
TRACED3
100
85
-
63
B8
D8
TRSTX
JTAG test reset Input pin
106
91
72
69
B6
D6
Document Number: 002-04918 Rev.*D Page 31 of 160
MB9B160R Series
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
External
Bus
MAD00_0
External bus interface address bus
27
22
17
100
K2
K2
MAD01_0
28
23
18
1
L1
K3
MAD02_0
29
24
19
2
L2
L1
MAD03_0
47
42
32
20
L7
L7
MAD04_0
48
43
33
21
L8
K7
MAD05_0
49
44
34
22
M9
M8
MAD06_0
50
45
35
23
L9
L8
MAD07_0
62
52
41
30
L13
L12
MAD08_0
63
53
42
31
L12
K12
MAD09_0
64
54
43
32
K13
K11
MAD10_0
65
55
44
33
K12
J12
MAD11_0
66
56
45
34
J13
J11
MAD12_0
67
57
46
35
J12
J10
MAD13_0
68
58
47
36
J11
H12
MAD14_0
69
59
48
37
H12
H11
MAD15_0
74
64
53
42
H11
H10
MAD16_0
75
65
54
43
G12
G12
MAD17_0
76
66
55
44
G11
G11
MAD18_0
77
67
56
45
F12
G10
MAD19_0
78
68
-
46
F11
F13
MAD20_0
79
69
-
47
E12
F12
MAD21_0
80
70
-
48
E11
F11
MAD22_0
86
71
-
49
D13
D13
MAD23_0
88
73
-
51
C13
D11
MAD24_0
89
74
-
52
C12
C12
Document Number: 002-04918 Rev.*D Page 32 of 160
MB9B160R Series
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
External
Bus
MCSX0_0
External bus interface chip select output pin
95
80
65
58
A10
B10
MCSX1_0
96
81
66
59
A9
D9
MCSX2_0
101
86
-
64
C8
C8
MCSX3_0
100
85
-
63
B8
D8
MCSX4_0
98
83
-
61
C9
B9
MCSX5_0
97
82
67
60
B9
C9
MCSX6_0
104
89
70
67
C6
C7
MCSX7_0
106
91
72
69
B6
D6
MCSX8_0
35
30
-
8
L3
M3
MADATA00_0
External bus interface data bus
(Address / data multiplex bus)
2
2
2
80
C1
C1
MADATA01_0
3
3
3
81
C2
C2
MADATA02_0
4
4
4
82
C3
D1
MADATA03_0
5
5
5
83
D1
D2
MADATA04_0
6
6
6
84
D2
D3
MADATA05_0
7
7
7
85
E1
E1
MADATA06_0
8
8
8
86
E2
E2
MADATA07_0
9
9
9
87
E3
E3
MADATA08_0
10
10
10
88
F1
E4
MADATA09_0
11
11
11
89
F2
F1
MADATA10_0
12
12
12
90
F3
F2
MADATA11_0
13
13
-
91
G1
F3
MADATA12_0
14
14
-
92
G2
F4
MADATA13_0
15
15
-
93
G3
G1
MADATA14_0
16
16
-
94
H2
G2
MADATA15_0
17
17
-
95
H3
G3
MDQM0_0
External bus interface byte mask signal output pin
93
78
63
56
B11
C10
MDQM1_0
92
77
62
55
A12
B13
MALE_0
External bus interface Address Latch enable
output signal for multiplex
94
79
64
57
B10
A11
MRDY_0
External bus interface external RDY input signal
116
96
76
74
B3
B3
MCLKOUT_0
External bus interface external clock output pin
99
84
-
62
A8
A9
MNALE_0
External bus interface ALE signal to control
NAND Flash output pin
18
-
-
-
-
G4
MNCLE_0
External bus interface CLE signal to control
NAND Flash output pin
19
-
-
-
-
H1
MNREX_0
External bus interface read enable signal to
control NAND Flash
21
-
-
-
-
H3
MNWEX_0
External bus interface write enable signal to
control NAND Flash
20
-
-
-
-
H2
MOEX_0
External bus interface read enable signal for
SRAM
114
94
74
72
B5
C4
MWEX_0
External bus interface write enable signal for
SRAM
113
93
73
71
C5
B5
External
Bus
MSDCLK_0
SDRAM interface
SDRAM clock output pin
23
18
-
96
J1
J1
MSDCKE_0
SDRAM interface
SDRAM clock enable pin
24
19
-
97
J2
J2
MRASX_0
SDRAM interface
SDRAM row address strobe pin
25
20
-
98
J3
J3
MCASX_0
SDRAM interface
SDRAM column address strobe pin
26
21
-
99
K1
J4
MSDWEX_0
SDRAM interface
SDRAM write enable pin
34
29
-
7
M3
N3
Document Number: 002-04918 Rev.*D Page 33 of 160
MB9B160R Series
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
External
Interrupt
INT00_0
External interrupt request 00 input pin
2
2
2
80
C1
C1
INT00_1
95
80
65
58
A10
B10
INT00_2
108
-
-
-
-
C6
INT01_0
External interrupt request 01 input pin
3
3
3
81
C2
C2
INT01_1
101
86
-
64
C8
C8
INT01_2
85
-
-
-
-
E10
INT02_0
External interrupt request 02 input pin
6
6
6
84
D2
D3
INT02_1
62
52
41
30
L13
L12
INT02_2
82
-
-
-
-
E13
INT03_0
External interrupt request 03 input pin
113
93
73
71
C5
B5
INT03_1
65
55
44
33
K12
J12
INT03_2
54
-
-
-
-
M10
INT04_0
External interrupt request 04 input pin
17
12
12
90
F3
G3
INT04_1
114
94
74
72
B5
C4
INT04_2
10
-
-
-
-
E4
INT05_0
External interrupt request 05 input pin
89
74
-
52
C12
C12
INT05_1
75
65
54
43
G12
G12
INT05_2
21
16
-
94
H2
H3
INT06_1
External interrupt request 06 input pin
88
73
59
51
C13
D11
INT06_2
22
17
-
95
H3
H4
INT07_1
External interrupt request 07 input pin
11
-
-
-
-
F1
INT07_2
7
7
7
85
E1
E1
INT08_1
External interrupt request 08 input pin
19
14
-
92
G2
H1
INT08_2
8
8
8
86
E2
E2
INT09_1
External interrupt request 09 input pin
20
15
-
93
G3
H2
INT09_2
15
10
10
88
F1
G1
INT10_1
External interrupt request 10 input pin
16
11
11
89
F2
G2
INT10_2
112
-
-
-
-
C5
INT11_1
External interrupt request 11 input pin
50
45
35
23
L9
L8
INT11_2
110
-
-
-
-
A6
INT12_1
External interrupt request 12 input pin
32
27
-
5
N2
N2
INT12_2
96
81
66
59
A9
D9
INT13_1
External interrupt request 13 input pin
33
28
-
6
N3
L2
INT13_2
49
44
34
22
M9
M8
INT14_1
External interrupt request 14 input pin
68
58
47
36
J11
H12
INT14_2
53
-
-
-
-
K9
INT15_1
External interrupt request 15 input pin
52
-
-
-
-
L9
INT15_2
14
9
9
87
E3
F4
NMIX
Non-Maskable Interrupt input pin
116
96
76
74
B3
B3
Document Number: 002-04918 Rev.*D Page 34 of 160
MB9B160R Series
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
GPIO
P00
General-purpose I/O port 0
106
91
72
69
B6
D6
P01
105
90
71
68
A6
B7
P02
104
89
70
67
C6
C7
P03
103
88
69
66
B7
D7
P04
102
87
68
65
C7
B8
P05
101
86
-
64
C8
C8
P06
100
85
-
63
B8
D8
P07
99
84
-
62
A8
A9
P08
98
83
-
61
C9
B9
P09
97
82
67
60
B9
C9
P0A
96
81
66
59
A9
D9
P0B
95
80
65
58
A10
B10
P0C
94
79
64
57
B10
A11
P0D
93
78
63
56
B11
C10
P0E
92
77
62
55
A12
B13
P10
General-purpose I/O port 1
62
52
41
30
L13
L12
P11
63
53
42
31
L12
K12
P12
64
54
43
32
K13
K11
P13
65
55
44
33
K12
J12
P14
66
56
45
34
J13
J11
P15
67
57
46
35
J12
J10
P16
68
58
47
36
J11
H12
P17
69
59
48
37
H12
H11
P18
74
64
53
42
H11
H10
P19
75
65
54
43
G12
G12
P1A
76
66
55
44
G11
G11
P1B
77
67
56
45
F12
G10
P1C
78
68
-
46
F11
F13
P1D
79
69
-
47
E12
F12
P1E
80
70
-
48
E11
F11
P1F
81
-
-
-
-
F10
P20
General-purpose I/O port 2
89
74
-
52
C12
C12
P21
88
73
59
51
C13
D11
P22
87
72
58
50
D12
D12
P23
86
71
57
49
D13
D13
P24
85
-
-
-
-
E10
P25
84
-
-
-
-
E11
P26
83
-
-
-
-
E12
P27
82
-
-
-
-
E13
Document Number: 002-04918 Rev.*D Page 35 of 160
MB9B160R Series
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
GPIO
P30
General-purpose I/O port 3
14
9
9
87
E3
F4
P31
15
10
10
88
F1
G1
P32
16
11
11
89
F2
G2
P33
17
12
12
90
F3
G3
P34
18
13
-
91
G1
G4
P35
19
14
-
92
G2
H1
P36
20
15
-
93
G3
H2
P37
21
16
-
94
H2
H3
P38
22
17
-
95
H3
H4
P39
23
18
13
96
J1
J1
P3A
24
19
14
97
J2
J2
P3B
25
20
15
98
J3
J3
P3C
26
21
16
99
K1
J4
P3D
27
22
17
100
K2
K2
P3E
28
23
18
1
L1
K3
P3F
29
24
19
2
L2
L1
P40
General-purpose I/O port 4
32
27
-
5
N2
N2
P41
33
28
-
6
N3
L2
P42
34
29
-
7
M3
N3
P43
35
30
-
8
L3
M3
P44
36
31
21
9
M4
L4
P45
37
32
22
10
L5
K5
P46
39
34
24
12
N5
N5
P47
40
35
25
13
N6
M5
P48
41
36
26
14
L6
L6
P49
42
37
27
15
M7
K6
P4B
47
42
32
20
L7
L7
P4C
48
43
33
21
L8
K7
P4D
49
44
34
22
M9
M8
P4E
50
45
35
23
L9
L8
P50
General-purpose I/O port 5
2
2
2
80
C1
C1
P51
3
3
3
81
C2
C2
P52
4
4
4
82
C3
D1
P53
5
5
5
83
D1
D2
P54
6
6
6
84
D2
D3
P55
7
7
7
85
E1
E1
P56
8
8
8
86
E2
E2
P57
9
-
-
-
-
E3
P58
10
-
-
-
-
E4
P59
11
-
-
-
-
F1
P5A
12
-
-
-
-
F2
P5B
13
-
-
-
-
F3
Document Number: 002-04918 Rev.*D Page 36 of 160
MB9B160R Series
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
GPIO
P60
General-purpose I/O port 6
116
96
76
74
B3
B3
P61
115
95
75
73
B4
B4
P62
114
94
74
72
B5
C4
P63
113
93
73
71
C5
B5
P64
112
-
-
-
-
C5
P65
111
-
-
-
-
D5
P66
110
-
-
-
-
A6
P67
109
-
-
-
-
B6
P68
108
-
-
-
-
C6
P70
General-purpose I/O port 7
51
-
-
-
-
K8
P71
52
-
-
-
-
L9
P72
53
-
-
-
-
K9
P73
54
-
-
-
-
M10
P74
55
-
-
-
-
L10
P80
General-purpose I/O port 8
118
98
78
76
A3
A3
P81
119
99
79
77
A2
A2
PE0
General-purpose I/O port E
56
46
36
24
M10
N10
PE2
58
48
38
26
N11
N11
PE3
59
49
39
27
N12
N12
Multi- function
Serial
0
SIN0_0
Multi-function serial interface ch.0 input pin
88
73
59
51
C13
D11
SIN0_1
65
55
44
33
K12
J12
SOT0_0
(SDA0_0)
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA0 when it is used in an I2C (operation mode
4).
87
72
58
50
D12
D12
SOT0_1
(SDA0_1)
66
56
45
34
J13
J11
SCK0_0
(SCL0_0)
Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SCL0 when it is used in an I2C (operation mode
4).
86
71
57
49
D13
D13
SCK0_1
(SCL0_1)
67
57
46
35
J12
J10
Multi- function
Serial
1
SIN1_0
Multi-function serial interface ch.1 input pin
96
81
66
59
A9
D9
SIN1_1
62
52
41
30
L13
L12
SOT1_0
(SDA1_0)
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA1 when it is used in an I2C (operation mode
4).
97
82
67
60
B9
C9
SOT1_1
(SDA1_1)
63
53
42
31
L12
K12
SCK1_0
(SCL1_0)
Multi-function serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a
CSIO (operation modes 4) and as SCL1 when it is
used in an I2C (operation mode 4).
98
83
-
61
C9
B9
SCK1_1
(SCL1_1)
64
54
43
32
K13
K11
Document Number: 002-04918 Rev.*D Page 37 of 160
MB9B160R Series
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
Multi- function
Serial
2
SIN2_0
Multi-function serial interface ch.2 input pin
53
-
-
-
-
K9
SIN2_1
85
-
-
-
-
E10
SIN2_2
68
58
47
36
J11
H12
SOT2_0
(SDA2_0)
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA2 when it is used in an I2C (operation mode
4).
54
-
-
-
-
M10
SOT2_1
(SDA2_1)
84
-
-
-
-
E11
SOT2_2
(SDA2_2)
69
59
48
37
H12
H11
SCK2_0
(SCL2_0)
Multi-function serial interface ch.2 clock I/O pin.
This pin operates as SCK2 when it is used in a
CSIO (operation modes 2) and as SCL2 when it is
used in an I2C (operation mode 4).
55
-
-
-
-
L10
SCK2_1
(SCL2_1)
83
-
-
-
-
E12
SCK2_2
(SCL2_2)
74
64
53
42
H11
H10
Multi- function
Serial
3
SIN3_0
Multi-function serial interface ch.3 input pin
110
-
-
-
-
A6
SIN3_1
15
10
10
88
F1
G1
SOT3_0
(SDA3_0)
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA3 when it is used in an I2C (operation mode
4).
109
-
-
-
-
B6
SOT3_1
(SDA3_1)
16
11
11
89
F2
G2
SCK3_0
(SCL3_0)
Multi-function serial interface ch.3 clock I/O pin.
This pin operates as SCK3 when it is used in a
CSIO (operation modes 2) and as SCL3 when it is
used in an I2C (operation mode 4).
108
-
-
-
-
C6
SCK3_1
(SCL3_1)
17
12
12
90
F3
G3
Multi- function
Serial
4
SIN4_0
Multi-function serial interface ch.4 input pin
6
6
6
84
D2
D3
SIN4_1
75
65
54
43
G12
G12
SIN4_2
10
-
-
-
-
E4
SOT4_0
(SDA4_0)
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA4 when it is used in an I2C (operation mode
4).
5
5
5
83
D1
D2
SOT4_1
(SDA4_1)
76
66
55
44
G11
G11
SOT4_2
(SDA4_2)
11
-
-
-
-
F1
SCK4_0
(SCL4_0)
Multi-function serial interface ch.4 clock I/O pin.
This pin operates as SCK4 when it is used in a
CSIO (operation modes 2) and as SCL4 when it is
used in an I2C (operation mode 4).
4
4
4
82
C3
D1
SCK4_1
(SCL4_1)
77
67
56
45
F12
G10
SCK4_2
(SCL4_2)
12
-
-
-
-
F2
CTS4_0
Multi-function serial interface ch.4 CTS input pin
2
2
2
80
C1
C1
CTS4_1
78
68
-
46
F11
F13
CTS4_2
13
-
-
-
-
F3
RTS4_0
Multi-function serial interface ch.4 RTS output pin
3
3
3
81
C2
C2
RTS4_1
79
69
-
47
E12
F12
RTS4_2
14
9
9
87
E3
F4
Document Number: 002-04918 Rev.*D Page 38 of 160
MB9B160R Series
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
Multi- function
Serial
5
SIN5_0
Multi-function serial interface ch.5 input pin
114
94
74
72
B5
C4
SIN5_1
113
-
-
-
-
B5
SIN5_2
20
15
-
93
G3
H2
SOT5_0
(SDA5_0)
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA5 when it is used in an I2C (operation mode
4).
115
95
75
73
B4
B4
SOT5_1
(SDA5_1)
112
-
-
-
-
C5
SOT5_2
(SDA5_2)
21
16
-
94
H2
H3
SCK5_0
(SCL5_0)
Multi-function serial interface ch.5 clock I/O pin.
This pin operates as SCK5 when it is used in a
CSIO (operation modes 2) and as SCL5 when it is
used in an I2C (operation mode 4).
116
96
76
74
B3
B3
SCK5_1
(SCL5_1)
111
-
-
-
-
D5
SCK5_2
(SCL5_2)
22
17
-
95
H3
H4
Multi- function
Serial
6
SIN6_0
Multi-function serial interface ch.6 input pin
7
7
7
85
E1
E1
SIN6_1
95
80
65
58
A10
B10
SOT6_0
(SDA6_0)
Multi-function serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA6 when it is used in an I2C (operation mode
4).
8
8
8
86
E2
E2
SOT6_1
(SDA6_1)
94
79
64
57
B10
A11
SCK6_0
(SCL6_0)
Multi-function serial interface ch.6 clock I/O pin.
This pin operates as SCK6 when it is used in a
CSIO (operation modes 2) and as SCL6 when it is
used in an I2C (operation mode 4).
9
-
-
-
-
E3
SCK6_1
(SCL6_1)
93
78
63
56
B11
C10
SCS6_1
Multi-function serial interface ch.6 serial chip
select pin
92
77
62
55
A12
B13
Multi- function
Serial
7
SIN7_0
Multi-function serial interface ch.7 input pin
101
86
-
64
C8
C8
SIN7_1
50
45
35
23
L9
L8
SOT7_0
(SDA7_0)
Multi-function serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA7 when it is used in an I2C (operation mode
4).
100
85
-
63
B8
D8
SOT7_1
(SDA7_1)
49
44
34
22
M9
M8
SCK7_0
(SCL7_0)
Multi-function serial interface ch.7 clock I/O pin.
This pin operates as SCK7 when it is used in a
CSIO (operation modes 2) and as SCL7 when it is
used in an I2C (operation mode 4).
99
84
-
62
A8
A9
SCK7_1
(SCL7_1)
48
43
33
21
L8
K7
SCS7_1
Multi-function serial interface ch.7 serial chip
select pin
47
42
32
20
L7
L7
Document Number: 002-04918 Rev.*D Page 39 of 160
MB9B160R Series
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
Multi-
function
Timer
0
DTTI0X_0
Input signal controlling wave form generator
outputs RTO00 to RTO05 of Multi-function timer
0.
23
18
13
96
J1
J1
DTTI0X_1
79
69
-
47
E12
F12
FRCK0_0
16-bit free-run timer ch.0 external clock input pin
18
13
-
91
G1
G4
FRCK0_1
80
70
-
48
E11
F11
FRCK0_2
62
52
41
30
L13
L12
IC00_0
16-bit input capture ch.0 input pin of Multi-function
timer 0.
ICxx describes channel number.
22
17
-
95
H3
H4
IC00_1
75
65
54
43
G12
G12
IC00_2
63
53
42
31
L12
K12
IC01_0
21
16
-
94
H2
H3
IC01_1
76
66
55
44
G11
G11
IC01_2
64
54
43
32
K13
K11
IC02_0
20
15
-
93
G3
H2
IC02_1
77
67
56
45
F12
G10
IC02_2
65
55
44
33
K12
J12
IC03_0
19
14
-
92
G2
H1
IC03_1
78
68
-
46
F11
F13
IC03_2
66
56
45
34
J13
J11
RTO00_0
(PPG00_0)
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
24
19
14
97
J2
J2
RTO00_1
(PPG00_1)
86
71
57
49
D13
D13
RTO01_0
(PPG00_0)
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
25
20
15
98
J3
J3
RTO01_1
(PPG00_1)
85
-
-
-
-
E10
RTO02_0
(PPG02_0)
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
26
21
16
99
K1
J4
RTO02_1
(PPG02_1)
84
-
-
-
-
E11
RTO03_0
(PPG02_0)
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
27
22
17
100
K2
K2
RTO03_1
(PPG02_1)
83
-
-
-
-
E12
RTO04_0
(PPG04_0)
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
28
23
18
1
L1
K3
RTO04_1
(PPG04_1)
82
-
-
-
-
E13
RTO05_0
(PPG04_0)
Wave form generator output pin of Multi-function
timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
29
24
19
2
L2
L1
RTO05_1
(PPG04_1)
81
-
-
-
-
F10
Document Number: 002-04918 Rev.*D Page 40 of 160
MB9B160R Series
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
Multi-
function
Timer
1
DTTI1X_0
Input signal controlling wave form generator
outputs RTO10 to RTO15 of Multi-function timer
1.
8
8
8
86
E2
E2
DTTI1X_1
55
-
-
-
-
L10
FRCK1_0
16-bit free-run timer ch.1 external clock input pin
96
81
66
59
A9
D9
FRCK1_1
50
45
35
23
L9
L8
IC10_0
16-bit input capture ch.1 input pin of Multi-function
timer 1.
ICxx describes channel number.
95
80
65
58
A10
B10
IC10_1
54
-
-
-
-
M10
IC11_0
94
79
64
57
B10
A11
IC11_1
53
-
-
-
-
K9
IC12_0
93
78
63
56
B11
C10
IC12_1
52
-
-
-
-
L9
IC13_0
92
77
62
55
A12
B13
IC13_1
51
-
-
-
-
K8
RTO10_0
(PPG10_0)
Wave form generator output pin of Multi-function
timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
2
2
2
80
C1
C1
RTO10_1
(PPG10_1)
32
27
-
5
N2
N2
RTO11_0
(PPG10_0)
Wave form generator output pin of Multi-function
timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
3
3
3
81
C2
C2
RTO11_1
(PPG10_1)
33
28
-
6
N3
L2
RTO12_0
(PPG12_0)
Wave form generator output pin of Multi-function
timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
4
4
4
82
C3
D1
RTO12_1
(PPG12_1)
34
29
-
7
M3
N3
RTO13_0
(PPG12_0)
Wave form generator output pin of Multi-function
timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
5
5
5
83
D1
D2
RTO13_1
(PPG12_1)
35
30
-
8
L3
M3
RTO14_0
(PPG14_0)
Wave form generator output pin of Multi-function
timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
6
6
6
84
D2
D3
RTO14_1
(PPG14_1)
36
31
21
9
M4
L4
RTO15_0
(PPG14_0)
Wave form generator output pin of Multi-function
timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
7
7
7
85
E1
E1
RTO15_1
(PPG14_1)
37
32
22
10
L5
K5
Quadrature
Position/
Revolution
Counter
0
AIN0_0
QPRC ch.0 AIN input pin
24
19
14
97
J2
J2
AIN0_1
51
-
-
-
-
K8
AIN0_2
2
2
2
80
C1
C1
BIN0_0
QPRC ch.0 BIN input pin
25
20
15
98
J3
J3
BIN0_1
52
-
-
-
-
L9
BIN0_2
3
3
3
81
C2
C2
ZIN0_0
QPRC ch.0 ZIN input pin
26
21
16
99
K1
J4
ZIN0_1
53
-
-
-
-
K9
ZIN0_2
4
4
4
82
C3
D1
Quadrature
Position/
Revolution
Counter
1
AIN1_0
QPRC ch.1 AIN input pin
10
-
-
-
-
E4
AIN1_1
89
74
-
52
C12
C12
AIN1_2
48
43
33
21
L8
K7
BIN1_0
QPRC ch.1 BIN input pin
11
-
-
-
-
F1
BIN1_1
88
73
-
51
C13
D11
BIN1_2
49
44
34
22
M9
M8
ZIN1_0
QPRC ch.1 ZIN input pin
12
-
-
-
-
F2
ZIN1_1
87
72
-
50
D12
D12
ZIN1_2
50
45
35
23
L9
L8
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MB9B160R Series
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
Real-time clock
RTCCO_0
0.5 seconds pulse output pin of Real-time clock
115
95
75
73
B4
B4
RTCCO_1
64
54
43
32
K13
K11
RTCCO_2
23
18
13
96
J1
J1
SUBOUT_0
Sub clock output pin
115
95
75
73
B4
B4
SUBOUT_1
64
54
43
32
K13
K11
SUBOUT_2
23
18
13
96
J1
J1
Low-Power
Consumption
Mode
WKUP0
Deep standby mode return signal input pin 0
116
96
76
74
B3
B3
WKUP1
Deep standby mode return signal input pin 1
14
9
9
87
E3
F4
WKUP2
Deep standby mode return signal input pin 2
50
45
35
23
L9
L8
WKUP3
Deep standby mode return signal input pin 3
69
59
48
37
H12
H11
DAC
DA0
D/A converter ch.0 analog output pin
36
31
21
9
M4
L4
DA1
D/A converter ch.1 analog output pin
37
32
22
10
L5
K5
VBAT
VREGCTL
On-board regulator control pin
41
36
26
14
L6
L6
VWAKEUP
The return signal input pin from a hibernation
state
42
37
27
15
M7
K6
SD I/F
S_CLK_0
SD memory card interface
SD memory card clock output pin
92
77
62
55
A12
B13
S_CMD_0
SD memory card interface
SD memory card command output
93
78
63
56
B11
C10
S_DATA1_0
SD memory card interface
SD memory card data bus
94
79
64
57
B10
A11
S_DATA0_0
95
80
65
58
A10
B10
S_DATA3_0
96
81
66
59
A9
D9
S_DATA2_0
97
82
67
60
B9
C9
S_CD_0
SD memory card interface
SD memory card detection pin
113
93
73
71
C5
B5
S_WP_0
SD memory card interface
SD memory card write protection
114
94
74
72
B5
C4
Reset
INITX
External Reset Input pin.
A reset is valid when INITX = "L".
38
33
23
11
M6
N4
Mode
MD1
Mode 1 pin.
During serial programming to Flash memory,
MD1 = "L" must be input.
56
46
36
24
M10
N10
MD0
Mode 0 pin.
During normal operation, MD0 = "L" must be
input. During serial programming to Flash
memory, MD0 = "H" must be input.
57
47
37
25
M11
M11
Power
VCC
Power supply Pin
1
1
1
79
B1
B1
31
26
-
4
M1
M1
46
41
31
19
M8
M9
61
51
-
29
M13
M13
91
76
61
54
B13
A12
117
97
77
75
A4
A4
Document Number: 002-04918 Rev.*D Page 42 of 160
MB9B160R Series
Pin
function
Pin name
Function description
Pin No
LQFP
120
LQFP
100
LQFP
80
QFP
100
BGA
112
BGA
144
GND
VSS
GND Pin
107
92
-
70
A5
A7
30
25
20
3
N1
N1
45
40
30
18
N10
N9
60
50
40
28
N13
N13
90
75
60
53
A13
A13
120
100
80
78
A1
A1
-
-
-
-
A7
A5
-
-
-
-
B2
A8
-
-
-
-
B12
A10
-
-
-
-
C11
B2
-
-
-
-
H1
B11
-
-
-
-
N4
B12
-
-
-
-
M5
C3
-
-
-
-
N7
C11
-
-
-
-
L11
C13
-
-
-
-
A11
D4
-
-
-
-
M12
D10
-
-
-
-
M2
K1
-
-
-
-
-
K4
-
-
-
-
-
K10
-
-
-
-
-
L3
-
-
-
-
-
L5
-
-
-
-
-
L11
-
-
-
-
-
L13
-
-
-
-
-
M2
GND
VSS
GND Pin
-
-
-
-
-
M4
-
-
-
-
-
M6
-
-
-
-
-
M7
-
-
-
-
-
M12
-
-
-
-
-
N6
Clock
X0
Main clock (oscillation) input pin
58
48
38
26
N11
N11
X1
Main clock (oscillation) I/O pin
59
49
39
27
N12
N12
X0A
Sub clock (oscillation) input pin
39
34
24
12
N5
N5
X1A
Sub clock (oscillation) I/O pin
40
35
25
13
N6
M5
CROUT_0
Built-in high-speed CR-osc clock output port
87
72
58
50
D12
D12
CROUT_1
113
93
73
71
C5
B5
ADC
Power
AVCC
A/D converter and D/A converter
analog power supply pin
70
60
49
38
H13
K13
AVRL
A/D converter analog reference voltage input pin
72
62
51
40
F13
H13
AVRH
A/D converter analog reference voltage input pin
73
63
52
41
E13
G13
VBAT
Power
VBAT
VBAT power supply pin.
Backup power supply (battery etc.) and system
power supply.
43
38
28
16
N8
N7
ADC
GND
AVSS
A/D converter and D/A converter
GND pin
71
61
50
39
G13
J13
C pin
C
Power supply stabilization capacity pin
44
39
29
17
N9
N8
Note:
− While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-04918 Rev.*D Page 43 of 160
MB9B160R Series
5. I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
When the main oscillation is selected.
• Oscillation feedback resistor
: Approximately 1 MΩ
• With Standby mode control
When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
B
• CMOS level hysteresis input
• Pull-up resistor
: Approximately 50 kΩ
P-ch
P-ch
N-ch
R
R
P-ch
P-ch
N-ch
X0
X1
Pull-up
resistor
Feedback
resistor
Pull-up
resistor
Standby mode control
Digital input
Standby mode control
Digital output
Digital output
Clock input
Digital input
Standby mode control
Pull-up resistor control
Pull-up resistor control
Digital output
Digital output
Pull-up resistor
Digital input
Document Number: 002-04918 Rev.*D Page 44 of 160
MB9B160R Series
Type
Circuit
Remarks
C
• Open drain output
• CMOS level hysteresis input
E
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
F
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
N-ch
P-chP-ch
N-ch
R
P-chP-ch
N-ch
R
Digital input
Digital output
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-04918 Rev.*D Page 45 of 160
MB9B160R Series
Type
Circuit
Remarks
G
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -12 mA, IOL = 12 mA
H
• CMOS level output
• CMOS level hysteresis input
• With standby mode control
• IOH = -20.5 mA, IOL = 18.5 mA
P-chP-ch
N-ch
R
P-ch
N-ch
R
Standby mode
control
Pull-up resistor
control
Digital input
Digital output
Digital output
Digital output
Digital output
Digital input
Standby mode
Control
Document Number: 002-04918 Rev.*D Page 46 of 160
MB9B160R Series
Type
Circuit
Remarks
I
• CMOS level output
• CMOS level hysteresis input
• 5V tolerant
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• Available to control of PZR registers.
J
CMOS level hysteresis input
L
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -8 mA, IOL = 8 mA
P-chP-ch
N-ch
R
P-chP-ch
N-ch
R
Standby mode control
Pull-up resistor
control
Digital input
Digital output
Digital output
Mode input
Digital output
Digital output
Pull-up resistor
control
Digital input
Standby mode
control
Document Number: 002-04918 Rev.*D Page 47 of 160
MB9B160R Series
Type
Circuit
Remarks
M
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -8 mA, IOL = 8 mA
N
・ CMOS level output
・ CMOS level hysteresis input
・ 5V tolerant
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA (GPIO)
・ IOL = 20 mA (Fast mode Plus)
・ Available to control of PZR
register (pseudo-open drain
control)
・ For PZR registers, refer to GPIO
in the FM4 Family Peripheral
Manual Main Part (002-04856).
・ When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off.
P-chP-ch
N-ch
R
P-ch
N-ch
R
P-ch
N-ch
Digital output
Digital output
Fast mode
control
Digital input
Standby mode
control
Pull-up resistor
control
Digital output
Digital output
Pull-up resistor
control
Digital input
Standby mode
control
Analog input
Input control
Document Number: 002-04918 Rev.*D Page 48 of 160
MB9B160R Series
Type
Circuit
Remarks
O
・ CMOS level output
・ CMOS level hysteresis input
・ 5 V tolerant
・ Pull-up resistor control
・ Pull-up resistor:
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
・ Available to control of PZR
register (pseudo-open drain
control)
・ For PZR registers, refer to GPIO
in the “FM4 Family Peripheral
Manual Main Part (002-04856)”.
・ For I/O setting, refer to VBAT
Domain in the FM4 Family
Peripheral Manual Main Part
(002-04856).
P
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• For I/O setting, refer to VBAT
Domain in the Peripheral Manual
P-ch
P-ch
N-ch
R
Digital output
Digital output
Digital input
Pull-up resistor
control
P-ch
P-ch
N-ch
R
Digital output
Digital output
Digital input
Pull-up resistor
control
Standby mode
control
OSC
X0A
Document Number: 002-04918 Rev.*D Page 49 of 160
MB9B160R Series
Type
Circuit
Remarks
Q
It is possible to select the sub
oscillation / GPIO function
When the sub oscillation is selected.
• Oscillation feedback resistor
: Approximately 10 MΩ
• With Standby mode control
• When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• For I/O setting, refer to VBAT
Domain in the Peripheral Manual
R
• CMOS level output
• CMOS level hysteresis input
• Analog output
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -12 mA, IOL = 12 mA
(4.5 V to 5.5 V)
• IOH = -8 mA, IOL = 8 mA
(2.7 V to 4.5 V)
P-ch
P-ch
N-ch
R
RX
P-ch
N-ch
R
P-ch
X1A
Digital output
Digital output
Digital input
Pull-up resistor
control
Standby mode
control
OSC
Standby mode
control
Clock input
Pull-up resistor
control
Digital input
Standby mode
control
Analog output
Digital output
Digital output
Document Number: 002-04918 Rev.*D Page 50 of 160
MB9B160R Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-04918 Rev.*D Page 51 of 160
MB9B160R Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress’ recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-04918 Rev.*D Page 52 of 160
MB9B160R Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of
1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04918 Rev.*D Page 53 of 160
MB9B160R Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this
device.
Power supply pins
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed
operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the
fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard
VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power
supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as
possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
• Surface mount type
Size: More than 3.2 mm × 1.5 mm
Load capacitance: Approximately 6 pF to 7 pF
• Lead type
Load capacitance: Approximately 6 pF to 7 pF
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
X1(PE3), X1A (P47)
Can be used as
general-purpose
I/O ports.
Set as External
clock input
Document Number: 002-04918 Rev.*D Page 54 of 160
MB9B160R Series
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with
power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time. The device operates normally after all power on.
VBAT only Power-on is possible when VBAT and VCC turns Power-on and Hibernation control is setting and then VCC turns
Power-off. About Hibernation control, see Chapter 7-2: VBAT Domain(A) in FM4 Family Peripheral Manual Main Part(002-04856).
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on :
VBAT → VCC
VCC → AVCC → AVRH
Turning off :
AVRH → AVCC → VCC
VCC → VBAT
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash products and
MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash products and MASK products are different because chip layout and
memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Device
C
VSS
CS
GND
Document Number: 002-04918 Rev.*D Page 55 of 160
MB9B160R Series
Pull-Up function of 5V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.
Adjoining wiring on circuit board
If wiring of the crystal oscillation circuit X1A adjoins and also runs in parallel with the wiring of P48/VREGCTL, there is a possibility
that the oscillation erroneously counts because X1A has noise with the change of P48/VREGCTL. Keep as much distance as
possible between both wirings and insert the ground pattern between them in order to avoid this possibility.
Handling when using debug pins
When debug pins(TDO/TMS/TDI/TCK/TRSTX or SWO/SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set
them as output, do not set them as input.
P47/
X1A P48/
VREGCTL
Ground
P46/
X0A P49/
VWAKEUP
Not allowed to run
both wirings in parallel
Insert the ground pattern
Device
Document Number: 002-04918 Rev.*D Page 56 of 160
MB9B160R Series
8. Block Diagram
Cortex-M4　Core
@160 MHz(Max)
MainFlash I/F
Clock Reset
Generator
Dual-Timer
Watchdog Timer
(Hardware)
DMAC
8ch.
Watch Counter
Unit 0
CSV
External Interrupt
Controller
16pin + NMI
Power-On
Reset
SRAM0
32/48/64 Kbytes
AHB-APB Bridge : APB1 (Max 160 MHz)
SRAM1
16/24/32 Kbytes
AHB-APB Bridge:
APB0(Max 80 MHz)
I
D
Sys
CLK
MB9BF166M/N/R, F167M/N/R, F168M/N/R
AHB-APB Bridge : APB2 (Max 80 MHz)
NVIC
Watchdog Timer
(Software)
Security
Unit 1
TRSTX,TCK,
TDI,TMS
TRACEDx,
TRACECLK
X0
AVCC,
AVSS,
AVRH
ANxx
TIOAx
TIOBx
C
TDO
X1
X0A
X1A
SCKx
SINx
SOTx
INTx
NMIX
P0x,
P1x,
.
.
.
PEx
INITX
MODE-Ctrl
IRQ-Monitor
MD0,
MD1
Regulator
CRC Accelerator
AHB-AHB Bridge
ADTGx
RTS4
CTS4
MADx
MADATAx
MainFlash
1 Mbytes/
768 Kbytes/
512 Kbytes
Multi-function Serial I/F
8ch.
HW flow control(ch.4)
External Bus I/F
GPIO
PIN-Function-Ctrl
LVD
Multi-layer AHB (Max 160 MHz)
TPIU* ROM
Table
ETM*SWJ-DP
Main
Osc PLL CR
100 kHz
LVD Ctrl
Base Timer
16-bit 16ch./
32-bit 8ch.
Peripheral Clock Gating
Low-speed CR Prescaler
RTCCO,
SUBOUT
Deep Standby Ctrl WKUPx
16-bit Free-run Timer
3ch.
16-bit Output Compare
6ch.
16-bit Input Capture
4ch.
A/D Activation Compare
6ch.
16-bit PPG
3ch.
DTTI0X
FRCK0
QPRC
2ch.
BINx
ZINx
IC0x
RTO0x
AINx
12-bit A/D Converter
Multi-function Timer × 2
MCSXx,MDQMx,
MOEX,MWEX,
MALE,MRDY,
MNALE,MNCLE,
MNWEX,MNREX,
MCLKOUT,MSDWEX,
MSDCLK,MSDCKE,
MRASX,MCASX
Waveform Generator
3ch.
MPUFPU
12-bit D/A Converter
2units
SRAM2
16/24/32 Kbytes
WorkFlash
32 Kbytes
WorkFlash I/F
Trace Buffer
(16 Kbytes)
DSTC
SD-CARD I/F S_CLK,S_CMD
S_DATAx
S_CD,S_WP
VREGCTL
VWAKEUP
Unit 2
DAx
Real-Time Clock
Port Ctrl.
Sub
Osc
VBAT Domain
VBAT Domain CR
4 MHz
CROUT
Source Clock
*: For the MB9BF166M, MB9BF167M and MB9BF168M, ETM is not available.
Document Number: 002-04918 Rev.*D Page 57 of 160
MB9B160R Series
9. Memory Size
See "Memory size" in "Product Lineup" to confirm the memory size.
10. Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
0x4007_0000
0x4006_F000
GPIO
0x4006_E000
SD-Card I/F
0xFFFF_FFFF 0x4006_2000
0xE010_0000 0x4006_1000 DSTC
0x4006_0000 DMAC
0xE000_0000
0x4004_0000
0x4003_F000 EXT-bus I/F
0x4003_C800
0x4003_C100 Peripheral Clock Gating
0x4003_C000 Low Speed CR Prescaler
0x6000_0000 0x4003_B000 RTC/Port Ctrl
0x4003_A000 Watch Counter
0x4003_9000 CRC
0x4400_0000 0x4003_8000 MFS
Reserved
0x4200_0000 0x4003_6000
0x4003_5000 LVD/DS mode
0x4003_4000
Reserved
0x4000_0000 0x4003_3000 D/AC
0x4003_2000
Reserved
0x4003_1000 Int-Req.Read
0x2400_0000 0x4003_0000 EXTI
0x4002_F000 Reserved
0x2200_0000 0x4002_E000 CR Trim
0x4002_8000
0x2010_0000 0x4002_7000 A/DC
0x200E_0000
WorkFlash I/F 0x4002_6000 QPRC
0x200C_0000 WorkFlash 0x4002_5000 Base Timer
0x4002_4000 PPG
0x2004_8000
0x2004_0000 SRAM2 0x4002_2000
0x2003_8000 SRAM1 0x4002_1000 MFT Unit1
0x2000_0000 Reserved 0x4002_0000 MFT Unit0
0x1FFF_0000 SRAM0
0x0050_0000 Reserved 0x4001_6000
0x0040_0000 Security/CR Trim 0x4001_5000 Dual Timer
0x4001_3000
0x4001_2000 SW WDT
0x0000_0000 0x4001_1000 HW WDT
0x4001_0000 Clock/Reset
0x4000_1000
0x4000_0000 MainFlash I/F
Reserved
32 Mbytes
Bit band alias
Reserved
Reserved
Reserved
Reserved
Cortex-M4 Private
Peripherals
Reserved
Reserved
External Device
Area
Reserved
Reserved
Reserved
Reserved
32 Mbytes
Bit band alias
Reserved
See "Memory Map (2)"
for the memory size
details.
MainFlash
Reserved
Reserved
Peripherals
Document Number: 002-04918 Rev.*D Page 58 of 160
MB9B160R Series
Memory Map (2)
MB9BF168M/N/R MB9BF167M/N/R MB9BF166M/N/R
0x2008_0000 0x2008_0000 0x2008_0000
0x200C_8000 0x200C_8000 0x200C_8000
0x200C_0000 0x200C_0000 0x200C_0000
0x2004_8000 0x2004_6000 0x2004_4000
0x2004_0000 0x2004_0000 0x2004_0000
0x2003_C000
0x2003_A000
0x2003_8000
0x2000_0000 0x2000_0000 0x2000_0000
0x1FFF_8000
0x1FFF_4000
0x1FFF_0000
0x0050_0000 0x0050_0000 0x0050_0000
0x0040_2000
CR trimming 0x0040_2000 CR trimming 0x0040_2000 CR trimming
0x0040_0000
Security 0x0040_0000 Security 0x0040_0000 Security
0x0010_0000
0x000C_0000
0x0008_0000
0x0000_0000 0x0000_0000 0x0000_0000
SRAM2
16 Kbytes
Reserved
SRAM0
32 Kbytes
Reserved
Reserved
SRAM1
24 Kbytes
Reserved
SRAM1
16 Kbytes
Reserved
Reserved
MainFlash
512 Kbytes
Reserved
MainFlash
768 Kbytes
Reserved
Reserved
Reserved
SRAM0
48 Kbytes
Reserved
WorkFlash
32 Kbytes
WorkFlash
32 Kbytes
Reserved
Reserved
WorkFlash
32 Kbytes
SRAM2
24 Kbytes
MainFlash
1 Mbytes
Reserved
Reserved
SRAM0
64 Kbytes
SRAM1
32 Kbytes
SRAM2
32 Kbytes
Document Number: 002-04918 Rev.*D Page 59 of 160
MB9B160R Series
Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000
0x4000_0FFF
AHB
MainFlash I/F register
0x4000_1000
0x4000_FFFF
Reserved
0x4001_0000
0x4001_0FFF
APB0
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
Software Watchdog timer
0x4001_3000
0x4001_4FFF
Reserved
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
APB1
Multi-function timer unit0
0x4002_1000
0x4002_1FFF
Multi-function timer unit1
0x4002_2000
0x4003_FFFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
Base Timer
0x4002_6000
0x4002_6FFF
Quadrature Position/Revolution Counter
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Internal CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
APB2
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_4FFF
Reserved
0x4003_3000
0x4003_3FFF
D/A Converter
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_57FF
Low Voltage Detector
0x4003_5800
0x4003_5FFF
Deep standby mode Controller
0x4003_6000
0x4003_7FFF
Reserved
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_BFFF
RTC/Port Ctrl
0x4003_C000
0x4003_C0FF
Low-speed CR Prescaler
0x4003_C100
0x4003_C7FF
Peripheral Clock Gating
0x4003_C800
0x4003_EFFF
Reserved
0x4003_F000
0x4003_FFFF
External Memory interface
0x4004_0000
0x4005_FFFF
AHB
Reserved
0x4006_0000
0x4006_0FFF
DMAC register
0x4006_1000
0x4006_3FFF
DSTC register
0x4006_4000
0x4006_DFFF
Reserved
0x4006_E000
0x4006_EFFF
SD-Card I/F
0x4006_F000
0x4006_FFFF
GPIO
0x4006_7000
0x41FF_FFFF
Reserved
0x200E_0000
0x200E_FFFF
WorkFlash I/F register
Document Number: 002-04918 Rev.*D Page 60 of 160
MB9B160R Series
11. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX = 0
This is the period when the INITX pin is the "L" level.
INITX = 1
This is the period when the INITX pin is the "H" level.
SPL = 0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".
SPL = 1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
Setting prohibition
Prohibition of a setting by specification limitation.
Document Number: 002-04918 Rev.*D Page 61 of 160
MB9B160R Series
List of Pin Status
Pin status type
Function
group
Power-on
reset or
low-voltage
detection
state
INITX
input
state
Device
internal
reset
state
Run mode
or SLEEP
mode state
TIMER mode,
RTC mode, or
STOP mode state
Deep standby RTC
mode or Deep standby
STOP mode state
Return from
Deep
standby
mode state
Power
supply
unstable
Power supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power
supply
stable
‐
INITX = 0
INITX = 1
INITX = 1
INITX = 1
INITX = 1
INITX = 1
‐
‐
‐
‐
SPL = 0
SPL = 1
SPL = 0
SPL = 1
-
A
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Main crystal
oscillator
input pin/
External main
clock input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
B
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
External main
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Main crystal
oscillator
output pin
Hi-Z /
Internal
input fixed
at "0"/
or Input
enable
Hi-Z /
Internal
input
fixed
at "0"
Hi-Z /
Internal
input
fixed
at "0"
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at "0"
C
INITX
input pin
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
D
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
E
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
enabled
GPIO
selected
Hi-Z /
Input
enabled
GPIO
selected
Document Number: 002-04918 Rev.*D Page 62 of 160
MB9B160R Series
Pin status type
Function
group
Power-on
reset or
low-voltage
detection
state
INITX
input
state
Device
internal
reset
state
Run mode
or SLEEP
mode state
TIMER mode,
RTC mode, or
STOP mode state
Deep standby RTC
mode or Deep standby
STOP mode state
Return from
Deep
standby
mode state
Power
supply
unstable
Power supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power
supply
stable
‐
INITX = 0
INITX = 1
INITX = 1
INITX = 1
INITX = 1
INITX = 1
‐
‐
‐
‐
SPL = 0
SPL = 1
SPL = 0
SPL = 1
-
F
NMIX selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
selected
Resource other
than above
selected
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Maintain
previous
state
G
JTAG
selected
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
H
JTAG
selected
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Resource other
than above
selected
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
GPIO
selected
I
Resource
selected
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
GPIO
selected
J
Analog output
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
*2
*3
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Resource other
than above
selected
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Document Number: 002-04918 Rev.*D Page 63 of 160
MB9B160R Series
Pin status type
Function
group
Power-on
reset or
low-voltage
detection
state
INITX
input
state
Device
internal
reset
state
Run mode
or SLEEP
mode state
TIMER mode,
RTC mode, or
STOP mode state
Deep standby RTC
mode or Deep standby
STOP mode state
Return from
Deep
standby
mode state
Power
supply
unstable
Power supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power
supply
stable
‐
INITX = 0
INITX = 1
INITX = 1
INITX = 1
INITX = 1
INITX = 1
‐
‐
‐
‐
SPL = 0
SPL = 1
SPL = 0
SPL = 1
-
K
External
interrupt
enabled
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Resource other
than above
selected
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
L
Analog input
selected
Hi-Z
Hi-Z /
Internal
input
fixedat
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixedat
"0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Resource other
than above
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
GPIO
selected
M
Analog input
selected
Hi-Z
Hi-Z /
Internal
input
fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
External
interrupt
enabled
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Resource other
than above
selected
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Document Number: 002-04918 Rev.*D Page 64 of 160
MB9B160R Series
Pin status type
Function
group
Power-on
reset or
low-voltage
detection
state
INITX
input
state
Device
internal
reset
state
Run mode
or SLEEP
mode state
TIMER mode,
RTC mode, or
STOP mode state
Deep standby RTC
mode or Deep standby
STOP mode state
Return from
Deep
standby
mode state
Power
supply
unstable
Power supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power
supply
stable
‐
INITX = 0
INITX = 1
INITX = 1
INITX = 1
INITX = 1
INITX = 1
‐
‐
‐
‐
SPL = 0
SPL = 1
SPL = 0
SPL = 1
-
N
Analog input
selected
Hi-Z
Hi-Z /
Internal
input
fixed
at"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Trace selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Trace
output
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Resource other
than above
selected
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
O
Analog input
selected
Hi-Z
Hi-Z /
Internal
input
fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Trace selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Trace
output
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
External
interrupt
enabled
selected
Maintain
previous
state
Resource other
than above
selected
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Document Number: 002-04918 Rev.*D Page 65 of 160
MB9B160R Series
Pin status type
Function
group
Power-on
reset or
low-voltage
detection
state
INITX
input
state
Device
internal
reset
state
Run mode
or SLEEP
mode state
TIMER mode,
RTC mode, or
STOP mode state
Deep standby RTC
mode or Deep standby
STOP mode state
Return from
Deep
standby
mode state
Power
supply
unstable
Power supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power
supply
stable
‐
INITX = 0
INITX = 1
INITX = 1
INITX = 1
INITX = 1
INITX = 1
‐
‐
‐
‐
SPL = 0
SPL = 1
SPL = 0
SPL = 1
-
P
Analog input
selected
Hi-Z
Hi-Z /
Internal
input
fixedat
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixedat
"0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
WKUP
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP input
enabled
GPIO
selected
Resource other
than above
selected
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Q
WKUP
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
WKUP input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
selected
External
interrupt
enabled
selected
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Resource other
than above
selected
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
R
GPIO
selected
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
GPIO
selected
*1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, STOP mode, Deep standby RTC mode, and Deep
standby STOP mode.
*2: Maintain previous state at timer mode. GPIO selected Internal input fixed at "0" at RTC mode, STOP mode.
*3: Maintain previous state at timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, STOP mode.
Document Number: 002-04918 Rev.*D Page 66 of 160
MB9B160R Series
List of VBAT Domain Pin Status
VBAT pin status type
Function
group
Power-o
n reset*1
INITX
input
state
Device
internal
reset
state
Run
mode or
SLEEP
mode
state
TIMER mode,
RTC mode, or
STOP mode state
Deep standby
RTC mode or Deep
standby STOP
mode state
Return
from
Deep
standby
mode
state
VBAT
RTC
mode
state
Return
from
VBAT
RTC
mode
state
Power
supply
unstable
Power supply
stable
Power
supply
stable
Power supply stable
Power supply stable
Power
supply
stable
Power
supply
stable
Power
supply
stable
‐
INITX = 0
INITX = 1
INITX = 1
INITX = 1
INITX = 1
INITX = 1
-
-
‐
‐
‐
‐
SPL = 0
SPL = 1
SPL = 0
SPL = 1
-
-
-
S
GPIO
selected
Setting
disabled
Maintain
Previous
state
Maintain
Previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
Previous
state
Maintain
Previous
state
Maintain
Previous
state
Maintain
Previous
state
Setting
prohibition
-
Sub crystal
oscillator
input pin /
External
sub clock
input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Maintain
previous
state
Maintain
previous
state
T
GPIO
selected
Setting
disabled
Maintain
Previous
state
Maintain
Previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
Previous
state
Maintain
Previous
state
Maintain
Previous
state
Maintain
Previous
state
Setting
prohibition
-
External
sub clock
input
selected
Setting
disabled
Maintain
Previous
state
Maintain
Previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
Previous
state
Maintain
previous
state
Maintain
Previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Sub crystal
oscillator
output pin
Hi-Z /
Internal
input fixed
at "0"/
or Input
enable
Maintain
Previous
state
Maintain
Previous
state
Maintain
previous
state
Maintain
previous
state/When
oscillation
stops,
Hi-Z*2
Maintain
previous
state/When
oscillation
stops,
Hi-Z*2
Maintain
previous
state/When
oscillation
stops,
Hi-Z*2
Maintain
previous
state/When
oscillation
stops,
Hi-Z*2
Maintain
Previous
state
Maintain
previous
state
Maintain
previous
state
U
Resource
selected
Hi-Z
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected
*1: When VBAT and VCC power on.
*2: When the SOSCNTL bit in the WTOSCCNT register is 0, the sub crystal oscillator output pin is maintained in the previous
state.
When the SOSCNTL bit in the WTOSCCNT register is 1, oscillation is stopped at Stop mode and Deep Standby Stop
Document Number: 002-04918 Rev.*D Page 67 of 160
MB9B160R Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
Power supply voltage *1, *2
VCC
VSS - 0.5
VSS + 6.5
V
Power supply voltage (VBAT) *1 ,*3
VBAT
VSS - 0.5
VSS + 6.5
V
Analog power supply voltage *1 ,*4
AVCC
VSS - 0.5
VSS + 6.5
V
Analog reference voltage *1 ,*4
AVRH
VSS - 0.5
VSS + 6.5
V
Input voltage *1
VI
VSS - 0.5
VCC + 0.5
(≤ 6.5V)
V
VSS - 0.5
VSS + 6.5
V
5V tolerant
Analog pin input voltage *1
VIA
VSS - 0.5
AVCC + 0.5
(≤ 6.5V)
V
Output voltage *1
VO
VSS - 0.5
VCC + 0.5
(≤ 6.5V)
V
"L" level maximum output current *5
IOL
-
10
mA
4mA type
20
mA
8mA type
20
mA
12mA type
22.4
mA
I2C Fm+
"L" level average output current *6
IOLAV
-
4
mA
4mA type
8
mA
8mA type
12
mA
12mA type
20
mA
I2C Fm+
"L" level total maximum output current
∑IOL
-
100
mA
"L" level total maximum output current *7
∑IOLAV
-
50
mA
"H" level maximum output current *5
IOH
-
- 10
mA
4mA type
20
mA
8mA type
- 20
mA
12mA type
"H" level average output current *6
IOHAV
-
- 4
mA
4mA type
8
mA
8mA type
- 12
mA
12mA type
"H" level total maximum output current
∑IOH
-
- 100
mA
"H" level total average output current *7
∑IOHAV
-
- 50
mA
Storage temperature
TSTG
- 55
+ 150
°C
*1: These parameters are based on the condition that VSS = AVSS = 0.0V.
*2: VCC must not drop below VSS - 0.5V.
*3: VBAT must not drop below VSS - 0.5V.
*4: Ensure that the voltage does not exceed VCC + 0.5V, for example, when the power is turned on.
*5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*6: The average output current is defined as the average current value flowing through any one of the corresponding pins for a
100ms period.
*7: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100ms.
WARNING:
− Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-04918 Rev.*D Page 68 of 160
MB9B160R Series
12.2 Recommended Operating Conditions
Parameter
Symbol
Conditions
Value
Unit
Remarks
Min
Max
Power supply voltage
VCC
-
2.7*3
5.5
V
Power supply voltage (VBAT)
VBAT
-
2.7
5.5
V
Analog power supply voltage
AVCC
-
2.7
5.5
V
AVCC = VCC
Analog reference voltage
AVRH
-
*2
AVCC
V
Operating
temperature
Junction temperature
Tj
-
- 40
+ 125
°C
Ambient temperature
TA
-
- 40
*1
°C
*1: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the junction
temperature (Tj).
The calculation formula of the ambient temperature (TA) is shown below.
TA(Max) = Tj(Max) - Pd(Max) × θja
Pd: Power dissipation (W)
θja: Package thermal resistance (°C/W)
Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH))
IOL: "L" level output current
IOH: "H" level output current
VOL: "L" level output voltage
VOH: "H" level output voltage
*2: The minimum value of Analog reference voltage depends on the value of compare clock cycle (Tcck). See 12.5. 12-bit A/D
Converter” for the details.
*3: Between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage, instruction execution
and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible to
operate.
Package thermal resistance and maximum permissible power for each package are shown below.
The operation is guaranteed maximum permissible power or less for semiconductor devices.
Table for package thermal resistance and maximum permissible power
Package
Printed circuit board
Thermal resistance
θja (°C/W)
Maximum permissible power
(mW)
TA = +85°C
TA = +105°C
LQH080
(0.5mm pitch)
Single-layered both sides
60
667
333
4 layers
39
1026
513
LQJ080
(0.65mm pitch)
Single-layered both sides
58
690
335
4 layers
38
1053
526
LQI100
(0.5mm pitch)
Single-layered both sides
57
702
351
4 layers
38
1053
526
PQH100
(0.65mm pitch)
Single-layered both sides
48
833
417
4 layers
34
1177
588
LQM120
(0.5mm pitch)
Single-layered both sides
62
645
323
4 layers
43
930
465
LDC112
(0.5mm pitch)
Single-layered both sides
60
667
333
4 layers
40
1000
500
LDC144
(0.5mm pitch)
Single-layered both sides
55
727
364
4 layers
40
1000
500
WARNING:
− The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-04918 Rev.*D Page 69 of 160
MB9B160R Series
Calculation method of power dissipation (Pd)
The power dissipation is shown in the following formula.
Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH))
IOL: "L" level output current
IOH: "H" level output current
VOL: "L" level output voltage
VOH: "H" level output voltage
ICC is a current consumed in device.
It can be analyzed as follows.
ICC = ICC(INT) + ΣICC(IO)
ICC(INT): Current consumed in internal logic and memory, etc. through regulator
ΣICC(IO): Sum of current (I/O switching current) consumed in output pin
For ICC (INT), it can be anticipated by 12.3.1 “Current Rating" in 12.3. DC Characteristics" (This rating value does not include ICC (IO)
for a value at pin fixed).
For Icc (IO), it depends on system used by customers.
The calculation formula is shown below.
ICC(IO) = (CINT + CEXT) × VCC × fsw
CINT: Pin internal load capacitance
CEXT: External load capacitance of output pin
fSW: Pin switching frequency
Parameter
Symbol
Conditions
Capacitance value
Pin internal load capacitance
CINT
4mA type
1.93pF
8mA type
3.45pF
12mA type
3.42pF
Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself.
1. Measure current value ICC (Typ) at normal temperature (+25°C).
2. Add maximum leak current value ICC (leak_max) at operating on a value in (1).
ICC(Max) = ICC(Typ) + ICC(leak_max)
Parameter
Symbol
Conditions
Current value
Maximum leak current at
operating
ICC(leak_max)
Tj = +125°C
45.5mA
Tj = +105°C
26.8mA
Tj = +85°C
16.2mA
Document Number: 002-04918 Rev.*D Page 70 of 160
MB9B160R Series
Current explanation diagram
A
V
・・・
・・・
・・・
V
A
A
Regulator
Logic
Flash
RAM
ICC
ICC(INT)
ΣICC(IO)
IOL
VOL
VOH
IOH
ICC(IO)
Chip
VCC
CEXT
Pd = VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH))
ICC = ICC(INT)＋ΣICC(IO)
Document Number: 002-04918 Rev.*D Page 71 of 160
MB9B160R Series
12.3 DC Characteristics
12.3.1 Current Rating
Table 12-1. Typical and maximum current consumption in Normal operation(PLL), code running from Flash memory (Flash
accelerator mode and trace buffer function enabled)
Parameter
Symbol
Pin
name
Conditions
Frequency*4
Value
Unit
Remarks
Typ*1
Max*2
Power supply
current
ICC
VCC
Normal operation*5,*6
(PLL)
160MHz
54
103
mA
*3
When all peripheral
clocks are ON
144MHz
49
98
120MHz
41
90
100MHz
35
84
80MHz
28
77
60MHz
22
71
40MHz
16
64
20MHz
8.9
58
8MHz
5.1
54
4MHz
3.8
53
160MHz
34
83
mA
*3
When all peripheral
clocks are OFF
144MHz
31
80
120MHz
26
75
100MHz
22
71
80MHz
18
67
60MHz
14
63
40MHz
10
59
20MHz
6.2
55
8MHz
3.8
53
4MHz
3.1
52
Table 12-2. Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from
Flash memory (Flash accelerator mode and trace buffer function disabled)
Parameter
Symbol
Pin
name
Conditions
Frequency*7
Value
Unit
Remarks
Typ*1
Max*2
Power supply
current
ICC
VCC
Normal operation*8
(PLL)
160MHz
74
126
mA
*3
When all peripheral
clocks are ON
144MHz
68
120
120MHz
59
112
100MHz
52
104
80MHz
44
97
60MHz
36
89
40MHz
27
79
20MHz
17
67
8MHz
8.3
58
4MHz
5.4
55
160MHz
51
103
mA
*3
When all peripheral
clocks are OFF
144MHz
47
100
120MHz
42
94
100MHz
37
90
80MHz
33
85
60MHz
28
80
40MHz
21
73
20MHz
13
64
8MHz
6.9
56
4MHz
4.6
54
*1: TA = +25°C, VCC = 3.3V
*2: Tj = +125°C, VCC = 5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK/2
Document Number: 002-04918 Rev.*D Page 72 of 160
MB9B160R Series
*5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1)
*6: Data access is nothing to MainFlash memory
*7: Frequency is a value of HCLK. PCLK0 = PCLK2 = HCLK/2, PCLK1 = HCLK
*8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0)
Table 12-3. Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from
Flash memory (flash 0 wait-cycle mode and read access 0 wait)
Parameter
Symbol
Pin
name
Conditions
Frequency*4
(MHz)
Value
Unit
Remarks
Typ*1
Max*2
Power supply
current
ICC
VCC
Normal
operation*5
(PLL)
72MHz
46
98
mA
*3
When all peripheral
clocks are ON
60MHz
40
92
48MHz
33
85
36MHz
27
78
24MHz
19
70
12MHz
11
61
8MHz
8.5
58
4MHz
5.5
55
72MHz
33
85
mA
*3
When all peripheral
clocks are OFF
60MHz
29
81
48MHz
25
76
36MHz
20
71
24MHz
15
65
12MHz
9.2
59
8MHz
6.9
56
4MHz
4.6
54
*1: TA = +25°C, VCC = 3.3V
*2: Tj = +125°C, VCC = 5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK
*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00)
Document Number: 002-04918 Rev.*D Page 73 of 160
MB9B160R Series
Table 12-4. Typical and maximum current consumption in Normal operation(other than PLL), code with data accessing
running from Flash memory (flash 0 wait-cycle mode and read access 0 wait
Parameter
Symbol
Pin
name
Conditions
Frequency*4
Value
Unit
Remarks
Typ*1
Max*2
Power supply
current
ICC
VCC
Normal
operation*5
(built-in high-speed
CR)
4MHz
3.3
51
mA
*3
When all peripheral
clocks are ON
2.8
51
mA
*3
When all peripheral
clocks are OFF
Normal
operation*5
(sub oscillation)
32kHz
0.64
48
mA
*3
When all peripheral
clocks are ON
0.56
48
mA
*3
When all peripheral
clocks are OFF
Normal
operation*5
(built-in
low-speed CR)
100kHz
0.64
48
mA
*3
When all peripheral
clocks are ON
0.58
48
mA
*3
When all peripheral
clocks are OFF
*1: TA = +25°C, VCC = 3.3V
*2: Tj = +125°C, VCC = 5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK/2
*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000)
Document Number: 002-04918 Rev.*D Page 74 of 160
MB9B160R Series
Table 12-5. Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2
Parameter
Symbol
Pin
name
Conditions
Frequency*4
Value
Unit
Remarks
Typ*1
Max*2
Power supply
current
ICCS
VCC
Sleep operation
(PLL)
160MHz
35
84
mA
*3
When all peripheral
clocks are ON
144MHz
32
81
120MHz
27
76
100MHz
23
72
80MHz
19
68
60MHz
15
64
40MHz
11
60
20MHz
6.5
55
8MHz
4.1
53
4MHz
3.3
52
160MHz
16
65
mA
*3
When all peripheral
clocks are OFF
144MHz
14
63
120MHz
12
61
100MHz
11
60
80MHz
9.0
58
60MHz
7.4
56
40MHz
5.6
54
20MHz
3.9
53
8MHz
2.9
52
4MHz
2.6
51
Table 12-6. Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK
Parameter
Symbol
Pin
name
Conditions
Frequency*5
Value
Unit
Remarks
Typ*1
Max*2
Power supply
current
ICCS
VCC
Sleep operation
(PLL)
72MHz
22
71
mA
*3
When all peripheral
clocks are ON
60MHz
19
68
48MHz
16
64
36MHz
12
61
24MHz
9.0
58
12MHz
5.8
55
8MHz
4.6
54
4MHz
3.6
52
72MHz
9.5
58
mA
*3
When all peripheral
clocks are OFF
60MHz
8.3
57
48MHz
7.1
56
36MHz
5.8
55
24MHz
4.6
53
12MHz
3.5
52
8MHz
3.0
52
4MHz
2.7
51
*1: TA = +25°C, VCC = 3.3V
*2: Tj = +125°C, VCC = 5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK/2
*5: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK
Document Number: 002-04918 Rev.*D Page 75 of 160
MB9B160R Series
Table 12-7. Typical and maximum current consumption in Sleep operation(other than PLL), when PCLK0 = PCLK1 = PCLK2
= HCLK/2
Parameter
Symbol
Pin
name
Conditions
Frequency*4
Value
Unit
Remarks
Typ*1
Max*2
Power supply
current
ICCS
VCC
Sleep
operation
(built-in high-speed
CR)
4MHz
1.5
49
mA
*3
When all peripheral
clocks are ON
1.0
49
mA
*3
When all peripheral
clocks are OFF
Sleep
operation
(sub oscillation)
32kHz
0.59
48
mA
*3
When all peripheral
clocks are ON
0.51
48
mA
*3
When all peripheral
clocks are OFF
Sleep
operation
(built-in low-speed
CR)
100kHz
0.61
48
mA
*3
When all peripheral
clocks are ON
0.53
48
mA
*3
When all peripheral
clocks are OFF
*1: TA = +25°C, VCC = 3.3V
*2: Tj = +125°C, VCC = 5.5V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK/2
Document Number: 002-04918 Rev.*D Page 76 of 160
MB9B160R Series
Table 12-8. Typical and maximum current consumption in STOP mode, TIMER mode and RTC mode
Parameter
Symbol
Pin
name
Conditions
Frequency
Value
Unit
Remarks
Typ*1
Max*2
Power supply
current
ICCH
VCC
STOP mode
-
0.33
1.8
mA
*3, *4
TA = +25°C
-
15
mA
*3, *4
TA = +85°C
-
22
mA
*3, *4
TA = +105°C
ICCT
TIMER mode (built-in
high-speed CR)
4MHz
0.70
2.2
mA
*3, *4
TA = +25°C
-
16
mA
*3, *4
TA = +85°C
-
22
mA
*3, *4
TA = +105°C
TIMER mode
(sub oscillation)
32kHz
0.33
1.8
mA
*3, *4
TA = +25°C
-
15
mA
*3, *4
TA = +85°C
-
22
mA
*3, *4
TA = +105°C
TIMER mode
(built-in
low-speed CR)
100kHz
0.34
1.8
mA
*3, *4
TA = +25°C
-
15
mA
*3, *4
TA = +85°C
-
22
mA
*3, *4
TA = +105°C
ICCR
RTC mode
(sub oscillation)
32kHz
0.33
1.8
mA
*3, *4
TA = +25°C
-
15
mA
*3, *4
TA = +85°C
-
22
mA
*3, *4
TA = +105°C
*1: VCC = 3.3V
*2: VCC = 5.5V
*3: When all ports are fixed.
*4: When LVD is OFF
Document Number: 002-04918 Rev.*D Page 77 of 160
MB9B160R Series
Table 12-9. Typical and maximum current consumption in Deep Standby STOP mode, Deep Standby RTC mode and VBAT
Parameter
Symbol
Pin name
Conditions
Frequency
Value
Unit
Remarks
Typ*1
Max*2
Power supply
current
ICCHD
VCC
Deep standby
STOP mode
(When RAM is
OFF)
-
29
140
μA
*3, *4
TA = +25°C
-
644
μA
*3, *4
TA = +85°C
-
1011
μA
*3, *4
TA = +105°C
Deep standby
STOP mode
(When RAM is ON)
48
273
μA
*3, *4
TA = +25°C
-
2676
μA
*3, *4
TA = +85°C
-
4162
μA
*3, *4
TA = +105°C
ICCRD
Deep standby
RTC mode
(When RAM is
OFF)
32kHz
29
140
μA
*3, *4
TA = +25°C
-
644
μA
*3, *4
TA = +85°C
-
1011
μA
*3, *4
TA = +105°C
Deep standby
RTC mode
(When RAM is ON)
48
273
μA
*3, *4
TA = +25°C
-
2676
μA
*3, *4
TA = +85°C
-
4162
μA
*3, *4
TA = +105°C
ICCVBAT
VBAT
RTC stop*6
-
0.015
0.29
μA
*3, *4, *5
TA = +25°C
-
5.77
μA
*3, *4, *5
TA = +85°C
-
10.6
μA
*3, *4, *5
TA = +105°C
RTC operation*6
1.53
22.6
μA
*3, *4
TA = +25°C
-
35.2
μA
*3, *4
TA = +85°C
-
41.8
μA
*3, *4
TA = +105°C
*1: VCC = 3.3V
*2: VCC = 5.5V
*3: When all ports are fixed.
*4: When LVD is OFF
*5: When sub oscillation is OFF
*6: In the case of setting RTC after VCC power on
Document Number: 002-04918 Rev.*D Page 78 of 160
MB9B160R Series
Table 12-10. Typical and maximum current consumption in Low-voltage detection circuit, Main flash memory write/erase
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Low-voltage
detection circuit
(LVD) power supply
current
ICCLVD
VCC
At operation
-
4
7
μA
For occurrence of
interrupt
Main flash memory
write/erase current
ICCFLASH
At Write/Erase
-
13.4
15.9
mA
Work flash memory
write/erase current
ICCWFLASH
At Write/Erase
-
11.5
13.6
mA
Peripheral current dissipation
Clock system
Peripheral
Unit
Frequency (MHz)
Unit
Remarks
40
80
160
HCLK
GPIO
All ports
0.22
0.43
0.85
mA
DMAC
-
0.74
1.48
2.88
DSTC
-
0.32
0.61
1.17
External bus I/F
-
0.14
0.27
0.55
SD card I/F
-
0.93
1.81
3.63
PCLK1
Base timer
4ch.
0.16
0.34
0.66
mA
Multi-functional timer/PPG
1unit/4ch.
0.55
1.09
2.17
Quadrature
position/Revolution
counter
1unit
0.04
0.09
0.17
A/DC
1unit
0.20
0.39
0.78
PCLK2
Muli-function serial
1ch.
0.31
0.62
-
mA
Document Number: 002-04918 Rev.*D Page 79 of 160
MB9B160R Series
12.3.2 Pin Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Typ
Max
"H" level input
voltage (hysteresis
input)
VIHS
CMOS
hysteresis input
pin, MD0, MD1
-
VCC×0.8
-
VCC + 0.3
V
5V tolerant
input pin
-
VCC×0.8
-
VSS + 5.5
V
Input pin
doubled as I2C
Fm+
-
VCC×0.7
-
VSS + 5.5
V
"L" level input
voltage (hysteresis
input)
VILS
CMOS
hysteresis input
pin, MD0, MD1
-
VSS - 0.3
-
VCC×0.2
V
5V tolerant
input pin
-
VSS - 0.3
-
VCC×0.2
V
Input pin
doubled as I2C
Fm+
-
VSS
-
VCC×0.3
V
"H" level output
voltage
VOH
4mA type
VCC ≥ 4.5 V,
IOH = - 4mA
VCC - 0.5
-
VCC
V
VCC < 4.5 V,
IOH = - 2mA
8mA type
VCC ≥ 4.5 V,
IOH = - 8mA
VCC - 0.5
-
VCC
V
VCC < 4.5 V,
IOH = - 4mA
12mA type
VCC ≥ 4.5 V,
IOH = - 12mA
VCC - 0.5
-
VCC
V
VCC < 4.5 V,
IOH = - 8mA
The pin
doubled as I2C
Fm+
VCC ≥ 4.5 V,
IOH = - 4mA
VCC - 0.5
-
VCC
V
At GPIO
VCC < 4.5 V,
IOH = - 3mA
Document Number: 002-04918 Rev.*D Page 80 of 160
MB9B160R Series
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Typ
Max
"L" level output
voltage
VOL
4mA type
VCC ≥ 4.5 V,
IOL = 4mA
VSS
-
0.4
V
VCC < 4.5 V,
IOL = 2mA
8mA type
VCC ≥ 4.5 V,
IOH = 8mA
VSS
-
0.4
V
VCC < 4.5 V,
IOH = 4mA
12mA type
VCC ≥ 4.5 V,
IOL = 12mA
VSS
-
0.4
V
VCC < 4.5 V,
IOL = 8mA
The pin
doubled as
I2C Fm+
VCC ≥ 4.5 V,
IOH = 4mA
VSS
-
0.4
V
At GPIO
VCC < 4.5 V,
IOH = 3mA
VCC ≤ 5.5 V,
IOH = 20mA
At I2C Fm+
Input leak current
IIL
-
-
- 5
-
+ 5
μA
Pull-up resistor
value
RPU
Pull-up pin
VCC ≥ 4.5 V
25
50
100
kΩ
VCC < 4.5 V
30
80
200
Input capacitance
CIN
Other than
VCC,
VBAT,
VSS,
AVCC,
AVSS, AVRH
-
-
5
15
pF
Document Number: 002-04918 Rev.*D Page 81 of 160
MB9B160R Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
name
Conditions
Value
Unit
Remarks
Min
Max
Input frequency
FCH
X0,
X1
VCC ≥ 4.5V
4
48
MHz
When crystal oscillator is
connected
VCC < 4.5V
4
20
VCC ≥ 4.5V
4
48
MHz
When using external clock
VCC < 4.5V
4
20
Input clock cycle
tCYLH
VCC ≥ 4.5V
20.83
250
ns
When using external clock
VCC < 4.5V
50
250
Input clock pulse width
-
PWH/tCYLH,
PWL/tCYLH
45
55
%
When using external clock
Input clock rising time and
falling time
tCF,
tCR
-
-
5
ns
When using external clock
Internal operating clock*1
frequency
FCC
-
-
-
160
MHz
Base clock (HCLK/FCLK)
FCP0
-
-
-
80
MHz
APB0 bus clock*2
FCP1
-
-
-
160
MHz
APB1 bus clock*2
FCP2
-
-
-
80
MHz
APB2 bus clock*2
Internal operating clock*1
cycle time
tCYCC
-
-
6.25
-
ns
Base clock (HCLK/FCLK)
tCYCP0
-
-
12.5
-
ns
APB0 bus clock*2
tCYCP1
-
-
6.25
-
ns
APB1 bus clock*2
tCYCP2
-
-
12.5
-
ns
APB2 bus clock*2
*1: For more information about each internal operating clock, see “Chapter: Clock” in “FM4 Family Peripheral Manual”.
*2: For about each APB bus which each peripheral is connected to, see “Block Diagram” in this datasheet.
X0
Document Number: 002-04918 Rev.*D Page 82 of 160
MB9B160R Series
12.4.2 Sub Clock Input Characteristics (VBAT = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Input frequency
1/ tCYLL
X0A,
X1A
-
-
32.768
-
kHz
When crystal oscillator
is connected
-
32
-
100
kHz
When using external
clock
Input clock cycle
tCYLL
-
10
-
31.25
μs
When using external
clock
Input clock pulse width
-
PWH/tCYLL,
PWL/tCYLL
45
-
55
%
When using external
clock
12.4.3 Built-in CR Oscillation Characteristics
Built-in High-speed CR (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Remarks
Min
Typ
Max
Clock frequency
FCRH
Tj = -20°C to + 105°C
3.92
4
4.08
MHz
When trimming*1
Tj = - 40°C to + 125°C
3.88
4
4.12
Clock frequency
FCRH
Tj = - 40°C to + 125°C
3
4
5
When not trimming
Frequency stabilization
time
tCRWT
-
-
-
30
μs
*2
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming.
*2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value. This period is able to use
high-speed CR clock as source clock.
Built-in Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Condition
Value
Unit
Remarks
Min
Typ
Max
Clock frequency
FCRL
-
50
100
150
kHz
X0A
VBAT
VBAT
VBAT
VBAT
0.8 × VBAT
Document Number: 002-04918 Rev.*D Page 83 of 160
MB9B160R Series
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Value
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
200
-
-
μs
PLL input clock frequency
FPLLI
4
-
16
MHz
PLL multiplication rate
-
13
-
80
multiplier
PLL macro oscillation clock frequency
FPLLO
200
-
320
MHz
Main PLL clock frequency*2
FCLKPLL
-
-
160
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see “Chapter: Clock” in “FM4 Family Peripheral Manual”.
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input clock of main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Value
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
200
-
-
μs
PLL input clock frequency
FPLLI
3.8
4
4.2
MHz
PLL multiplication rate
-
50
-
75
multiplier
PLL macro oscillation clock frequency
FPLLO
190
-
320
MHz
Main PLL clock frequency*2
FCLKPLL
-
-
160
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see “Chapter: Clock” in “FM4 Family Peripheral Manual”.
Note:
− Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has
been trimmed.
12.4.6 Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Condition
Value
Unit
Remarks
Min
Max
Reset input time
tINITX
INITX
-
500
-
ns
Document Number: 002-04918 Rev.*D Page 84 of 160
MB9B160R Series
12.4.7 Power-on Reset Timing (VSS = 0V, TA = -40°C to +85°C)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Power supply shut down time
tOFF
VCC
-
50
-
-
ms
*1
Power ramp rate
dV/dt
VCC: 0.2V to 2.70V
1.3
-
1000
mV/µs
*2
Time until releasing Power-on reset
tPRT
-
0.33
-
0.60
ms
*1: VCC must be held below 0.2V for a minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50ms).
Note:
− If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 6.
Glossary:
VDH: detection voltage of Low Voltage detection reset. See “12.7. Low-Voltage Detection Characteristics”.
12.4.8 GPIO Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
Output frequency
tPCYCLE
Pxx*
VCC ≥ 4.5 V
-
50
MHz
VCC < 4.5 V
-
32
MHz
*: GPIO is a target.
Pxx
tPCYCLE
VDH
tPRT
Internal RST
VCC
CPU Operation start
RST Active release
0.2V 0.2V
tOFF
dV/dt
0.2V
2.7V
Document Number: 002-04918 Rev.*D Page 85 of 160
MB9B160R Series
12.4.9 External Bus Timing
External bus clock output characteristics (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
Output frequency
tCYCLE
MCLKOUT*1
VCC ≥ 4.5 V
-
50*2
MHz
VCC < 4.5 V
-
32*3
MHz
*1: The external bus clock (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see “Chapter: External Bus Interface” in “FM4 Family Peripheral Manual”.
*2: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 100MHz.
*3: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 64MHz.
External bus signal input/output characteristics (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Remarks
Signal input characteristics
VIH
-
0.8 × VCC
V
VIL
0.2 × VCC
V
Signal output characteristics
VOH
0.8 × VCC
V
VOL
0.2 × VCC
V
0.8 × Vcc0.8 × Vcc
tCYCLE
VIH
VIL VIL
VIH
VOH
VOL VOL
VOH
MCLK
Signal input
Signal output
Document Number: 002-04918 Rev.*D Page 86 of 160
MB9B160R Series
Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
MOEX
Mininum pulse width
tOEW
MOEX
VCC ≥ 4.5V
MCLK×n-3
-
ns
VCC < 4.5V
MCSX↓→Address output
delay time
tCSL – AV
MCSX[7:0],
MAD[24:0]
VCC ≥ 4.5V
-9
+9
ns
VCC < 4.5V
-12
+12
MOEX↑→Address hold time
tOEH - AX
MOEX,
MAD[24:0]
VCC ≥ 4.5V
0
MCLK×m+9
ns
VCC < 4.5V
MCLK×m+12
MCSX↓→
MOEX↓ delay time
tCSL - OEL
MOEX,
MCSX[7:0]
VCC ≥ 4.5V
MCLK×m-9
MCLK×m+9
ns
VCC < 4.5V
MCLK×m-12
MCLK×m+12
MOEX↑→
MCSX↑ time
tOEH - CSH
VCC ≥ 4.5V
0
MCLK×m+9
ns
VCC < 4.5V
MCLK×m+12
MCSX↓→MDQM↓
delay time
tCSL - RDQML
MCSX,
MDQM[1:0]
VCC ≥ 4.5V
MCLK×m-9
MCLK×m+9
ns
VCC < 4.5V
MCLK×m-12
MCLK×m+12
Data set up→MOEX↑ time
tDS - OE
MOEX,
MADATA[15:0]
VCC ≥ 4.5V
20
-
ns
VCC < 4.5V
38
-
MOEX↑→
Data hold time
tDH - OE
MOEX,
MADATA[15:0]
VCC ≥ 4.5V
0
-
ns
VCC < 4.5V
MWEX
Mininum pulse width
tWEW
MWEX
VCC ≥ 4.5V
MCLK×n-3
-
ns
VCC < 4.5V
MWEX↑→Address output
delay time
tWEH - AX
MWEX,
MAD[24:0]
VCC ≥ 4.5V
0
MCLK×m+9
ns
VCC < 4.5V
MCLK×m+12
MCSX↓→MWEX↓ delay time
tCSL - WEL
MWEX,
MCSX[7:0]
VCC ≥ 4.5V
MCLK×n-9
MCLK×n+9
ns
VCC < 4.5V
MCLK×n-12
MCLK×n+12
MWEX↑→MCSX↑ delay time
tWEH - CSH
VCC ≥ 4.5V
0
MCLK×m+9
ns
VCC < 4.5V
MCLK×m+12
MCSX↓→MDQM↓ delay time
tCSL-WDQML
MCSX,
MDQM[1:0]
VCC ≥ 4.5V
MCLK×n-9
MCLK×n+9
ns
VCC < 4.5V
MCLK×n-12
MCLK×n+12
MCSX↓→
Data output time
tCSL-DX
MCSX,
MADATA[15:0]
VCC ≥ 4.5V
MCLK-9
MCLK+9
ns
VCC < 4.5V
MCLK-12
MCLK+12
MWEX↑→
Data hold time
tWEH - DX
MWEX,
MADATA[15:0]
VCC ≥ 4.5V
0
MCLK×m+9
ns
VCC < 4.5V
MCLK×m+12
Note:
− When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16)
Document Number: 002-04918 Rev.*D Page 87 of 160
MB9B160R Series
Invalid
Address
tCSL-OEL
tCSL-AV
RD
Address
WD
tDH-OE
tDS-OE tWEH-DX
tOEW
tOEH-AX
tOEH-CSH
tWEW
tCYCLE
tCSL-WEL
tCSL-AV
tWEH-CSH
tWEH-AX
tCSL-WDQML
tCSL-RDQML
tCSL-DX
MCLK
MCSX[7:0]
MAD[24:0]
MDQM[1:0]
MWEX
MADATA[15:0]
MOEX
Document Number: 002-04918 Rev.*D Page 88 of 160
MB9B160R Series
Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
Address delay time
tAV
MCLK,
MAD[24:0]
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
MCSX delay time
tCSL
MCLK,
MCSX[7:0]
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
tCSH
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
MOEX delay time
tREL
MCLK,
MOEX
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
tREH
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
Data set up
→MCLK↑ time
tDS
MCLK,
MADATA[15:0]
VCC ≥ 4.5V
19
-
ns
VCC < 4.5V
37
MCLK↑→
Data hold time
tDH
MCLK,
MADATA[15:0]
VCC ≥ 4.5V
0
-
ns
VCC < 4.5V
MWEX delay time
tWEL
MCLK,
MWEX
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
tWEH
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
MDQM[1:0]
delay time
tDQML
MCLK,
MDQM[1:0]
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
tDQMH
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
MCLK↑→
Data output time
tODS
MCLK,
MADATA[15:0]
VCC ≥ 4.5V
MCLK+1
MCLK+18
ns
VCC < 4.5V
MCLK+24
MCLK↑→
Data hold time
tOD
MCLK,
MADATA[15:0]
VCC ≥ 4.5V
1
18
ns
VCC < 4.5V
24
Note:
− When the external load capacitance CL = 30pF
Invalid
tDQML
tREH
Address
tCSL
tAV
tREL
RD
Address
WD
tDQMH
tWEH
tWEL
tDH
tDS tOD
tAV
tCSH
tCYCLE
tDQML tDQMH
tODS
MCLK
MCSX[7:0]
MAD[24:0]
MDQM[1:0]
MWEX
MADATA[15:0]
MOEX
Document Number: 002-04918 Rev.*D Page 89 of 160
MB9B160R Series
Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
Multiplexed address delay
time
tALE-CHMADV
MALE,
MADATA[15:0]
VCC ≥ 4.5V
0
10
ns
VCC < 4.5V
20
Multiplexed address hold
time
tCHMADH
VCC ≥ 4.5V
MCLK×n+0
MCLK×n+10
ns
VCC < 4.5V
MCLK×n+0
MCLK×n+20
Note:
− When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16)
MCLK
MCSX[7:0]
MALE
MOEX
MWEX
MADATA[15:0]
MAD [24:0]
MDQM [1:0]
Document Number: 002-04918 Rev.*D Page 90 of 160
MB9B160R Series
Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Max
MALE delay time
tCHAL
MCLK,
ALE
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
ns
tCHAH
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
ns
MCLK↑→
Multiplexed address delay
time
tCHMADV
MCLK,
MADATA[15:0]
VCC ≥ 4.5V
1
tOD
ns
VCC < 4.5V
MCLK↑→
Multiplexed data output time
tCHMADX
VCC ≥ 4.5V
1
tOD
ns
VCC < 4.5V
Note:
− When the external load capacitance CL = 30pF
MCLK
MCSX[7:0]
MALE
MOEX
MWEX
MADATA[15:0]
MAD [24:0]
MDQM [1:0]
Document Number: 002-04918 Rev.*D Page 91 of 160
MB9B160R Series
NAND Flash Mode (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
MNREX
Min pulse width
tNREW
MNREX
VCC ≥ 4.5V
MCLK×n-3
-
ns
VCC < 4.5V
Data set up
→MNREX↑ time
tDS – NRE
MNREX,
MADATA[15:0]
VCC ≥ 4.5V
20
-
ns
VCC < 4.5V
38
-
MNREX↑→
Data hold time
tDH – NRE
MNREX,
MADATA[15:0]
VCC ≥ 4.5V
0
-
ns
VCC < 4.5V
MNALE↑→
MNWEX delay time
tALEH - NWEL
MNALE,
MNWEX
VCC ≥ 4.5V
MCLK×m-9
MCLK×m+9
ns
VCC < 4.5V
MCLK×m-12
MCLK×m+12
MNALE↓→
MNWEX delay time
tALEL - NWEL
MNALE,
MNWEX
VCC ≥ 4.5V
MCLK×m-9
MCLK×m+9
ns
VCC < 4.5V
MCLK×m-12
MCLK×m+12
MNCLE↑→
MNWEX delay time
tCLEH - NWEL
MNCLE,
MNWEX
VCC ≥ 4.5V
MCLK×m-9
MCLK×m+9
ns
VCC < 4.5V
MCLK×m-12
MCLK×m+12
MNWEX↑→
MNCLE delay time
tNWEH - CLEL
MNCLE,
MNWEX
VCC ≥ 4.5V
0
MCLK×m+9
ns
VCC < 4.5V
MCLK×m+12
MNWEX
Min pulse width
tNWEW
MNWEX
VCC ≥ 4.5V
MCLK×n-3
-
ns
VCC < 4.5V
MNWEX↓→
Data output time
tNWEL – DV
MNWEX,
MADATA[15:0]
VCC ≥ 4.5V
- 9
+ 9
ns
VCC < 4.5V
-12
+12
MNWEX↑→
Data hold time
tNWEH – DX
MNWEX,
MADATA[15:0]
VCC ≥ 4.5V
0
MCLK×m+9
ns
VCC < 4.5V
MCLK×m+12
Note:
− When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16)
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
Read
Document Number: 002-04918 Rev.*D Page 92 of 160
MB9B160R Series
NAND Flash Address Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MADATA[15:0]
MNWEX
Write
MCLK
MNALE
MNCLE
MADATA[15:0]
MNWEX
Write
Document Number: 002-04918 Rev.*D Page 93 of 160
MB9B160R Series
External Ready Input Timing (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Max
MCLK↑
MRDY input
setup time
tRDYI
MCLK,
MRDY
VCC ≥ 4.5V
19
-
ns
VCC < 4.5V
37
When RDY is input
When RDY is released
···
Over 2cycle
tRDYI
······
2 cycle
tRDYI
0.5×VCC
MCLK
Original
MOEX
MWEX
MRDY
MCLK
Extended
MOEX
MWEX
MRDY
Document Number: 002-04918 Rev.*D Page 94 of 160
MB9B160R Series
SDRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin name
Value
Unit
Min
Max
Output frequency
tCYCSD
MSDCLK
-
32
MHz
Address delay time
tAOSD
MSDCLK,
MAD[15:0]
2
12
ns
MSDCLK↑→Data output delay time
tDOSD
MSDCLK,
MADATA[31:0]
2
12
ns
MSDCLK↑→Data output
Hi-Z time
tDOZSD
MSDCLK,
MADATA[31:0]
2
20
ns
MDQM[1:0] delay time
tWROSD
MSDCLK,
MDQM[1:0]
1
12
ns
MCSX delay time
tMCSSD
MSDCLK,
MCSX8
2
12
ns
MRASX delay time
tRASSD
MSDCLK,
MRASX
2
12
ns
MCASX delay time
tCASSD
MSDCLK,
MCASX
2
12
ns
MSDWEX delay time
tMWESD
MSDCLK,
MSDWEX
2
12
ns
MSDCKE delay time
tCKESD
MSDCLK,
MSDCKE
2
12
ns
Data set up time
tDSSD
MSDCLK,
MADATA[31:0]
23
-
ns
Data hold time
tDHSD
MSDCLK,
MADATA[31:0]
0
-
ns
Note:
− When the external load capacitance CL = 30pF
Document Number: 002-04918 Rev.*D Page 95 of 160
MB9B160R Series
RD
WD
MSDCLK
MDQM[1:0]
MCSX
MRASX
MCASX
MSDWEX
MSDCKE
MADATA[15:0]
Address
MADATA[15:0]
MAD[24:0]
tCYCSD
tAOSD
tWROSD
tMCSSD
tRASSD
tCASSD
tMWESD
tCKESD
tDOSD tDOZSD
tDSSD tDHSD
SDRAM Access
Document Number: 002-04918 Rev.*D Page 96 of 160
MB9B160R Series
12.4.10 Base Timer Input Timing
Timer input timing (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Max
Input pulse width
tTIWH,
tTIWL
TIOAn/TIOBn
(when using as ECK,
TIN)
-
2tCYCP
-
ns
Trigger input timing (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Max
Input pulse width
tTRGH,
tTRGL
TIOAn/TIOBn
(when using as TGIN)
-
2tCYCP
-
ns
Note:
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see “Block Diagram” in this datasheet.
tTIWH
VIHS VIHS VILS VILS
tTIWL
tTRGH
VIHS VIHS VILS VILS
tTRGL
ECK
TIN
TGIN
Document Number: 002-04918 Rev.*D Page 97 of 160
MB9B160R Series
12.4.11 CSIO/UART Timing
Synchronous serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
name
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
Baud rate
-
-
-
-
8
-
8
Mbps
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
4tCYCP
-
ns
SCK↓→SOT delay time
tSLOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN→SCK↑
setup time
tIVSHI
SCKx,
SINx
50
-
30
-
ns
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
0
-
0
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
External shift
clock
operation
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
50
-
30
ns
SIN→SCK↑
setup time
tIVSHE
SCKx,
SINx
10
-
10
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
20
-
20
-
ns
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30pF.
Document Number: 002-04918 Rev.*D Page 98 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tSCYC
VOH
VOH
VOL
VOL
VOL
VIH
VIL
VIH
VIL
tSLOVI
tIVSHI tSHIXI
tSLSH tSHSL
VIH
tFtR
VIH
VOH
VIH
VIL VIL
VOL
VIH
VIL VIH
VIL
tSLOVE
tIVSHE tSHIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04918 Rev.*D Page 99 of 160
MB9B160R Series
Synchronous serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
name
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
Baud rate
-
-
-
-
8
-
8
Mbps
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
4tCYCP
-
ns
SCK↑→SOT delay time
tSHOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN→SCK↓
setup time
tIVSLI
SCKx,
SINx
50
-
30
-
ns
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
0
-
0
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
External shift clock
operation
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
50
-
30
ns
SIN→SCK↓
setup time
tIVSLE
SCKx,
SINx
10
-
10
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
20
-
20
-
ns
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30pF.
Document Number: 002-04918 Rev.*D Page 100 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tSCYC
VOH VOH
VOH
VOL
VOL
VIH
VIL
VIH
VIL
tSHOVI
tIVSLI tSLIXI
tSHSL tSLSH
VIH
tF
tR
VIH
VOH
VIL
VIL VIL
VOL
VIH
VIL VIH
VIL
tSHOVE
tIVSLE tSLIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04918 Rev.*D Page 101 of 160
MB9B160R Series
Synchronous serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
name
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
Baud rate
-
-
-
-
8
-
8
Mbps
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
4tCYCP
-
ns
SCK↑→SOT delay time
tSHOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN→SCK↓
setup time
tIVSLI
SCKx,
SINx
50
-
30
-
ns
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
0
-
0
-
ns
SOT→SCK↓ delay time
tSOVLI
SCKx,
SOTx
2tCYCP - 30
-
2tCYCP - 30
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
External shift
clock operation
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
50
-
30
ns
SIN→SCK↓
setup time
tIVSLE
SCKx,
SINx
10
-
10
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
20
-
20
-
ns
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
− About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30pF.
Document Number: 002-04918 Rev.*D Page 102 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
*: Changes when writing to TDR register
tSOVLI
tSCYC
tSHOVI
VOL VOL
VOH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSLI tSLIXI
tF tR
tSLSH tSHSL
tSHOVE
VIL VIL
VIH VIH VIH
VOH
*VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSLE tSLIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04918 Rev.*D Page 103 of 160
MB9B160R Series
Synchronous serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
name
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
Baud rate
-
-
-
-
8
-
8
Mbps
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
4tCYCP
-
ns
SCK↓→SOT delay time
tSLOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN→SCK↑
setup time
tIVSHI
SCKx,
SINx
50
-
30
-
ns
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
0
-
0
-
ns
SOT→SCK↑ delay time
tSOVHI
SCKx,
SOTx
2tCYCP - 30
-
2tCYCP -
30
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
External shift clock
operation
2tCYCP - 10
-
2tCYCP -
10
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP +
10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
50
-
30
ns
SIN→SCK↑
setup time
tIVSHE
SCKx,
SINx
10
-
10
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
20
-
20
-
ns
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30pF.
Document Number: 002-04918 Rev.*D Page 104 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tSCYC
tSLOVI
VOL
VOH VOH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSHI tSHIXI
tSOVHI
tSHSL
tR tSLSH tF
tSLOVE
VIL VIL
VIL VIH VIH
VIH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSHE tSHIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04918 Rev.*D Page 105 of 160
MB9B160R Series
When using synchronous serial chip select (SCINV = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
SCS↓→SCK↓setup time
tCSSI
Internal shift
clock operation
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
SCK↑→SCS↑ hold time
tCSHI
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
SCS deselect time
tCSDI
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
ns
SCS↓→SCK↓setup time
tCSSE
External shift
clock operation
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↑→SCS↑ hold time
tCSHE
0
-
0
-
ns
SCS deselect time
tCSDE
3tCYCP+30
-
3tCYCP+30
-
ns
SCS↓→SUT delay time
tDSE
-
40
-
40
ns
SCS↑→SUT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
− When the external load capacitance CL = 30pF.
Document Number: 002-04918 Rev.*D Page 106 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSEtCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-04918 Rev.*D Page 107 of 160
MB9B160R Series
When using synchronous serial chip select (SCINV = 1, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
SCS↓→SCK↑setup time
tCSSI
Internal shift
clock operation
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
SCK↓→SCS↑ hold time
tCSHI
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
SCS deselect time
tCSDI
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
ns
SCS↓→SCK↑setup time
tCSSE
External shift
clock operation
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↓→SCS↑ hold time
tCSHE
0
-
0
-
ns
SCS deselect time
tCSDE
3tCYCP+30
-
3tCYCP+30
-
ns
SCS↓→SOT delay time
tDSE
-
40
-
40
ns
SCS↑→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
− When the external load capacitance CL = 30pF.
Document Number: 002-04918 Rev.*D Page 108 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSEtCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-04918 Rev.*D Page 109 of 160
MB9B160R Series
When using synchronous serial chip select (SCINV = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
SCS↑→SCK↓setup time
tCSSI
Internal shift
clock operation
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
SCK↑→SCS↓ hold time
tCSHI
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
SCS deselect time
tCSDI
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
ns
SCS↑→SCK↓setup time
tCSSE
External shift
clock operation
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↑→SCS↓ hold time
tCSHE
0
-
0
-
ns
SCS deselect time
tCSDE
3tCYCP+30
-
3tCYCP+30
-
ns
SCS↑→SOT delay time
tDSE
-
40
-
40
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
− When the external load capacitance CL = 30pF.
Document Number: 002-04918 Rev.*D Page 110 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSE tCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-04918 Rev.*D Page 111 of 160
MB9B160R Series
When using synchronous serial chip select (SCINV = 1, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
SCS↑→SCK↑setup time
tCSSI
Internal shift
clock operation
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
SCK↓→SCS↓ hold time
tCSHI
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
SCS deselect time
tCSDI
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
ns
SCS↑→SCK↑setup time
tCSSE
External shift
clock operation
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↓→SCS↓ hold time
tCSHE
0
-
0
-
ns
SCS deselect time
tCSDE
3tCYCP+30
-
3tCYCP+30
-
ns
SCS↑→SOT delay time
tDSE
-
40
-
40
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
− When the external load capacitance CL = 30pF.
Document Number: 002-04918 Rev.*D Page 112 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSE tCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-04918 Rev.*D Page 113 of 160
MB9B160R Series
High-speed synchronous serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
name
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
4tCYCP
-
ns
SCK↓→SOT delay time
tSLOVI
SCKx,
SOTx
-10
+10
-10
+10
ns
SIN→SCK↑
setup time
tIVSHI
SCKx,
SINx
14
-
12.5
-
ns
12.5*
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
5
-
5
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
External shift clock
operation
2tCYCP – 5
-
2tCYCP – 5
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
15
-
15
ns
SIN→SCK↑
setup time
tIVSHE
SCKx,
SINx
5
-
5
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
5
-
5
-
ns
SINx
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− These characteristics only guarantee the following pins.
− No chip select: SIN4_1, SOT4_1, SCK4_1
− Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1
− When the external load capacitance CL = 30pF. (For *, when CL = 10pF)
Document Number: 002-04918 Rev.*D Page 114 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tSCYC
VOH
VOH
VOL
VOL
VOL
VIH
VIL
VIH
VIL
tSLOVI
tIVSHI tSHIXI
tSLSH tSHSL
VIH
tFtR
VIH
VOH
VIH
VIL VIL
VOL
VIH
VIL VIH
VIL
tSLOVE
tIVSHE tSHIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04918 Rev.*D Page 115 of 160
MB9B160R Series
High-speed synchronous serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
name
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
4tCYCP
-
ns
SCK↑→SOT delay time
tSHOVI
SCKx,
SOTx
-10
+10
-10
+10
ns
SIN→SCK↓
setup time
tIVSLI
SCKx,
SINx
14
-
12.5
-
ns
12.5*
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
5
-
5
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
External shift clock
operation
2tCYCP – 5
-
2tCYCP – 5
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
15
-
15
ns
SIN→SCK↓
setup time
tIVSLE
SCKx,
SINx
5
-
5
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
5
-
5
-
ns
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− These characteristics only guarantee the following pins.
− No chip select: SIN4_1, SOT4_1, SCK4_1
− Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1
− When the external load capacitance CL = 30pF. (For *, when CL = 10pF)
Document Number: 002-04918 Rev.*D Page 116 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tSCYC
VOH VOH
VOH
VOL
VOL
VIH
VIL
VIH
VIL
tSHOVI
tIVSLI tSLIXI
tSHSL tSLSH
VIH
tF
tR
VIH
VOH
VIL
VIL VIL
VOL
VIH
VIL VIH
VIL
tSHOVE
tIVSLE tSLIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04918 Rev.*D Page 117 of 160
MB9B160R Series
High-speed synchronous serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
Serial clock cycle time
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
4tCYCP
-
ns
SCK↑→SOT delay time
tSHOVI
SCKx,
SOTx
-10
+10
-10
+10
ns
SIN→SCK↓
setup time
tIVSLI
SCKx,
SINx
14
-
12.5
-
ns
12.5*
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
5
-
5
-
ns
SOT→SCK↓ delay time
tSOVLI
SCKx,
SOTx
2tCYCP – 10
-
2tCYCP – 10
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
External shift clock
operation
2tCYCP – 5
-
2tCYCP – 5
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
15
-
15
ns
SIN→SCK↓
setup time
tIVSLE
SCKx,
SINx
5
-
5
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
5
-
5
-
ns
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− These characteristics only guarantee the following pins.
− No chip select: SIN4_1, SOT4_1, SCK4_1
− Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1
− When the external load capacitance CL = 30pF. (For *, when CL = 10pF)
Document Number: 002-04918 Rev.*D Page 118 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
*: Changes when writing to TDR register
tSOVLI
tSCYC
tSHOVI
VOL VOL
VOH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSLI tSLIXI
tF tR
tSLSH tSHSL
tSHOVE
VIL VIL
VIH VIH VIH
VOH
*VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSLE tSLIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04918 Rev.*D Page 119 of 160
MB9B160R Series
High-speed synchronous serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
name
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
Internal shift clock operation
tSCYC
SCKx
Internal shift clock
operation
4tCYCP
-
4tCYCP
-
ns
SCK↓→SOT delay time
tSLOVI
SCKx,
SOTx
-10
+10
-10
+10
ns
SIN→SCK↑
setup time
tIVSHI
SCKx,
SINx
14
-
12.5
-
ns
12.5*
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
5
-
5
-
ns
SOT→SCK↑ delay time
tSOVHI
SCKx,
SOTx
2tCYCP – 10
-
2tCYCP – 10
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
External shift clock
operation
2tCYCP – 5
-
2tCYCP – 5
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
15
-
15
ns
SIN→SCK↑
setup time
tIVSHE
SCKx,
SINx
5
-
5
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
5
-
5
-
ns
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− These characteristics only guarantee the following pins.
− No chip select: SIN4_1, SOT4_1, SCK4_1
− Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1
− When the external load capacitance CL = 30pF. (For *, when CL = 10pF)
Document Number: 002-04918 Rev.*D Page 120 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tSCYC
tSLOVI
VOL
VOH VOH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSHI tSHIXI
tSOVHI
tSHSL
tR tSLSH tF
tSLOVE
VIL VIL
VIL VIH VIH
VIH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSHE tSHIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04918 Rev.*D Page 121 of 160
MB9B160R Series
When using high-speed synchronous serial chip select (SCINV = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
SCS↓→SCK↓setup time
tCSSI
Internal shift clock
operation
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
SCK↑→SCS↑ hold time
tCSHI
(*2)+0
(*2)+20
(*2)+0
(*2)+20
ns
SCS deselect time
tCSDI
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
ns
SCS↓→SCK↓setup time
tCSSE
External shift clock
operation
3tCYCP+15
-
3tCYCP+15
-
ns
SCK↑→SCS↑ hold time
tCSHE
0
-
0
-
ns
SCS deselect time
tCSDE
3tCYCP+15
-
3tCYCP+15
-
ns
SCS↓→SOT delay time
tDSE
-
25
-
25
ns
SCS↑→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
− When the external load capacitance CL = 30pF.
Document Number: 002-04918 Rev.*D Page 122 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSEtCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-04918 Rev.*D Page 123 of 160
MB9B160R Series
When using high-speed synchronous serial chip select (SCINV = 1, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
SCS↓→SCK↑setup time
tCSSI
Internal shift
clock operation
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
SCK↓→SCS↑ hold time
tCSHI
(*2)+0
(*2)+20
(*2)+0
(*2)+20
ns
SCS deselect time
tCSDI
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
ns
SCS↓→SCK↑setup time
tCSSE
External shift
clock operation
3tCYCP+15
-
3tCYCP+15
-
ns
SCK↓→SCS↑ hold time
tCSHE
0
-
0
-
ns
SCS deselect time
tCSDE
3tCYCP+15
-
3tCYCP+15
-
ns
SCS↓→SOT delay time
tDSE
-
25
-
25
ns
SCS↑→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
− When the external load capacitance CL = 30pF.
Document Number: 002-04918 Rev.*D Page 124 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSEtCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-04918 Rev.*D Page 125 of 160
MB9B160R Series
When using high-speed synchronous serial chip select (SCINV = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
SCS↑→SCK↓setup time
tCSSI
Internal shift clock
operation
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
SCK↑→SCS↓ hold time
tCSHI
(*2)+0
(*2)+20
(*2)+0
(*2)+20
ns
SCS deselect time
tCSDI
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
ns
SCS↑→SCK↓setup time
tCSSE
External shift clock
operation
3tCYCP+15
-
3tCYCP+15
-
ns
SCK↑→SCS↓ hold time
tCSHE
0
-
0
-
ns
SCS deselect time
tCSDE
3tCYCP+15
-
3tCYCP+15
-
ns
SCS↑→SOT delay time
tDSE
-
25
-
25
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
− When the external load capacitance CL = 30pF.
Document Number: 002-04918 Rev.*D Page 126 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSE tCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-04918 Rev.*D Page 127 of 160
MB9B160R Series
When using high-speed synchronous serial chip select (SCINV = 1, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
SCS↑→SCK↑setup time
tCSSI
Internal shift
clock operation
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
SCK↓→SCS↓ hold time
tCSHI
(*2)+0
(*2)+20
(*2)+0
(*2)+20
ns
SCS deselect time
tCSDI
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
ns
SCS↑→SCK↑setup time
tCSSE
External shift
clock operation
3tCYCP+15
-
3tCYCP+15
-
ns
SCK↓→SCS↓ hold time
tCSHE
0
-
0
-
ns
SCS deselect time
tCSDE
3tCYCP+15
-
3tCYCP+15
-
ns
SCS↑→SOT delay time
tDSE
-
25
-
25
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.
− About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.
− When the external load capacitance CL = 30pF.
Document Number: 002-04918 Rev.*D Page 128 of 160
MB9B160R Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSE tCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-04918 Rev.*D Page 129 of 160
MB9B160R Series
External clock (EXT = 1) : when in asynchronous mode only (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Condition
Value
Unit
Remarks
Min
Max
Serial clock "L" pulse width
tSLSH
CL = 30pF
tCYCP + 10
-
ns
Serial clock "H" pulse width
tSHSL
tCYCP + 10
-
ns
SCK falling time
tF
-
5
ns
SCK rising time
tR
-
5
ns
tSHSL
VIL VIL VIL
VIH VIH VIH
tR tF
tSLSH
SCK
Document Number: 002-04918 Rev.*D Page 130 of 160
MB9B160R Series
12.4.12 External Input Timing (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Max
Input pulse
width
tINH,
tINL
ADTG
-
2tCYCP*1
-
ns
A/D converter trigger input
FRCKx
Free-run timer input clock
ICxx
Input capture
DTTIxX
-
2tCYCP*1
-
ns
Waveform generator
INT00 to INT31,
NMIX
-
2tCYCP + 100*1
-
ns
External interrupt,
NMI
500*2
-
ns
WKUPx
-
500*3
-
ns
Deep standby wake up
*1: tCYCP indicates the APB bus clock cycle time except stop when in STOP mode, in timer mode.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to,
see “Block Diagram” in this data sheet.
*2: When in STOP mode, in timer mode.
*3: When in deep standby RTC mode, in deep standby STOP mode.
Document Number: 002-04918 Rev.*D Page 131 of 160
MB9B160R Series
12.4.13 Quadrature Position/Revolution Counter Timing (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Min
Max
AIN pin "H" width
tAHL
-
2tCYCP*
-
ns
AIN pin "L" width
tALL
-
BIN pin "H" width
tBHL
-
BIN pin "L" width
tBLL
-
BIN rising time from
AIN pin "H" level
tAUBU
PC_Mode2 or PC_Mode3
AIN falling time from
BIN pin "H" level
tBUAD
PC_Mode2 or PC_Mode3
BIN falling time from
AIN pin "L" level
tADBD
PC_Mode2 or PC_Mode3
AIN rising time from
BIN pin "L" level
tBDAU
PC_Mode2 or PC_Mode3
AIN rising time from
BIN pin "H" level
tBUAU
PC_Mode2 or PC_Mode3
BIN falling time from
AIN pin "H" level
tAUBD
PC_Mode2 or PC_Mode3
AIN falling time from
BIN pin "L" level
tBDAD
PC_Mode2 or PC_Mode3
BIN rising time from
AIN pin "L" level
tADBU
PC_Mode2 or PC_Mode3
ZIN pin "H" width
tZHL
QCR:CGSC = "0"
ZIN pin "L" width
tZLL
QCR:CGSC = "0"
AIN/BIN rising and falling time from
determined ZIN level
tZABE
QCR:CGSC = "1"
Determined ZIN level from AIN/BIN
rising and falling time
tABEZ
QCR:CGSC = "1"
*: tCYCP indicates the APB bus clock cycle time except stop when in STOP mode, in timer mode.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see “Block Diagram” in this data
sheet.
AIN
BIN
tAUBU tBUAD tADBD tBDAU
tAHL tALL
tBHL tBLL
Document Number: 002-04918 Rev.*D Page 132 of 160
MB9B160R Series
BIN
tBUAU tAUBD tBDAD tADBU
tBHL tBLL
tAHL tALL
AIN
ZIN
ZIN
AIN/BIN
Document Number: 002-04918 Rev.*D Page 133 of 160
MB9B160R Series
12.4.14 I2C Timing
Standard-mode, Fast-mode (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Standard-mode
Fast-mode
Unit
Remarks
Min
Max
Min
Max
SCL clock frequency
FSCL
CL = 30pF,
R = (Vp/IOL)*1
0
100
0
400
kHz
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
tHDSTA
4.0
-
0.6
-
μs
SCL clock "L" width
tLOW
4.7
-
1.3
-
μs
SCL clock "H" width
tHIGH
4.0
-
0.6
-
μs
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
tSUSTA
4.7
-
0.6
-
μs
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
0
3.45*2
0
0.9*3
μs
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT
250
-
100
-
ns
STOP condition setup time
SCL ↑ → SDA ↑
tSUSTO
4.0
-
0.6
-
μs
Bus free time between
"STOP condition" and
"START condition"
tBUF
4.7
-
1.3
-
μs
Noise filter
tSP
2MHz ≤
tCYCP<40MHz
2tCYCP*4
-
2tCYCP*4
-
ns
*5
40MHz ≤
tCYCP<60MHz
4tCYCP*4
-
4tCYCP*4
-
ns
60MHz ≤
tCYCP<80MHz
6tCYCP*4
-
6tCYCP*4
-
ns
80MHz ≤
tCYCP<100MHz
8tCYCP*4
-
8tCYCP*4
-
ns
100MHz ≤
tCYCP<120MHz
10tCYCP*4
-
10tCYCP*4
-
ns
120MHz ≤
tCYCP<140MHz
12tCYCP*4
-
12tCYCP*4
-
ns
140MHz ≤
tCYCP<160MHz
14tCYCP*4
-
14tCYCP*4
-
ns
160MHz ≤
tCYCP<180MHz
16tCYCP*4
-
16tCYCP*4
-
ns
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power
supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of
“tSUDAT ≥ 250 ns”.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see “Block Diagram” in this data sheet.
*5: The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
Document Number: 002-04918 Rev.*D Page 134 of 160
MB9B160R Series
Fast-mode Plus (Fm+) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Fast-mode Plus (Fm+)*6
Unit
Remarks
Min
Max
SCL clock frequency
FSCL
CL = 30pF,
R = (Vp/IOL)*1
0
1000
kHz
(Repeated) START condition hold time
SDA ↓ → SCL ↓
tHDSTA
0.26
-
μs
SCL clock "L" width
tLOW
0.5
-
μs
SCL clock "H" width
tHIGH
0.26
-
μs
SCL clock frequency
tSUSTA
0.26
-
μs
(Repeated) START condition hold time
SDA ↓ → SCL ↓
tHDDAT
0
0.45*2, *3
μs
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT
50
-
ns
STOP condition setup time
SCL ↑ → SDA ↑
tSUSTO
0.26
-
μs
Bus free time between
"STOP condition" and
"START condition"
tBUF
0.5
-
μs
Noise filter
tSP
60MHz ≤
tCYCP<80MHz
6 tCYCP*4
-
ns
*5
80MHz ≤
tCYCP<100MHz
8 tCYCP*4
-
ns
100MHz ≤
tCYCP<120MHz
10 tCYCP*4
-
ns
120MHz ≤
tCYCP<140MHz
12 tCYCP*4
-
ns
140MHz ≤
tCYCP<160MHz
14 tCYCP*4
-
ns
160MHz ≤
tCYCP<180MHz
16 tCYCP*4
-
ns
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power
supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of
"tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see “Block Diagram” in this data sheet.
To use Fast-mode Plus (Fm+), set the peripheral bus clock at 64 MHz or more.
*5: The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
*6: When using Fast-mode Plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register.
See “Chapter: I/O Port” in “FM4 Family Peripheral Manual” for the details.
SDA
SCL
Document Number: 002-04918 Rev.*D Page 135 of 160
MB9B160R Series
12.4.15 SD Card Interface Timing
Default-Speed Mode
Clock CLK (All values are referred to VIH and VIL) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Remarks
Min
Max
Clock frequency Data Transfer Mode
fPP
S_CLK
CCARD ≤ 10pF
(1card)
0
16
MHz
Clock frequency Identification Mode
fOD
S_CLK
0*/100
400
kHz
Clock low time
tWL
S_CLK
10
-
ns
Clock high time
tWH
S_CLK
10
-
ns
Clock rising time
tTLH
S_CLK
-
10
ns
Clock falling time
tTHL
S_CLK
-
10
ns
*: 0Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is required.
Card Inputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin name
Conditions
Value
Remarks
Min
Max
Input set-up time
tISU
S_CMD,
S_DATA3:0
CCARD ≤ 10pF
(1card)
5
-
ns
Input hold time
tIH
S_CMD,
S_DATA3:0
5
-
ns
Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin name
Conditions
Value
Remarks
Min
Max
Output Delay time during Data Transfer
Mode
tODLY
S_CMD,
S_DATA3:0
CCARD ≤ 40pF
(1card)
0
22
ns
Output Delay time durinn Identification
Mode
tODLY
S_CMD,
S_DATA3:0
0
50
ns
Defalt-Speed Mode
Note:
− The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the
Host.
VIL
VIL
tWL
tWH
VIH
VIH
VIH
tTHL
tTLH
tISU
VIH
VIL
VIH
VIL
tIH
VOH
VOL
VOH
VOL
tODLY(Max)
tODLY(Min)
S_CLK
(SD Clock)
S_CMD,
S_DATA3:0
(Card Input)
S_CMD,
S_DATA3:0
(Card Output)
Document Number: 002-04918 Rev.*D Page 136 of 160
MB9B160R Series
High-Speed Mode
Clock CLK (All values are referred to VIH and VIL) (VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Remarks
Min
Max
Clock frequency Data Transfer Mode
fPP
S_CLK
CCARD ≤ 10pF
(1card)
0
32
MHz
Clock low time
tWL
S_CLK
7
-
ns
Clock high time
tWH
S_CLK
7
-
ns
Clock rising time
tTLH
S_CLK
-
3
ns
Clock falling time
tTHL
S_CLK
-
3
ns
Card Inputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin name
Conditions
Value
Remarks
Min
Max
Input set-up time
tISU
S_CMD,
S_DATA3:0
CCARD ≤ 10pF
(1card)
8
-
ns
Input hold time
tIH
S_CMD,
S_DATA3:0
2
-
ns
Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin name
Conditions
Value
Remarks
Min
Max
Output Delay time during Data Transfer
Mode
tODLY
S_CMD,
S_DATA3:0
CL ≤ 40pF
(1card)
-
22
ns
Output Hold time
tOH
S_CMD,
S_DATA3:0
CL ≥ 15pF
(1card)
2.5
-
ns
Total System capacitance for each line*
CL
-
1card
-
40
pF
*: In order to satisfy severe timing, host shall drive only one card.
High-Speed Mode
Notes:
− The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the
Host.
− In high-speed mode, set the Clock frequency (fPP) and the AHB Bus Clock frequency to the same values.
VIL
VIL
tWL
tWH
VIH
VIH
VIH
tTHL
tTLH
tISU
VIH
VIL
VIH
VIL
tIH
VOH
VOL
VOH
VOL
tODLY(Max)
tOH(Min)
50%VCC
50%VCC
S_CLK
(SD Clock)
S_CMD,
S_DATA3:0
(Card Input)
S_CMD,
S_DATA3:0
(Card Output)
Document Number: 002-04918 Rev.*D Page 137 of 160
MB9B160R Series
12.4.16 ETM Timing (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Max
Data hold
tETMH
TRACECLK,
TRACED[3:0]
VCC ≥ 4.5V
2
9
ns
VCC < 4.5V
2
15
TRACECLK
frequency
1/ tTRACE
TRACECLK
VCC ≥ 4.5V
-
50
MHz
VCC < 4.5V
-
32
MHz
TRACECLK
clock cycle
tTRACE
VCC ≥ 4.5V
20
-
ns
VCC < 4.5V
31.25
-
ns
Note:
− When the external load capacitance CL = 30pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-04918 Rev.*D Page 138 of 160
MB9B160R Series
12.4.17 JTAG Timing (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Max
TMS, TDI setup time
tJTAGS
TCK,
TMS, TDI
VCC ≥ 4.5V
15
-
ns
VCC < 4.5V
TMS, TDI hold time
tJTAGH
TCK,
TMS, TDI
VCC ≥ 4.5V
15
-
ns
VCC < 4.5V
TDO delay time
tJTAGD
TCK,
TDO
VCC ≥ 4.5V
-
25
ns
VCC < 4.5V
-
45
Note:
− When the external load capacitance CL = 30pF.
TCK
TMS/TDI
TDO
Document Number: 002-04918 Rev.*D Page 139 of 160
MB9B160R Series
12.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V)
Parameter
Symbol
Pin name
Value
Unit
Remarks
Min
Typ
Max
Resolution
-
-
-
-
12
bit
Integral Nonlinearity
-
-
- 4.5
-
+ 4.5
LSB
AVRH = 2.7V to
5.5V
Differential Nonlinearity
-
-
-2.5
-
+ 2.5
LSB
Zero transition voltage
VZT
ANxx
- 15
-
+ 15
mV
Full-scale transition
voltage
VFST
ANxx
AVRH - 15
-
AVRH + 15
mV
Conversion time
-
-
0.5*1
-
-
μs
AVCC ≥ 4.5V
Sampling time*2
Ts
-
0.15
-
10
μs
AVCC ≥ 4.5V
0.3
-
AVCC < 4.5V
Compare clock cycle*3
Tcck
-
25
-
1000
ns
AVCC ≥ 4.5V
50
-
1000
AVCC < 4.5V
State transition time to
operation permission
Tstt
-
-
-
1.0
μs
Power supply current
(analog + digital)
-
AVCC
-
0.69
0.92
mA
A/D 1unit operation
-
1.0
18
μA
When A/D stop
Reference power supply
current
(AVRH)
-
AVRH
-
1.1
1.97
mA
A/D 1unit operation
AVRH = 5.5V
0.3
6.3
μA
When A/D stop
Analog input capacity
CAIN
-
-
-
12.05
pF
Analog input resistance
RAIN
-
-
-
1.2
kΩ
AVCC ≥ 4.5V
1.8
AVCC < 4.5V
Interchannel disparity
-
-
-
-
4
LSB
Analog port input leak
current
-
ANxx
-
-
5
μA
Analog input voltage
-
ANxx
AVSS
-
AVRH
V
Reference voltage
-
AVRH
4.5
-
AVCC
V
Tcck < 50ns
2.7
-
AVCC
Tcck ≥ 50ns
*1: The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is when the value of sampling time: 150ns, the value of compare time: 350ns
(AVCC ≥ 4.5V). Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting*4 of sampling
time and compare clock cycle, see "Chapter: A/D Converter" in "FM4 Family PERIPHERAL MANUAL Analog Macro Part". The
register setting of the A/D Converter is reflected by the peripheral clock timing. The sampling and compare clock are set at Base
clock (HCLK).
*2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1).
*3: The compare time (Tc) is the value of (Equation 2).
*4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock. The sampling clock and compare clock
are set in base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see “Block Diagram”
in this data sheet.
Document Number: 002-04918 Rev.*D Page 140 of 160
MB9B160R Series
(Equation 1) Ts ≥ (RAIN + Rext ) × CAIN × 9
Ts: Sampling time
RAIN: Input resistance of A/D = 1.2kΩ at 4.5V < AVCC < 5.5V
Input resistance of A/D = 1.8kΩ at 2.7V < AVCC < 4.5V
CAIN: Input capacity of A/D = 12.05pF at 2.7V < AVCC < 5.5V
Rext: Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc: Compare time
Tcck: Compare clock cycle
RAIN
CAIN
Analog signal
source
Rext
ANxx
Analog input pin
Comparator
Document Number: 002-04918 Rev.*D Page 141 of 160
MB9B160R Series
Definition of 12-bit A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001)
and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual
conversion characteristics.
Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code
by 1 LSB.
Integral Nonlinearity of digital output N =
VNT - {1LSB × (N - 1) + VZT}
[LSB]
1LSB
Differential Nonlinearity of digital output N =
V(N + 1) T - VNT
- 1 [LSB]
1LSB
1LSB =
VFST - VZT
4094
N: A/D converter digital output value.
VZT: Voltage at which the digital output changes from 0x000 to 0x001.
VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Integral Nonlinearity
Differential Nonlinearity
Digital output
Digital output
Actual conversion
characteristics
Actual conversion
characteristics
Ideal characteristics
(Actually-
measured
value)
Actual conversion
characteristics
Actual conversion characteristics
(Actually-measured
value)
(Actually-measured value)
Ideal characteristics
(Actually-measured
value)
Analog input
Analog input
(Actually-measured
value)
0x001
0x002
0x003
0x004
0xFFD
0xFFE
0xFFF
AVss
AVRH
AVss
AVRH
0x(N-2)
0x(N-1)
0x(N+1)
0xN
{1 LSB(N-1) + VZT}
VNT
VFST
VZT
VNT
V(N+1)T
Document Number: 002-04918 Rev.*D Page 142 of 160
MB9B160R Series
12.6 12-bit D/A Converter
Electrical Characteristics for the D/A Converter (VCC = AVCC = 2.7Vto5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
name
Value
Unit
Remarks
Min
Typ
Max
Resolution
-
DAx
-
-
12
bit
Conversion time
tc20
0.56
0.69
0.81
μs
Load 20pF
tc100
2.79
3.42
4.06
μs
Load 100pF
Integral Nonlinearity*
INL
- 16
-
+ 16
LSB
Differential Nonlinearity*
DNL
- 0.98
-
+ 1.5
LSB
Output voltage offset
VOFF
-
-
10.0
mV
When setting 0x000
- 20.0
-
+ 1.4
mV
When setting 0xFFF
Analog output impedance
RO
3.10
3.80
4.50
kΩ
D/A operation
2.0
-
-
MΩ
When D/A stop
Power supply current*
IDDA
AVCC
260
330
410
μA
D/A 1unit operation AVCC = 3.3V
400
510
620
μA
D/A 1unit operation AVCC = 5.0V
IDSA
-
-
14
μA
When D/A stop
*: During no load
Document Number: 002-04918 Rev.*D Page 143 of 160
MB9B160R Series
12.7 Low-Voltage Detection Characteristics
12.7.1 Low-Voltage Detection Reset
Parameter
Symbol
Conditions
Value
Unit
Remarks
Min
Typ
Max
Detected voltage
VDL
-
2.25
2.45
2.65
V
When voltage drops
Released voltage
VDH
-
2.30
2.50
2.70
V
When voltage rises
12.7.2 Interrupt of Low-Voltage Detection
Parameter
Symbol
Conditions
Value
Unit
Remarks
Min
Typ
Max
Detected voltage
VDL
SVHI = 00111
2.58
2.8
3.02
V
When voltage drops
Released voltage
VDH
2.67
2.9
3.13
V
When voltage rises
Detected voltage
VDL
SVHI = 00100
2.76
3.0
3.24
V
When voltage drops
Released voltage
VDH
2.85
3.1
3.34
V
When voltage rises
Detected voltage
VDL
SVHI = 01100
2.94
3.2
3.45
V
When voltage drops
Released voltage
VDH
3.04
3.3
3.56
V
When voltage rises
Detected voltage
VDL
SVHI = 01111
3.31
3.6
3.88
V
When voltage drops
Released voltage
VDH
3.40
3.7
3.99
V
When voltage rises
Detected voltage
VDL
SVHI = 01110
3.40
3.7
3.99
V
When voltage drops
Released voltage
VDH
3.50
3.8
4.10
V
When voltage rises
Detected voltage
VDL
SVHI = 01001
3.68
4.0
4.32
V
When voltage drops
Released voltage
VDH
3.77
4.1
4.42
V
When voltage rises
Detected voltage
VDL
SVHI = 01000
3.77
4.1
4.42
V
When voltage drops
Released voltage
VDH
3.86
4.2
4.53
V
When voltage rises
Detected voltage
VDL
SVHI = 11000
3.86
4.2
4.53
V
When voltage drops
Released voltage
VDH
3.96
4.3
4.64
V
When voltage rises
LVD stabilization wait time
TLVDW
-
-
-
4480×tCYCP*
μs
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-04918 Rev.*D Page 144 of 160
MB9B160R Series
12.8 MainFlash Memory Write/Erase Characteristics (VCC = 2.7V to 5.5V)
Parameter
Value
Unit
Remarks
Min
Typ
Max
Sector erase time
Large Sector
-
0.7
3.7
s
Includes write time prior to internal erase
Small Sector
0.3
1.1
Half word (16-bit)
write time
Write cycles
< 100 times
-
12
100
μs
Not including system-level overhead time
Write cycles >
100 times
200
Chip erase time
-
13.6
68
s
Includes write time prior to internal erase
Write cycles and data hold time
Erase/Write cycles (cycle)
Data hold time (year)
1,000
20 *
10,000
10 *
100,000
5 *
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test
result into average temperature value at + 85°C) .
12.9 WorkFlash Memory Write/Erase Characteristics (VCC = 2.7V to 5.5V)
Parameter
Value
Unit
Remarks
Min
Typ
Max
Sector erase time
-
0.3
1.5
s
Includes write time prior to internal erase
Half word (16-bit)
write time
-
20
200
μs
Not including system-level overhead time
Chip erase time
-
1.2
6
s
Includes write time prior to internal erase
Write cycles and data hold time
Erase/Write cycles (cycle)
Data hold time (year)
1,000
20 *
10,000
10 *
100,000
5 *
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test
result into average temperature value at + 85°C) .
Document Number: 002-04918 Rev.*D Page 145 of 160
MB9B160R Series
12.10 Standby Recovery Time
12.10.1 Recovery cause: Interrupt/WKUP
The time from recovery cause reception of the internal circuit to the program operation start is shown.
Recovery count time (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Value
Unit
Remarks
Typ
Max*
Sleep mode
Ticnt
HCLK×1
μs
High-speed CR Timer mode
Main Timer mode
PLL Timer mode
40
80
μs
Low-speed CR timer mode
450
900
μs
Sub timer mode
896
1136
μs
RTC mode
stop mode
(High-speed CR /Main/PLL run mode return)
316
581
μs
RTC mode
stop mode
(Low-speed CR/sub run mode return)
270
540
Deep standby RTC mode with RAM retention
Deep standby stop mode with RAM retention
365
667
μs
without RAM
retention
365
667
μs
with RAM
retention
*: The maximum value depends on the built-in CR accuracy.
Example of standby recovery operation (when in external interrupt recovery*)
Ext.INT
Ticnt
Interrupt factor
accept
CPU
Operation Start
Active
Interrupt factor
clear by CPU
*: External interrupt is set to detecting fall edge.
Document Number: 002-04918 Rev.*D Page 146 of 160
MB9B160R Series
Example of standby recovery operation (when in internal resource interrupt recovery*)
Internal
Resource INT
Ticnt
Interrupt factor
accept
CPU
Operation Start
Active
Interrupt factor
clear by CPU
*: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause.
Notes:
− The return factor is different in each Low-Power consumption modes.
See “Chapter: Low Power Consumption Mode” and “Operations of Standby Modes” in FM4 Family Peripheral Manual.
− When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See “Chapter: Low Power Consumption Mode” in “FM4 Family Peripheral Manual”.
Document Number: 002-04918 Rev.*D Page 147 of 160
MB9B160R Series
12.10.2 Recovery cause: Reset
The time from reset release to the program operation start is shown.
Recovery count time (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Value
Unit
Remarks
Typ
Max*
Sleep mode
Trcnt
155
266
μs
High-speed CR Timer mode
Main Timer mode
PLL Timer mode
155
266
μs
Low-speed CR timer mode
315
567
μs
Sub timer mode
315
567
μs
RTC mode
stop mode
315
567
μs
Deep standby RTC mode with RAM retention
Deep standby stop mode with RAM retention
336
667
μs
without RAM
retention
μs
with RAM
retention
*: The maximum value depends on the built-in CR accuracy.
Example of standby recovery operation (when in INITX recovery)
INITX
Trcnt
Internal RST
CPU
Operation Start
RST Active Release
Document Number: 002-04918 Rev.*D Page 148 of 160
MB9B160R Series
Example of standby recovery operation (when in internal resource reset recovery*)
Internal
Resource RST
Trcnt
Internal RST
CPU
Operation Start
RST Active Release
*: Depending on the standby mode, the reset issue from the internal resource is not included in the recovery cause.
Notes:
− The return factor is different in each Low-Power consumption modes.
See “Chapter: Low Power Consumption Mode” and “Operations of Standby Modes” in FM4 Family Peripheral Manual.
− The time during the power-on reset/low-voltage detection reset is excluded to the recovery source. See “12.4.7 Power-on
Reset Timing” in “12.4. AC Characteristics” in “12.Electrical Characteristics" for the detail on the time during the power-on
reset/low-voltage detection reset.
− When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.
− The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-04918 Rev.*D Page 149 of 160
MB9B160R Series
13. Ordering Information
Part Number
Flash
RAM
Package
MB9BF168MPMC-G-JNE2
1 MB
128 KB
Plastic・LQFP (0.5 mm pitch), 80 pin
(LQH080)
MB9BF167MPMC-G-JNE2
768 KB
96 KB
MB9BF166MPMC-G-JNE2
512 KB
64 KB
MB9BF168MPMC1-G-JNE2
1 MB
128 KB
Plastic・LQFP (0.65 mm pitch), 80 pin
(LQJ080)
MB9BF167MPMC1-G-JNE2
768 KB
96 KB
MB9BF166MPMC1-G-JNE2
512 KB
64 KB
MB9BF168NPMC-G-JNE2
1 MB
128 KB
Plastic・LQFP (0.5 mm pitch), 100 pin
(LQI100)
MB9BF167NPMC-G-JNE2
768 KB
96 KB
MB9BF166NPMC-G-JNE2
512 KB
64 KB
MB9BF168RPMC-G-JNE2
1 MB
128 KB
Plastic・LQFP (0.5 mm pitch), 120 pin
(LQM120)
MB9BF167RPMC-G-JNE2
768 KB
96 KB
MB9BF166RPMC-G-JNE2
512 KB
64 KB
MB9BF168NBGL-GE1
1 MB
128 KB
Plastic・PFBGA (0.5 mm pitch), 112 pin
(LDC112)
MB9BF167NBGL-GE1
768 KB
96 KB
MB9BF166NBGL-GE1
512 KB
64 KB
MB9BF168RBGL-GK7E1
1 MB
128 KB
Plastic・PFBGA (0.5 mm pitch), 144 pin
(LDC144)
MB9BF167RBGL-GK7E1
768 KB
96 KB
MB9BF166RBGL-GK7E1
512 KB
64 KB
MB9BF168NPQC-G-JNE2
1 MB
128 KB
Plastic・QFP (0.65 mm pitch), 100 pin
(PQH100)
MB9BF167NPQC-G-JNE2
768 KB
96 KB
MB9BF166NPQC-G-JNE2
512 KB
64 KB
Document Number: 002-04918 Rev.*D Page 150 of 160
MB9B160R Series
14. Package Dimensions
Package Type
Package Code
LQFP-120
LQM120
M IN. NOM . M AX.
07.1A
A1 0.05 0.15
b 0.17 0.22 0.27
c0.115 0.195
D 18.00 BSC
D1 16.00 BSC
e0.50 BSC
E
E1
L 0.45 0.60 0.75
18.00 BSC
16.00 BSC
DIM ENSIONS
SYM BOL
θ0°8°
SIDE VIEW
BOTTOM VIEW
TOP VIEW
1
120
D1
D
e
EE1
0.20 C A -B D
0.10 C A -B D
0.08 C A-B D
b
0.08 C
SEATI NG
PLA NE
A
A'
θ
A
A1
0.25 10
L
b
SEC TION A -A'
c
9
4
57
3
4
5
7
3
8
7
5
2
2
6
30
31
60
6190
91
130
31
60
0916
91
PACKAGE OUTLINE, 120 LEAD LQFP
18.0X18.0X1.7 M MLQM120 REV**
002-16172 **
Document Number: 002-04918 Rev.*D Page 151 of 160
MB9B160R Series
Package Type
Package Code
LQFP-100
LQI100
NOTES :
1. ALL DIM ENSIONS ARE IN M ILLIM ETERS.
2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE M OLD PARTING
LINE COINCIDENT W ITH W HERE THE LEAD EXITS THE BODY.
3. DATUM S A-B AND D TO BE DETERM INED AT DATUM PLANE H.
4. TO BE DETERM INED AT SEATING PLAN E C.
5. DIM ENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRU SION.
ALLOW ABLEPROTRUSION IS 0.25mm PRE SIDE.
DIM ENSIONS D1 AND E1 INCLUDE MOLD MISMATCH AND ARE DETERM INED
AT DATUM PLANE H.
6. DETAILS OF PIN 1 ID ENTIFIER ARE OPTION AL BUT M UST BE LOCATED
W ITHIN THEZONE INDICATED.
7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOW ER BODY
SECTIONS. DIM ENSIONS D1 AND E1 ARE DETERM INED AT THE LARGEST
FEATURE OF THE BODY EXCLUSIVE OF M OLD FLASH AND GATE BURRS.
BUT INCLUDIN G AN Y M ISM ATCH BETW EEN THE UPPER AND LOW ER
SECTIONS OF THE M OLDER BODY.
8. DIM ENSION b DOES NOT INCLUDE DAM BAR PROTRUSION. THE DAM BAR
PROTRUSION (S) SHALL NOT CAUSE THE LEAD W IDTH TO EXCEED b
M AXIM UM BY M ORE THAN 0.08m m . D AM BAR CANN OT BE LOCATED ON
THE LOW ER RADIUS OR THE LEAD FOOT.
9. THESE DIM ENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETW EEN 0.10mm AND 0.25m m FROM THE LEAD TIP.
10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO
THE LOW EST POINT OF THE PACKAGE BODY.
DIM ENSIONS
SYM BOL MIN. NOM . M AX.
A1.70
A1 0.05 0.15
b 0.15 0.27
c 0.09 0.20
D 16.00 BSC
D1 14.00 BSC
e0.50 BSC
E
E1
L 0.45 0.60 0.75
L1 0.30 0.50 0.70
16.00 BSC
14.00 BSC
A
A1
0.25
0.0 8 C
1
100
D1
D
E1 E
e
4
4
0.0 8 C A-B D
7
5
SEATING
PLA N E
0.2 0 C A-B D
0.1 0 C A -B D
b
SECTION A-A '
c
9
A
A'
57
5
7
3
3
6
8
10
2
2
L1
L
b
D1
D
E1 E
4
4
57
5
7
25
26
50
5175
76
SIDE VIEW
TOP VIEW
BOTTOM VIEW
DETAIL A
1
25
26
50
5715
100
76
PACKAGE OUTLINE, 100 LEAD LQFP
14.0X14.0X1.7 MM LQI100 REV*A
002-11500 *A
Document Number: 002-04918 Rev.*D Page 152 of 160
MB9B160R Series
Package Type
Package Code
QFP-100
PQH100
DIM ENSIONS
SYMBOL M IN . NO M . M AX.
A 3.35
A1 0.05 0.45
b 0.27 0.32 0.37
c 0.11 0.23
D 23.90 BSC
D1 20.00 BSC
e 0.65BSC
E
E1
L0.73 0.88 1.03
L1 1.95 REF
L2 0.25 BSC
17.90 BSC
14.00 BSC
0°8°
θ
L2
031
100
e
b
D1
D
57
4
EE1
36
4
5
7
0.20 C A-B D
7
5
2
0.13 C A-B D 8
0.40 C A-B D 3
2
SEATING
PLANE
b
SECTION A-A'
c
9
SID E VIEW
TOP VIEW
A
A'
0.10 C
θ
10
DETAIL A
31
50
5180
81
130
100
31
50
0815
81
BOTTOM VIEW
PACKAGE OUTLINE, 100 LEAD Q FP
20.00X14.00X3 .35 MM PQH100 REV**
002-15156 **
Document Number: 002-04918 Rev.*D Page 153 of 160
MB9B160R Series
Package Type
Package Code
LQFP-80
LQH080
DIM ENSIONS
M IN. NOM . M AX.
07.1A
A1 0.05 0.15
b 0.15 0.27
c 0.09 0.20
D 14.00 BSC.
D1 12.00 BSC.
e0.50 BSC
E
E1
L0.45 0.60 0.75
L1 0.30 0.50 0.70
14.00 BSC.
12.00 BSC.
SYMBOL
BOTTOM VIEW
A
A1
0.25
1
80
D1
D
e
b
D
0.2 0 C A-B D
0.1 0 C A -B D
0.0 8 C A-B D
E
E1
4
57
3
4
5
7
3
8
7
5
2
10 b
SECTION A-A'
c
9
2
SEATIN G
PLANE
0.0 8 C
A
A'
6
L1
L
SIDE VIEW
TOP VIEW
20
21
40
1406
61
0614
80
61
21
40
1
20
PACKAGE OUTLINE, 80 LEAD LQFP
12.0X12.0X1.7 MM LQH080 Rev **
002-11501 **
Document Number: 002-04918 Rev.*D Page 154 of 160
MB9B160R Series
Package Type
Package Code
LQFP-80
LQJ080
DIM ENSIONS
SYMBOL M IN. NOM . MAX.
A1.70
A1 0.00 0.20
b 0.16 0.38
c 0.09 0.20
D 16.00 BSC
D1 14.00 BSC
e0.65 BSC
E
E1
L 0.45 0.60 0.75
L1 0.30 0.50 0.70
16.00 BSC
14.00 BSC
0.32
0°8°
θ
D1
D
e
021
80
EE1
4
5
7
4
57
3
0.2 0 C A-B D
3
b
0.1 0 C A-B D
8
7
5
2
2
A
A'
SEATING
PLANE
θ
A
A1
0.2 5 10 b
SECTION A-A'
c
9
L1
L
6
0.1 0 C
ddd C A-B D
1
21
40
4160
61
20
21
40
0614
80
61
14.0X14.0X1.7 MM LQJ080 REV**
PACKAGE OUTLINE, 80 LEAD LQFP
002-14043 **
Document Number: 002-04918 Rev.*D Page 155 of 160
MB9B160R Series
Package Type
Package Code
BGA-112
LDC112
002-16663 **
2. DIM ENSIONS AND TOLERANCES METHODS PER ASM E Y14.5-2009.
THIS OUTLINE CONFORM S TO JEP95, SECTION 4.5.
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-010.
4. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYM BOL "M D"IS THE BALL MATRIX SIZE IN THE "D"DIRECTION.
SYM BOL "M E" IS THE BALL M ATRIX SIZE IN THE "E"DIRECTION.
n IS THE NUM BER OF POPULATED SOLDER BALL POSITIONS FOR M ATRIX
SIZE M D X ME.
6. DIM ENSION "b "IS M EASURED AT THE M AXIM UM BALL DIAM ETER
IN A PLANE PARALLEL TO DATUM C.
7. "SD" AND "SE" ARE M EASURED W ITH RESPECT TO DATUM S A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW .
W HEN THERE IS AN ODD NUM BER OF SOLDER BALLS IN THE OUTER ROW ,
"SD"OR "SE"= 0.
W HEN THERE IS AN EVEN NUM BER OF SOLDER BALLS IN THE OUTER ROW ,
"SD"= eD/2 A ND "SE"= eE/2.
1. ALL DIM ENSION S ARE IN M ILLIM ETERS.
8. A1 CORNER TO BE IDENTIFIED BY CHAM FER, LASER OR INK MARK.
M ETALLIZED M ARK INDENTATION OR OTHER M EANS.
9. "+ " INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
NOM .MIN.
E 7.00 BSC
D
A
1
A
7.00 BSC
SYM BOL
MAX.
1.35
DIM ENSIONS
0.15
D1
E1
ME
MD
n
13
13
112
Φb0.20 0.400.30
eE
eD
SD / SE
0.50 BSC
0.50 BSC
0.00
6.00 BSC
6.00 BSC
0.25 0.35
NOTES
A
0.20 C A
B
0.20 C B
INDEX MARK
PIN A 1
CORNER 8112xφb0.05 C A B
6
7
7
DETAIL A
SIDE VIEW
0.20 C
0.10 C C
DETAIL A
BOTTOM VIEWTOP VIEW
1
2
3
4
5
6
7
8
9
10
11
ABCDEFGH
J
KLMN
12
13
7.0X7.0X1.35 MM LD C112 REV**
PACKAGE OUTLINE, 112 BALL FBGA
Document Number: 002-04918 Rev.*D Page 156 of 160
MB9B160R Series
Package Type
Package Code
BGA-144
LDC144
002-16662 **
2. DIM ENSIONS AND TOLERANCES METHODS PER ASM E Y14.5-2009.
THIS OUTLINE CONFORM S TO JEP95, SECTION 4.5.
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-010.
4. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYM BOL "M D"IS THE BALL MATRIX SIZE IN THE "D"DIRECTION.
SYM BOL "M E" IS THE BALL M ATRIX SIZE IN THE "E"DIRECTION.
n IS THE NUM BER OF POPULATED SOLDER BALL POSITIONS FOR M ATRIX
SIZE M D X ME.
6. DIM ENSION "b "IS M EASURED AT THE M AXIM UM BALL DIAM ETER
IN A PLANE PARALLEL TO DATUM C.
7. "SD" AND "SE" ARE M EASURED W ITH RESPECT TO DATUM S A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW .
W HEN THERE IS AN ODD NUM BER OF SOLDER BALLS IN THE OUTER ROW ,
"SD"OR "SE"= 0.
W HEN THERE IS AN EVEN NUM BER OF SOLDER BALLS IN THE OUTER ROW ,
"SD"= eD/2 A ND "SE"= eE/2.
1. ALL DIM ENSION S ARE IN M ILLIM ETERS.
8. A1 CORNER TO BE IDENTIFIED BY CHAM FER, LASER OR INK MARK.
M ETALLIZED M ARK INDENTATION OR OTHER M EANS.
9. "+ " INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
NOM .MIN.
E 7.00 BSC
D
A
1
A
7.00 BSC
SYM BOL
MAX.
1.30
DIM ENSIONS
0.15
D1
E1
ME
MD
n
13
13
144
Φb0.20 0.400.30
eE
eD
SD / SE
0.50 BSC
0.50 BSC
0.00
6.00 BSC
6.00 BSC
0.25 0.35
NOTES
A
0.20 C A
2X
B
0.20 C B
2X
INDEX MARK
PIN A 1
CORNER 8144xφb0.05 C A B
6
7
7
DETAIL A
SIDE VIEW
0.20 C
0.08 C C
DETAIL A
BOTTOM VIEWTOP VIEW
1
2
3
4
5
6
7
8
9
10
11
ABCDEFGH
J
KLMN
12
13
7.0X7.0X1.3 MM LD C144 REV**
PACKAGE OUTLINE, 144 BALL FBGA
Document Number: 002-04918 Rev.*D Page 157 of 160
MB9B160R Series
15. Major Changes
Spansion Publication Number: DS709-00004
Page
Section
Change Results
-
-
Preliminary → Data Sheet
1
Description
Deleted the following description :
The products which are described in this data sheet are placed into
TYPE4 product categories in "FM4
Family PERIPHERAL MANUAL".
3
Features
Multi-Function Serial Interface
[I2c]
Revised the following description :
Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3 and ch.7)
supported
→Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A and
ch.7=ch.B) supported
7
Features
Unique Id
Added new section
9
Product Lineup
Function
Added “Unique ID”
51, 52
I/O Circuit Type
Revised the remarks of “Type O, P, Q”
59
Handling Devices
Handling When Using Debug Pins
Added new section
60
Block Diagram
Revised the block diagram
72
Electrical Characteristics
2. Recommended Operating Conditions
Revised “Table for package thermal resistance and maximum
permissible power”
75 to 80
Electrical Characteristics
3. Dc Characteristics
(1) Current Rating
• Revised the value of TBD
• Added the note to “ICCVBAT”
85
Electrical Characteristics
4. Ac Characteristics
(2) Sub Clock Input Characteristics
Revised the waveform chart
85
Electrical Characteristics
4. Ac Characteristics
(3) Built-In Cr Oscillationcharacteristics
• Revised the value of TBD
• Revised the table and the note of “Built-in High-speed CR”
144
Electrical Characteristics
5. 12-Bit A/D Converter
Electrical Characteristics For The A/D Converter
• Revised the value of TBD
• Revised the condition of the electrical characteristics table
147
Electrical Characteristics
6. 12-Bit D/A Converter
Electrical Characteristics For The D/A Converter
• Revised the value of TBD
• Revised the condition and Remarks of the electrical characteristics
table
150
Electrical Characteristics
10. Standby Recovery Time
(1) Recovery Cause: Interrupt/Wkup
• Revised the value of TBD
• Revised the table of Recovery count time
152
Electrical Characteristics
10. Standby Recovery Time
(2) Recovery Cause:Reset
• Revised the value of TBD
• Revised the table of Recovery count time
Note: Please see “Document History” about later revised information.
Document Number: 002-04918 Rev.*D Page 158 of 160
MB9B160R Series
Document History
Document Title: MB9B160R Series 32-bit ARM® Cortex®-M4F FM4 Microcontroller
Document Number: 002-04918
Revision
MB9B160R
Series ECN
Orig. of
Change
Submission
Date
Description of Change
**
–
AKIH
06/27/2013
Migrated to Cypress and assigned document number 002-04918.
No change to document contents or format.
*A
5162380
AKIH
03/07/2016
Updated to Cypress format.
*B
5516291
YSKA
02/02/2017
Updated “12.4.7 Power-On Reset Timing”. Changed parameter from
“Power Supply rise time(Tr)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and add some
comments (Page 84)
Modified the Chapter name “12.4.11 UART Timing” to “12.4.11 CSIO/UART Timing”.
(Page 97)
Modified “12.4.11 CSIO/UART Timing)”. Deleted “SPI=1, MS=0” in the titles and
added MS=0,1 in the schematic (Page 105-112, 121-128)
Added the Baud rate spec in “12.4.12 CSIO/UART Timing”.(Page 97, 99, 101, 103)
“Modified RTC description in “Features, Real-Time Clock(RTC)”
Changed starting count value from 01 to 00. Deleted “second , or day of the week” in
the Interrupt function (Page 3)
Added Maximum Access size in “Features”(Page 1)
Modifications related to the VBAT in the following chapter.
“7. Handling Devices” Notes on Power-on (Page 54) “11. Pin Status in Each CPU
State” List of VBAT Domain Pin Status (Page 66) “12.3.1 Current Rating” Table12-9.
Typical and Maximum Current Consumption in Deep Standby STOP Mode, Deep
Standby RTC Mode and VBAT (Page 77)
Added Notes for JTAG (Page 42), Changed “J-TAG” to” JTAG” in “4 List of Pin
Functions” (Page 30)
Modify typo in number of power supply(Three -> Two) (Page 4)
Updated Package code and dimensions as follows (Page 8-14, 68, 150-156)
FPT-120P-M37 -> LQM120, FPT-100P-M23 -> LQI100,
FPT-100P-M36 -> PQH100, FPT-80P-M37 -> LQH080,
FPT-80P-M40 -> LQJ080, BGA-112P-M05 -> LDC112,
BGA-144P-M09 -> LDC144
Changed the mode name of I2C as follows (Page 2, 133-134)
Typical mode -> Standard-mode, High-speed mode -> Fast-mode
Modified from “Analog port input current” to “Analog port input leak current” in “12.5
12-bit A/D Converter” (Page 139)
Modified according to the Datasheet Errata as below (No.1-9)
1. Modified Reference voltage value in “Electrical Characteristics for the A/D
Converter” in “12.5 12-bit A/D Converter” (Page 139)
2. Modified typo in “Features, Processor version” (Page 1)
3. Updated Remarks of Type H, I in “5. I/O Circuit Type” (Page 45)
4. Updated “List of VBAT Domain Pin Status” (Page 66)
5. Modified “12.2 Recommended Operating Conditions” (Page 68)
6. Added “Frequency stabilization time” spec in “12.4.3 Built-in CR Oscillation
Document Number: 002-04918 Rev.*D Page 159 of 160
MB9B160R Series
Revision
MB9B160R
Series ECN
Orig. of
Change
Submission
Date
Description of Change
Characteristics” (Page 82)
7. Added “Conversion time” spec in “12.6 12-bit D/A Converter” (Page 142)
8. Modified some spec values in “12.10.1 Recovery cause: Interrupt/WKUP” (Page
145) and “12.10.2 Recovery cause: Reset” (Page 147)
9. Modified the “sampling time” and “State transition time to operation permission”
spec values in ”12.5 12-bit A/D Converter”(Page 139)
Deleted MPNs below from “13. Ordering Information” (Page 149)
MB9BF166RBGL-GE1, MB9BF167RBGL-GE1, MB9BF168RBGL-GE1
Added MPNs below to “13. Ordering Information” (Page 149)
MB9BF166RBGL-GK7E1, MB9BF167RBGL-GK7E1, MB9BF168RBGL-GK7E1
Updated IO circuit (type A, N, O) (Page 43)
Modified the expression of the “Reference power supply current” “12.5 12-bit A/D
Converter” (Page 139)
Modified the expression of the “Built-in CR” and add Note in the “1. Product
Lineup”(Page 7)
Modified typo(SCLKx_0 -> SCKx_0)(Page 97, 99, 101, 103)
*C
5738077
YSAT
05/16/2017
Adapted new Cypress logo
*D
5873294
HUAL
09/25/2017
Fix minor issues listed in CDT 270742:
1.new note format had been updated from *x to *x
2.double heading number had been cancelled on chapter 12.2
3.some chapter number missed in reference
4.change this sentence “In between less than the minimum power supply
voltage and low voltage reset/interrupt detection voltage or more,
instruction execution and low voltage detection function by built-in
High-speed CR (including Main PLL is used) or built-in Low-speed CR is
possible to operate only” to sentence “Between less than the minimum
power supply voltage and low voltage reset/interrupt detection voltage,
instruction execution and low voltage detection function by built-in
High-speed CR (including Main PLL is used) or built-in Low-speed CR is
possible to operate”
Document Number: 002-04918 Rev.*D September 25, 2017 Page 160 of 160
MB9B160R Series
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