Preliminary UL62H1708A Low Voltage Automotive Fast 128K x 8 SRAM Features Description F 131072 x 8 bit static CMOS RAM F 35 and 55 ns Access Time F Common data inputs and The UL62H1708A is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-Transistor cell. The circuit is activated by the rising edge of E2 (at E1 = L), or the falling edge of E1 (at E2 = H). The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. During the active state (E1 = L and E2 = H) each address change leads to a new Read or Write cycle. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word will be available at the outputs DQ0-DQ7. After the address change, the data data outputs F Three-state outputs F Typ. operating supply current F F F F F F F F 35 ns: 45mA 55 ns: 30mA Standby current <100A at 125C TTL/CMOS-compatible Power supply voltage 3.3 V Operating temperature range -40 C to 85 C -40 C to 125 C CECC 90000 Quality Standard ESD protection > 2000 V (MIL STD 883C M3015.7) Latch-up immunity >100 mA Package: SOP32 (300/330 mil) Pin Configuration outputs go High-Z until the new information is available. The data outputs have no preferred state. If the memory is driven by CMOS levels in the active state, and if there is no change of the address, data input and control signals W or G, the operating current (IO = 0 mA) drops to the value of the operating current in the Standby mode. The Read cycle is finished by the falling edge of E2 or W, or by the rising edge of E1, respectively. Data retention is guaranteed down to 2 V. With the exception of E1 and E2, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. Pin Description n.c. 1 32 VCC A16 2 31 A15 A14 3 30 E2 A12 4 29 W A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 G A2 10 23 A10 A1 11 22 A0 12 DQ0 Signal Name Signal Description A0 - A16 Address Inputs DQ0 - DQ7 Data In/Out E1 E2 Chip Enable 1 Chip Enable 2 G Output Enable W VCC Write Enable E1 Power Supply Voltage 21 DQ7 VSS Ground 13 20 DQ6 n.c. not connected DQ1 14 19 DQ5 DQ2 15 18 DQ4 16 17 DQ3 VSS SOP Top View November 01, 2001 1 Row Decoder 1024 Rows x 128 x 8 Columns DQ0 Sense Amplifier/ Write Control Logic Address Change Detector DQ1 Common Data I/O A0 A1 A2 A3 A10 A5 A6 Memory Cell Array Column Decoder A7 A8 A9 A4 A11 A12 A13 A14 A15 A16 Column Address Inputs Block Diagram Preliminary Row Address Inputs UL62H1708A Clock Generator DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC Truth Table VSS E1 E2 W G Operating Mode E1 E2 W G DQ0 - DQ7 Standby/not selected * L * * High-Z H * * * High-Z Internal Read L H H H High-Z Read L H H L Data Outputs Low-Z Write L H L * Data Inputs High-Z * H or L Characteristics All voltages are referenced to V SS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 2.5 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured 200 mV from steady-state voltage. Maximum Ratings Symbol Min. Max. Unit VCC -0.3 4.6 V Input Voltage VI -0.5 VCC + 0.5 V Output Voltage VO -0.5 VCC + 0.5 V Power Dissipation PD - 1 W Ta -40 -40 85 125 C Tstg -65 150 C 100 mA Power Supply Voltage Operating Temperature Storage Temperature Output Short-Circuit Current at VCC = 3.3 V and VO = 0 V** K-Type A-Type | IOS | **Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s. 2 November 01, 2001 Preliminary UL62H1708A Recommended Operating Conditions Symbol Power Supply Voltage Input Low Voltage * Input High Voltage Conditions Min. Max. Unit VCC 3.0 3.6 V VIL -0.3 0.8 V VIH 2.0 VCC + 0.3 V Min. Max. Unit 90 70 60 mA mA mA 100 A 10 20 mA mA * -2 V at Pulse Width 10 ns Electrical Characteristics Supply Current - Operating Mode Symbol ICC(OP) Supply Current - Standby Mode (CMOS level) ICC(SB) Supply Current - Standby Mode (TTL level) ICC(SB)1 Conditions VCC VIL VIH tcW tcW tcW = = = = = = VCC = 3.6 V = VCC - 0.2 V VE1= VE2 VCC VE1= VE2 3.6 V 0.8 V 2.0 V 35 ns 55 ns 70 ns = 3.6 V = 2.0 V K-Type A-Type Output High Voltage VOH Output Low Voltage VOL Input High Leakage Current IIH Input Low Leakage Current IIL Output High Current IOH Output Low Current IOL Output Leakage Current High at Three-State Outputs IOHZ Low at Three-State Outputs IOLZ November 01, 2001 VCC IOH VCC IOL = 3.0 V = -0.5 mA = 3.0 V = 0.5 mA VCC VIH VCC VIL = 3.6 V = 3.6 V = 3.6 V = 0V VCC VOH VCC VOL = = = = VCC VOH VCC VOL = 3.6 V = 3.6 V = 3.6 V = 0V 3 3.0 V 2.0 V 3.0 V 0.4 V 2.2 V 0.4 V 2 A -2 A -0.5 0.5 mA 2 -2 mA A A UL62H1708A Switching Characteristics Read Cycle Preliminary Symbol 35 55 Unit Alt. IEC Min. Read Cycle Time tRC tcR 35 Address Access Time to Data Valid tAA ta(A) 35 55 ns Chip Enable Access Time to Data Valid tACE ta(E) 35 55 ns G LOW to Data Valid tOE ta(G) 15 25 ns E1 HIGH or E2 LOW to Output in High-Z tHZCE tdis(E) 12 15 ns G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns E1 LOW or E2 HIGH to Output in Low-Z tLZCE ten(E) 3 3 ns G LOW to Output in Low-Z tLZOE ten(G) 0 0 ns Output Hold Time from Address Change tOH tv(A) 3 3 ns E1 LOW or E2 HIGH to Power-Up Time tPU 0 0 ns E1 HIGH or E2 LOW to Power-Down Time tPD Switching Characteristics Write Cycle Max. Min. Max. 55 ns 35 Symbol 55 35 ns 55 Unit Alt. IEC Min. Write Cycle Time tWC tcW 35 55 ns Write Pulse Width tWP tw(W) 20 35 ns Write Setup Time tWP tsu(W) 20 35 ns Address Setup Time tAS tsu(A) 0 0 ns Address Valid to End of Write tAW tsu(A-WH) 20 40 ns Chip Enable Setup Time tCW tsu(E) 25 40 ns Pulse Width Chip Enable to End of Write tCW tw(E) 25 40 ns Data Setup Time tDS tsu(D) 15 25 ns Data Hold Time tDH th(D) 0 0 ns Address Hold from End of Write tAH th(A) 0 0 ns W LOW to Output in High-Z tHZWE tdis(W) 15 20 ns G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns W HIGH to Output in Low-Z tLZWE ten(W) 0 0 ns G LOW to Output in Low-Z tLZOE ten(G) 0 0 ns 4 Max. Min. Max. November 01, 2001 Preliminary UL62H1708A Data Retention Mode Data Retention Characteristics Symbol Conditions Alt. Min. 1.5 Data Retention Supply Voltage VCC(DR) Data Retention Supply Current ICC(DR) VCC(DR) = 2 V VE1 =VE2 = V CC(DR) - 0.2 V tCDR tsu(DR) tR trec See Data Retention Waveforms (below) Data Retention Setup Time Operating Recovery Time Data Retention Mode E1 - controlled VCC 3.0 V VCC(DR) 1.5 V 2.0 V tsu(DR) Data Retention 2.0 V E1 trec 0V VE2(DR) VCC(DR) - 0.2 V or V E2(DR) 0.2 V VCC(DR) - 0.2 V VE1(DR) V CC(DR) + 0.2 V Data Retention Mode E2 - controlled VCC 3.0 V VCC(DR) 1.5 V tDR Data Retention 0.8 V E2 trec 0.8 V 0V VE1(DR) VCC(DR) - 0.2 V or VE1(DR) 0.2 V VE2(DR) 0.2 V November 01, 2001 Typ. Max. Unit 3.6 V 30 A IEC 5 0 ns tcR ns UL62H1708A Preliminary Test Configuration for Functional Check VIL VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 481 VO 30 pF1 E1 E2 W G 1) Simultaneous measurement of all 8 output pins VIH Input level according to the relevant test measurement 3.3 V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 255 VSS In measurement of tdis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 pF. Capacitance Conditions Input Capacitance Output Capacitance VCC VI f Ta Symbol = 3.3 V = VSS = 1 MHz = 25 C Min. Max. Unit CI 7 pF Co 7 pF All pins not under test must be connected with ground by capacitors . IC Code Numbers UL62H1708A S A 35 Type Access Time 35 = 35 ns 55 = 55 ns Package S = SOP32 300 mil S1 = SOP32 330 mil Operating Temperature Range K = -40 to 85 C A = -40 to 125 C The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2 digits the calendar week. 6 November 01, 2001 Preliminary UL62H1708A Read Cycle 1: Ai-controlled (during Read Cycle : E1 = G = VIL, W = E2 = VIH) tcR Ai DQi Address Valid ta(A) Output Data Valid Previous Data Valid Output tv(A) Read Cycle 2: G-, E1, E2-controlled (during Read Cycle: W = V IH) tcR Ai E1 Addresses Valid tsu(A) ta(E) ten(E) tdis(E) tsu(A) ta(E) tdis(E) ten(E) E2 G ta(G) tdis(G) ten(G) DQi Output ICC(OP) ICC(SB) High-Z Output Data Valid tPU* tPD * 50 % 50 % * The same applies to E1 Write Cycle1: W-controlled tcW Ai Addresses Valid th(A) tsu(E) E1 tsu(E) E2 W tsu(A) tw(W) tsu(D) DQi Input DQi Input Data Valid tdis(W) High-Z Output G November 01, 2001 th(D) 7 ten(W) UL62H1708A Preliminary Write Cycle 2: E1-controlled tcW Ai E1 Addresses Valid tsu(A) th(A) tw(E) tsu(E) E2 tsu(W) W tsu(D) DQi Input ten(E) th(D) Input Data Valid tdis(W) DQi High-Z tdis(G) Output G Write Cycle 3 (E2-controlled) tcW Ai Addresses Valid th(A) tsu(E) E1 tsu(A) E2 tw(E) tsu(W) W tsu(D) DQi Input ten(E) tdis(W) Input Data Valid DQi Output th(D) High-Z tdis(G) G undefined L- to H-level H- to L-level The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved. 8 November 01, 2001 Preliminary UL62H1708A LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD's warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. November 01, 2001 Zentrum Mikroelektronik Dresden AG Grenzstrae 28 * D-01109 Dresden * P. O. B. 80 01 34 * D-01101 Dresden * Germany Phone: +49 351 8822 306 * Fax: +49 351 8822 337 * Email: sales@zmd.de * http://www.zmd.de