UL62H1708ASA55 - ZMD AG - Datasheet.Directory

1 November 01, 2001

UL62H1708A

Preliminary

F131072 x 8 bit static CMOS RAM

F35 and 55 ns Access Time

FCommon data inputs and

data outputs

FThree-state outputs

FTyp. operating supply current

35 ns: 45mA

55 ns: 30mA

FStandby current <100µA at 125°C

FTTL/CMOS-compatible

FPower supply voltage 3.3 V

FOperating temperature range

-40 °C to 85 °C

-40 °C to 125 °C

FCECC 90000 Qua lity Standard

FESD protection > 2000 V

(MIL STD 883C M3015.7)

FLatch-up im mun ity >100 mA

FPackage: SOP32 (300/330 mil)

The UL62H1708A is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

- Read - Standby

- Write - Data Rete ntion

The memory array is based on a

6-Transistor cell.

The circuit is activated by the rising

edge of E2 (at E1 = L), or the falling

edge of E1 (at E2 = H). The

address and control inputs open

simultaneously. According to the

information of W and G, the data

inputs, or outputs, are active.

During the act ive state (E1 = L and

E2 = H) each address change

leads to a new Read or Write cycl e.

In a Read cycle, the data outputs

are activated by the falling edge of

G, afterwards the data wo rd will b e

available at the outputs DQ0-DQ7.

After the address change, the data

outputs go High-Z until the new

information is available. The data

outputs have no preferred state. If

the memory is driven by CMOS

levels in the active state, and if

there is no change of the address,

data input and cont rol signals W or

G, the operating current (IO = 0 mA)

drops to the value of the operating

current in the Standby mode. The

Read cycle is finished by th e falling

edge of E2 or W, or by the rising

edge of E1, respectively.

Data retention is guaranteed down

to 2 V. With the exception of E1

and E2, all inputs consist of NOR

gates, so that no pull-up/pull-down

resistors are requ ired.

Low Voltage Automotive Fast 128K x 8 SRAM

Pin Configuration

Top View

Sign al Name Signal Descript ion

A0 - A16 Address Inputs

DQ0 - DQ7 Data In/Out

E1 Chip Enable 1

E2 Chip Enable 2

GOutput Enable

WWrite Enable

VCC Power Supply Voltage

VSS Ground

n.c. not connected

Pin Descript ion

n.c. VCC32

2A16 A1531

4A12 W

5A7 A1328

3A14 E230

6A6 A827

7A5 A926

8A4 A1125

12A0 DQ721

9A3 G

A2 A1023

11A1 E1

13DQ0 DQ620

14DQ1 DQ519

SOP

DQ4

DQ3

DQ2

VSS

Features Description

2 November 01, 200 1

UL62H1708A Preliminary

Oper ating Mode E1 E2 W GDQ0 - DQ7

Standby/n ot selected *L** High-Z

H*** High-Z

Internal Read L H H H High-Z

Read L H H L Data Outputs Low-Z

Wri te L H L * Data Inputs High-Z

Tr uth Table

Block Diagram

Maximum Ratings Symbol Min. Max. Unit

Power Supply Voltage VCC -0.3 4.6 V

Input Voltage VI-0.5 VCC + 0.5 V

Outpu t Vol tage VO-0.5 VCC + 0.5 V

Power Dissipa tion PD-1W

Operating Temperature K-Type

A-Type Ta-40

-40 85

125 °C

Storage Temperature Tstg -65 150 °C

Outpu t Short-Circuit Current

at VCC = 3.3 V and VO = 0 V** | I OS |100mA

Characteristics

**Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.

All voltages are referenced to VSS = 0 V (ground).

All charac teristics are valid in the power supply voltage range and in the operating temperature range specified.

Dynam ic measurements a re based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as

input levels of VIL = 0 V and VIH = 2.5 V. The timing reference level of all input and output signals is 1.5 V,

with the exceptio n of the tdis-times an d ten-times, in which cases transition is me asured ±200 mV from steady-state voltage.

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VCC VSS W GE1

Row Address

Inputs

Column Address

Inputs

Address

Change

Detector

Column Decoder Row Decoder

Sense Amplifier/

Write C ontrol Logi c

Clock

Generator

Common Data I/O

Mem ory Cell

Array

1024 Rows x

128 x 8 Columns

A10

A11

A12

A13

A14

A15

A16

*H or L

3 November 01, 2001

UL62H1708A

Preliminary

Recommended

Operating Conditions Symbol Conditions Min. Max. Unit

Powe r Su pply Voltage VCC 3.0 3.6 V

Input Low Voltage*VIL -0.3 0.8 V

Input High Voltage VIH 2.0 VCC + 0.3 V

Electrical Characteristics Symbol Conditions Min. Max. Unit

Supply Current - O perating M ode

Supply Current - Standby Mode

(CMOS level)

Supply Current - Standby Mode

(TTL level)

ICC(OP)

ICC(SB)

ICC(SB)1

VCC

VIL

VIH

tcW

VCC

VE1= VE2

VCC

VE1= VE2

K-Type

A-Type

= 3.6 V

= 0.8 V

= 2.0 V

= 35 ns

= 55 ns

= 70 ns

= 3.6 V

= VCC - 0.2 V

= 3.6 V

= 2.0 V

100

µA

Output High Voltage

Output Low Vo ltage

VOH

VOL

VCC

IOH

VCC

IOL

= 3.0 V

=-0.5 mA

= 3.0 V

= 0.5 mA

2.2

0.4

Input High Leakage Current

Input Low Leakage Current

IIH

IIL

VCC

VIH

VCC

VIL

= 3.6 V

= 0 V -2

2µA

µA

Output High Current

Output Low Current

IOH

IOL

VCC

VOH

VCC

VOL

= 3.0 V

= 2.0 V

= 3.0 V

= 0.4 V 0.5

-0.5 mA

Output Leakage Current

High at Three-S t ate Outputs

Low at Three-State Ou tputs

IOHZ

IOLZ

VCC

VOH

VCC

VOL

= 3.6 V

=0 V -2

2µA

µA

* -2 V at Pulse Width 10 ns

4 November 01, 200 1

UL62H1708A Preliminary

Sw itchin g Characteri stics

Read Cycle

Symbol 35 55 Unit

Alt. IEC Min. Max. Min. Max.

Read Cycle Time tRC tcR 35 55 ns

Addre ss Access Time to Data Valid tAA ta(A) 35 55 ns

Chip Enable Acce ss Time to Data Va li d tACE ta(E) 35 55 ns

G LOW to Data Valid tOE ta(G) 15 25 ns

E1 HIGH or E2 LOW to O utput in High-Z tHZCE tdis(E) 12 15 ns

G HIGH to O utput in High-Z tHZOE tdis(G) 12 15 ns

E1 LOW or E2 HIGH to Output in Low-Z tLZCE ten(E) 33ns

G LO W to Outp ut in L o w - Z tLZOE ten(G) 00ns

Outp ut Hold Tim e from Ad dress Change tOH tv(A) 33ns

E1 LOW or E2 HIGH to Power-Up Time tPU 00ns

E1 HIGH or E2 LOW to Power-Down Time tPD 35 55 ns

Switching Characteristics

Write Cycle

Symbol 35 55 Unit

Alt. IEC Min. Max. Min. Max.

Write Cycle Time tWC tcW 35 55 ns

Write Pulse Width tWP tw(W) 20 35 ns

Write Setup Time tWP tsu(W) 20 35 ns

Address Setup Ti me tAS tsu(A) 00ns

Address Valid to End of Wri te tAW tsu(A-WH) 20 40 ns

Chip Enab le Setup Time tCW tsu(E) 25 40 ns

Pulse Width Chip Enable to End of Write tCW tw(E) 25 40 ns

Data Setup Ti me t DS tsu(D) 15 25 ns

Data Hold Tim e tDH th(D) 00ns

Address Hold from End of Write tAH th(A) 00ns

W LOW to Output in High-Z tHZWE tdis(W) 15 20 ns

G HIGH to Ou tpu t in High-Z tHZOE tdis(G) 12 15 ns

W HIGH to Output in Low-Z tLZWE ten(W) 00ns

G LOW to Output in Low-Z tLZOE ten(G) 00ns

5 November 01, 2001

UL62H1708A

Preliminary

Data Retention

Characteristics Symbol Conditions Min. Typ. Max. Unit

Alt. IEC

Data Retention Supply Voltage VCC(DR) 1.5 3.6 V

Data Retention Supply Current ICC(DR) VCC(DR) = 2 V

VE1 =VE2 = V CC(DR) - 0.2 V 30 µA

Data Retention Setup Tim e tCDR tsu(DR) See Data Retention

Waveforms (below ) 0ns

Operating Recovery Ti me tRtrec tcR ns

Data Retention Mode E 1 - cont ro lled

Data Retenti on

3.0 V

tsu(DR) trec

VCC

VCC(DR) ≥ 1.5 V

0 V

2.0 V2.0 V

Data Rete ntion Mo de E2 - cont r olled

VE2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V

VCC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.2 V

0.8 V

3.0 V

0 V

VCC

VE1(DR) ≥ VCC(DR) - 0.2 V or VE1(DR) ≤ 0.2 V

VE2(DR) ≤ 0.2 V

trec

tDR

VCC(DR) ≥ 1.5 V

Data Retention E2

Data Retention Mode

6 November 01, 200 1

UL62H1708A Preliminary

Capacitance Conditions Symbol Min. Max. Unit

Input Capacitance VCC

= 3.3 V

= VSS

= 1 MHz

= 25 °C

CI7pF

Output Capacitance Co7pF

IC Code Numbers

UL62H1708A SA35

Type

Package

S = SOP32 300 mil

S1 = SOP32 330 m il

Oper ating Temp eratu re Rang e

K = -40 to 85 °C

A = -40 to 125 °C

Access Time

35 = 35 ns

55 = 55 ns

The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year , and

the last 2 digits the calendar week.

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Tes t Co nf ig ur a tio n f or Funct i on a l Check

VIH

VIL

VSS

VCC

3.3 V

481

255

1) In measurement of tdis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 p F.

In put l evel accord ing t o th e

relevant test measurement

Simultaneous measure-

ment of all 8 output pins

A10

A11

A12

A13

A14

A15

A16

All pins not under test must be co nnect ed with ground by capacitors.

30 pF1

7 November 01, 2001

UL62H1708A

Preliminary

Previous Data Valid Output Data Valid

Address Valid

Read Cycle 1: Ai-con trolled (during Read Cycle : E1 = G = VIL, W = E2 = VIH)

Read Cycle 2: G-, E1, E2-con t rol led (durin g R ea d C ycl e : W = VIH)

ta(A)

tcR

tv(A)

DQi

Output

tcR

High-Z

Addresses Valid

DQi

Output

tdis(E)

tsu(A) ta(E)

tsu(A)

ten(E)

ten(G)

ta(G)

ta(E) tdis(E)

tdis(G)

Output Data Valid

tPD*

tPU*

ICC(OP)

ICC(SB)

* The same applies to E1

50 % 50 %

Write Cycl e1: W-controlled

th(D)

DQi

Output

tcW

tsu(E) th(A)

tw(W)

tsu(A)

tsu(E)

tsu(D)

tdis(W) ten(W)

Addresses Valid

High-Z

Input In pu t Data Va li d

8 November 01, 200 1

UL62H1708A Preliminary

Write Cycle 2: E1-controlled

tsu(A)

th(D)

DQi

Input

DQi

Output

tcW

tw(E)

th(A)

tsu(W)

tsu(E)

tsu(D)

tdis(W)

ten(E)

Addresses Valid

Inp ut Data Val id

High-Z

tdis(G)

Write Cycle 3 (E2-contro lled)

High-Z

Inp ut Data Valid

th(D)

tsu(W)

tw(E)

tsu(D)

tcW

Addresses Valid

tsu(A)

tsu(E) th(A)

ten(E) tdis(W)

DQi

Input

DQi

Output tdis(G)

L- to H - le ve l undefined H- to L-le ve l

The information describes the type of component and shall not be considered as assured characteristics.Terms of

delivery and rights to change design rese rved.

Zentrum Mikroelektronik Dresden AG

Grenzstra ße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Ge rmany

Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Em ail: sales@zmd.de • http://www.zmd.de

November 01, 2001

UL62H1708A

Preliminary

LIFE S U PP O R T POLI CY

ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or o ther applications intended to s upport or sustain life, or f or any othe r application in which

the failure of the ZMD product could create a situation where personal injury or death may occur.

Componen ts used in life-s upport devices or systems must be expressly authorized by ZMD for such purpose.

LIMITED WARRANTY

The information in this document has been carefully checked and is believed to be reliable. However Zentrum

Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said in form ation

and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.

The inform ation in this docum ent des cribes t he t ype of comp onent and sh all not be c onsidere d as ass ured charac-

teristics.

ZMD does not guarantee that the use of any information contained herei n will not infringe upon the patent, trade-

mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This

document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and

condition s of sale.

ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,

presented in this publication at any time and without notice.