TS256MLQ64V5U - TRANSCEND INFORMATION

U 240PIN DDR2 533 Unbuffered DIMM

2GB With 128Mx8 CL4

Transcend Information Inc. 1

Description

The TS256MLQ64V5U is a 256M x 64bits DDR2-533

Unbuffered DIMM. The TS256MLQ64V5U consists of

16pcs 128Mx8bits DDR2 SDRAMs in 68 ball FBGA

packages and a 2048 bits serial EEPROM on a 240-pin

printed circuit board. The TS256MLQ64V5U is a Dual

In-Line Memory Module and is intended for mounting into

240-pin edge connector sockets.

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible

on both edges of DQS. Range of operation frequencies,

programmable latencies allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

Features

• RoHS compliant products.

• JEDEC standard 1.8V ± 0.1V Power supply

• VDDQ=1.8V ± 0.1V

• Max clock Freq: 267MHZ; 533M b/S/Pin.

• Posted CAS

• Programmable CAS Latency: 3,4,5

• Programmable Additive Latency :0, 1,2,3 and 4

• Write Latency (WL) = Read Latency (RL)-1

• Burst Length: 4,8(Interleave/nibble sequential)

• Programmable sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended

data-strobe is an optional feature)

• Off-Chip Driver (OCD) Imp edance Adjustment

• MRS cycle with address key programs.

• On Die Termination

• Serial presence detect with EEPROM

• Placement

PCB: 09-2345

U 240PIN DDR2 533 Unbuffered DIMM

2GB With 128Mx8 CL4

Transcend Information Inc. 2

Dimensions

Side Millimeters Inches

A 133.35±0.15 5.250±0.006

B 55 2.165

C 63 2.480000

D 5 0.197

E 2.5 0.0980

F 1.5±0.10 0.059±0.039

G 5.175 0.204

H 2.2 0.867

I 4 0.157

J 10 0.394

K 17.8 0.701

L 30±0.15 1.181±0.006

M 1.27±0.10 0.050±0.004

(Refer Placement)

Pin Identification

Symbol Function

A0~A13, BA0~BA2 Address input

DQ0~DQ63 Data Input / Output.

DQS0~DQS8 Data strobe

/DQS0~/DQS8 Differential Data strobe

CK0, /CK0

CK1, /CK1

CK2, /CK2

Clock Input.

CKE0, CKE1 Clock Enable Input.

ODT0, ODT1 On-die termination control li ne

/CS0, /CS1 Chip Select Input.

/RAS Row Address Strobe

/CAS Column Address Strobe

/WE Write Enable

DM0~DM8 Data-in Mask

VDD +1.8 Voltage power supply

VDDQ +1.8 Voltage Power Supply for

DQS

VREF Power Supply for Referen ce

VDDSPD Serial EEPROM Positive Power

Supply

SA0~SA2 Address select for EEPROM

SCL Serial PD Clock

SDA Serial PD Add/Data input/output

VSS Ground

NC No Connection

U 240PIN DDR2 533 Unbuffered DIMM

2GB With 128Mx8 CL4

Transcend Information Inc. 3

Pinouts:

No Pin

Name Pin

No Pin

Name Pin

No Pin

Name Pin

No Pin

Name Pin

No Pin

Name Pin

No Pin

Name

01 VREF 41 VSS 81 DQ33 121 VSS 161 *CB4 201 VSS

02 VSS 42 *CB0 82 VSS 122 DQ4 162 *CB5 202 DM4

03 DQ0 43 *CB1 83 /DQS4 123 DQ5 163 VSS 203 NC

04 DQ1 44 VSS 84 DQS4 124 VSS 164 *DM8 204 VSS

05 VSS 45 */DQS8 85 VSS 125 DM0 165 NC 205 DQ38

06 /DQS0 46 *DQS8 86 DQ34 126 NC 166 VSS 206 DQ39

07 DQS0 47 VSS 87 DQ35 127 VSS 167 CB6 207 VSS

08 VSS 48 *CB2 88 VSS 128 DQ6 168 CB7 208 DQ44

09 DQ2 49 *CB3 89 DQ40 129 DQ7 169 VSS 209 DQ45

10 DQ3 50 VSS 90 DQ41 130 VSS 170 VDDQ 210 VSS

11 VSS 51 VDDQ 91 VSS 131 DQ12 171 CKE1 211 DM5

12 DQ8 52 CKE0 92 /DQS5 132 DQ13 172 VDD 212 NC

13 DQ9 53 VDD 93 DQS5 133 VSS 173 NC 213 VSS

14 VSS 54 *BA2 94 VSS 134 DM1 174 NC 214 DQ46

15 /DQS1 55 NC 95 DQ42 135 NC 175 VDDQ 215 DQ47

16 DQS1 56 VDDQ 96 DQ43 136 VSS 176 A12 216 VSS

17 VSS 57 A11 97 VSS 137 CK1 177 A9 217 DQ52

18 NC 58 A7 98 DQ48 138 /CK1 178 VDD 218 DQ53

19 NC 59 VDD 99 DQ49 139 VSS 179 A8 219 VSS

20 VSS 60 A5 100 VSS 140 DQ14 180 A6 220 CK2

21 DQ10 61 A4 101 SA2 141 DQ15 181 VDDQ 221 /CK2

22 DQ11 62 VDDQ 102 NC 142 VSS 182 A3 222 VSS

23 VSS 63 A2 103 VSS 143 DQ20 183 A1 223 DM6

24 DQ16 64 VDD 104 /DQS6 144 DQ21 184 VDD 224 NC

25 DQ17 65 VSS 105 DQS6 145 VSS 185 CK0 225 VSS

26 VSS 66 VSS 106 VSS 146 DM2 186 /CK0 226 DQ54

27 /DQS2 67 VDD 107 DQ50 147 NC 187 VDD 227 DQ55

28 DQS2 68 NC 108 DQ51 148 VSS 188 A0 228 VSS

29 VSS 69 VDD 109 VSS 149 DQ22 189 VDD 229 DQ60

30 DQ18 70 A10/AP 110 DQ56 150 DQ23 190 BA1 230 DQ61

31 DQ19 71 BA0 111 DQ57 151 VSS 191 VDDQ 231 VSS

32 VSS 72 VDDQ 112 VSS 152 DQ28 192 /RAS 232 DM7

33 DQ24 73 /WE 113 /DQS7 153 DQ29 193 /CS0 233 NC

34 DQ25 74 /CAS 114 DQS7 154 VSS 194 VDDQ 234 VSS

35 VSS 75 VDDQ 115 VSS 155 DM3 195 ODT0 235 DQ62

36 /DQS3 76 /CS1 116 DQ58 156 NC 196 A13 236 DQ63

37 DQS3 77 ODT1 117 DQ59 157 VSS 197 VDD 237 VSS

38 VSS 78 VDDQ 118 VSS 158 DQ30 198 VSS 238 VDDSPD

39 DQ26 79 VSS 119 SDA 159 DQ31 199 DQ36 239 SA0

40 DQ27 80 DQ32 120 SCL 160 VSS 200 DQ37 240 SA1

*For ECC type; Please refer Block Diagram

U 240PIN DDR2 533 Unbuffered DIMM

2GB With 128Mx8 CL4

Transcend Information Inc. 4

Block Diagram

DQS0

DM0

/DQS0

/CS0

/CS1

DM/CS DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/CS DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS1

DM1

/DQS1

DM/CS DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/CS DQS/DQS

I/O 0

I/O

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS2

DM2

/DQS2

DM/CS DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/CS DQS/DQS

U11

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS3

DM3

/DQS3

DM/CS DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/CS DQS/DQS

U12

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS4

DM4

/DQS4

DM/CS DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS5

DM5

/DQS5

DM/CS DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/CS DQS /DQS

U14

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS6

DM6

/DQS6

DM/CS DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS7

DM7

/DQS7

DM/CS DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/CS DQS /DQS

U16

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ 0

DQ 1

DQ 2

DQ 3

DQ 4

DQ 5

DQ 6

DQ 7

DQ 8

DQ 9

DQ 11

DQ 12

DQ 13

DQ 14

DQ 15

DQ 16

DQ 17

DQ 19

DQ 20

DQ 21

DQ 24

DQ 25

DQ 26

DQ 27

DQ 28

DQ 29

DQ 30

DQ 31

DQ 32

DQ 33

DQ 34

DQ 35

DQ 36

DQ 37

DQ 38

DQ 39

VDDSPD

VDD/VDDQ

VREF

VSS

EEPROM

U1~U16

SDA

SCL

SA0 SA1 SA2

EEPROM

CK0,/CK0

A0~A13

BA0~BA2

CKE0

CKE1

/RAS

/CAS

/WE

ODT0

ODT1

U1~U16

U1~U8

U9~U16

U1~U16

U1~U8

U9~U16

CK1,/CK1

CK2,/CK2

U4~U5 &

U12~U13

U1~U3 & U9~U11

U6~U8 &

U14~U16

Note: 1.DQ,DM,DQS & /DQS resistors :22

Ohms 5%

2.Bx,Ax, / RAS, /CAS & /WE resi stors :3

Ohms 5%

DQ 40

DQ 41

DQ 42

DQ 43

DQ 44

DQ 45

DQ 46

DQ 47

DQ 48

DQ 49

DQ 50

DQ 51

DQ 52

DQ 53

DQ 54

DQ 55

DQ 56

DQ 57

DQ 58

DQ 59

DQ 60

DQ 61

DQ 62

DQ 63

This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either

expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes

in specifications at any time without prior notice.

U 240PIN DDR2 533 Unbuffered DIMM

2GB With 128Mx8 CL4

Transcend Information Inc. 5

Absolute Maximum DC Ratings

Parameter Symbol Value Unit Notes

Voltage on VDD relative to Vss VDD -1.0 ~ 2.3 V 1

Voltage on VDDQ pin relative to Vss VDDQ -0.5 ~ 2.3 V 1

Voltage on VDDL pin relative to Vss VDDL -0.5 ~ 2.3 V 1

Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 2.3 V 1

Storage temperature TSTG -55~+100 °C 1,2

1.Stress greater than those listed under “Absolute Maximum Ratin gs” may cause permanent damage to the

stress rating only and functional operation of the device at these or any other conditions above those indicated

in the operational sections of this spe cification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability.

Note:

2.Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the

measurement conditions, please refer to JESD5 1-2 standard.

AC & DC Operating Conditions

Recommended DC operating conditions (SSTL –1.8)

Rating

Parameter Symbol Min Typ. Max Unit Notes

Supply voltage VDD 1.7 1.8 1.9 V

Supply voltage for DLL VDDL 1.7 1.8 1.9 V 4

Supply voltage for Output VDDQ 1.7 1.8 1.9 V 4

I/O Reference voltage VREF 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V 1,2

I/O Termination voltage VTT VREF-0.04 VREF VREF+0.04 V 3

DC Input logic high VIH(DC) VREF+0.125 - VDDQ+0.3 V

DC Input logic low VIL(DC) -0.3 - VREF-0.125 V

There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all

conditions VDDQ must be less than or equal to VDD.

1.The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the

value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track

variations in VDDQ.

2.Peak to peak AC noise on VREF may not exceed +/-2% VREF (DC).

3.VTT of transmitting device must track VREF of receiving device.

Note:

4.AC parameters are measured with VDD, VDDQ and VDDDL tied togethe r.

Operating Temperature Condition

Parameter Symbol Rating Unit Note

Operating Temperature TOPER 0 to 85 °C1,2

1.Operating Temperature is the case surface temperature on the ce nter/top side of the DRAM. For the

measurement conditions, please refer to JESD5 1.2 standard.

2. At 0 - 85°C, operation temperature range are the temperature which all DRAM specification will be supported.

Note:

U 240PIN DDR2 533 Unbuffered DIMM

2GB With 128Mx8 CL4

Transcend Information Inc. 6

IDD Specification parameters Definition

( IDD values are for full operating range of voltage and Temperatur e)

Parameter Symbol Max. Unit Note

Operating One bank Acti ve-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD),

tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWIT CHING IDD0 1,040 mA

Operating One bank Acti ve-read-Precharge current; IOUT = 0mA; BL = 4, CL =

CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(ID D), tRCD =

tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bu s

inputs are SWITCHING; Data pattern is same a s IDD4W IDD1 1,120 mA

Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW;

Other control and address bus inputs are STABLE; Data bus inputs are FLOATING IDD2P 240 mA

Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,

CS\ is HIGH; Other control and address bus inputs ar e STABLE; Data bus inputs are

FLOATING IDD2Q 720 mA

Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is

HIGH; Other control an d address bus inputs are SWITCHING; Data bus inputs are

SWITCHING IDD2N 720 mA

Fast PDN Exit MRS(12) = 0mA IDD3P-F 560

Active power - down current; All banks open; tCK

= tCK(IDD); CKE is LOW; Other control and address

bus inputs are STABLE; Data bus input s are

FLOATING Slow PDN Exit MRS(12) = 1mA IDD3P-S 288 mA

Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD),

tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other co ntrol

and address bus inputs ar e SWITCHING; Data bus inputs are SWITCHING IDD3N 840 mA

Operating burst read current; All ban ks open, Continuous burst reads, IOUT =

0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =

tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; A ddress bus inputs

are SWITCHING; Data pattern is same as IDD4W IDD4R 1,400 mA

Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL

= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is

HIGH, CS\ is HIGH between valid comm ands; Addres s bus inputs are SWITCHING;

Data bus inputs are SWITCHING IDD4R IDD4W 1,400 mA

Burst Auto refre sh current; tCK = tCK(IDD); Refre s h command at every tRFC(IDD)

interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and

address bus i nputs are SWITCHING; Data bus inputs are SWITCHING IDD5B 2,080 mA

Self refresh current; CK and CK\ at 0 V ; CKE ≒ 0.2V; Other control and address

bus inputs are FLOATING; Data bus inputs are FLOATING IDD6 240 mA

Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK =tCK(IDD), tRC = tRC(IDD),

tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid

commands; Address bus inputs a re STABLE during Deselects; Data pattern is same

as IDD4R; Refer to the following page for detailed timing conditio ns

IDD7 2,600 mA

Note: 1. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ

loading capacitor.

U 240PIN DDR2 533 Unbuffered DIMM

2GB With 128Mx8 CL4

Transcend Information Inc. 7

Input AC Logic Level

Parameter Symbol Min Max Unit Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.250 V

Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.250 V

AC Input Test Condition

Condition Symbol Value Unit Note

Input reference voltage VREF 0.5*VDDQ V 1

Input signal maximum peak to peak swing VSWING(MAX) 1.0 V 1

Input signal minimum slew rate SLEW 1.0 V/ns 2,3

1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the

device under test.

2. The input signal minimum slew rate is to be maintained ove r the ran ge from VREF to VIH(AC) min for rising

edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure.

Note:

3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions

and VIH(AC) to VIL(AC) on the negative transitions.

SWING(MAX)

delta TF delta TR

VDD

(AC)

min

(DC)

min

VREF

(DC)

max

(AC)

max

VSS

Falling Slew= V

REF

-V

(AC)

max

delta TF Rising Slew= V

(AC)

min-

REF

delta TR

AC Input Test Signal Waveform

Input/Output Capacitance (VDD = 1.8V, VDDQ = 1.8V, TA = 25°C)

Parameter Symbol Min Max Unit

Input capacitance (CK0 and /CK0)

Input capacitance (CK1 and /CK1)

Input capacitance (CK2 and /CK2)

Input capacitance (CKE0 and /CS)

Input capacitance (A0~A13, BA0~BA2, /RAS, /CAS, /WE)

Input capacitance (DQ, DM, DQS, /DQS)

CCK0

CCK1

CCK2

CI1

CI2

CIO

Note: DM is internally loaded to match DQ and DQS identically.

U 240PIN DDR2 533 Unbuffered DIMM

2GB With 128Mx8 CL4

Transcend Information Inc. 8

Timing Parameters & Specifications

(These AC characteristics were tested on the Component)

Parameter Symbol Min Max Unit Note

DQ output access time from CK & /CK tAC -500 +500 ps

DQS output access time from CK & /CK tDQSCK -450 +450 ps

CK high-level width tCH 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 tCK

CK half period tHP min(tCL,tCH) X ps

Clock cycle time, CL=x tCK 3750 8000 ps

DQ and DM input hold time tDH 225 x ps

DQ and DM input setup time tDS 100 X ps

Control & Address input pulse width for each input tIPW 0.6 x tCK

DQ and DM input pulse wi dth for each input tDIPW 0.35 X tCK

Data-out high-impedance time from CK/CK tHZ X tAC max ps

DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max ps

DQ low-impedan ce time from CK/CK tLZ(DQ) 2* tACmin tACmax ps

DQS-DQ skew for DQS and associated DQ signals tDQSQ X 300 ps

DQ hold skew factor tQHS X 400 ps

DQ/DQS output hold time from DQS tQH tHP - tQHS X ps

Write command to first DQS latching transition tDQSS -0.25 +0.25 tCK

DQS input high pulse width tDQSH 0.35 X tCK

DQS input low pulse width tDQSL 0.35 X tCK

DQS falling edge to CK setup time tDSS 0.2 X

tCK

DQS falling edge hold time from CK tDSH 0.2 X tCK

Mode register set command cycle time tMRD 2 X tCK

Write postamble tWPST 0.4 0.6 tCK

Write preamble tWPRE 0.35 X tCK

Address and control input hold time tIH 375 X ps

Address and control input setup time tIS 250 X ps

Read preamble tRPRE 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 tCK

Active to active command period for 1KB page size

products tRRD 7.5 X ns

Active to active command period for 2KB page size

products tRRD 10 X ns

Four Activate Window for 1KB page si ze products tFAW 37.5 ns

U 240PIN DDR2 533 Unbuffered DIMM

2GB With 128Mx8 CL4

Transcend Information Inc. 9

Four Activate Window for 2KB page si ze products tFAW 50 ns

/CAS to /CAS command delay tCCD 2 tCK

Write recovery time tWR 15 X

Auto precharge write recovery + precharge time tDAL tWR+tRP X tCK

Internal write to read command delay tWTR 7.5 X ns

Internal read to precharge comm and delay tRTP 7.5

Exit self refresh to a non-read command tXSNR tRFC + 10 ns

Exit self refresh to a read command tXSRD 200 tCK

Exit precharge power down to any non-read command tXP 2 X

tCK

Exit active power down to read command tXARD 2 X tCK

Exit active power down to read command (Slow exit,

Lower power) tXARDS 6 - AL tCK

CKE minimum pulse width (high and low pul se width) tCKE 3 tCK

ODT turn-on delay tAOND 2 2 tCK

ODT turn-on tAON tAC(min) tAC(max)+1 ns

ODT turn-on(Power-Down mode) tAONPD tAC(min)+2 2tCK+

tAC(max)+1 ns

ODT turn-off delay tAOFD 2.5 2.5 tCK

ODT turn-off tAOF tAC(min) tAC(max)+ 0.6 ns

ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 2.5tCK+

tAC(max)+1 ns

ODT to power down entry latency tANPD 3 tCK

ODT power down exit latency tAXPD 8 tCK

OCD drive mode output delay tOIT 0 12 ns

Minimum time clocks remains ON after CKE

asynchronously drops LOW tDelay tIS+tCK+tIH ns

U 240PIN DDR2 533 Unbuffered DIMM

2GB With 128Mx8 CL4

Transcend Information Inc. 10

SERIAL PRESENCE DETECT SPECIFICATION

Serial Presence Detect

Byte No. Function Described Standard Specification Vendor Part

0 # of Serial PD Bytes written during module p roduction 128bytes 80

1 Total # of Bytes of S.P.D Memory Device 256bytes 08

2 Fundamental Memory Type DDR2 SDRAM 08

3 # of Row Addresses on this Assembly 13 0E

4 # of Column Addresses on this Assembly 10 0A

5 # of Module Rows on this Assembly 2 ROW, Planar,

30.0mm 61

6 Data Width of this Assembly 64bits 40

7 Reserved - 00

8 VDDQ and Interface Standard of this Assembly SSTL 1.8V 05

9 DDR2 SDRAM cycle time at Max. Supported CAS

latency=X 3.75ns 3D

10 DDR2 SDRAM Access time from clock at CL=X ±0.5ns 50

11 DIMM configuration type (non-parity, Parity, ECC) Non ECC 00

12 Refresh Rate 7.8us 82

13 Primary DDR2 SDRAM Width X8 08

14 Error Checking DDR2 SDRAM Width N/A 00

15 Reserved - 00

16 DDR2 SDRAM device attributes: Burst lengths

supported 4,8 0C

17 DDR2 SDRAM device attributes: # of banks on each

DDR2 SDRAM dev ice 8 banks 08

18 DDR2 SDRAM device attributes:CAS Latency

supported 5,4,3 38

19 Reserved - 00

20 DIMM type information Regular UDIMM 02

21 DDR2 SDRAM Module Attributes Analysis probe not

installed, FET switch

external not enable 00

22 DDR2 SDRAM Device Attributes: Gene ral Supports weak driver 01

23 DDR2 SDRAM Cycle Tim e CL=X-1 3.75ns 3D

24 DDR SDRAM Access from Clock CL=X-1 ±0.5ns 50

25 DDR SDRAM Cycle Time CL =X-2 5.0ns 50

26 DDR SDRAM Access from Clock CL=X-2 ±0.6ns 60

27 Minimum Row Precharge Time (tRP) 15ns 3C

28 Minimum Row Active to Row Activate delay (tRRD) 7.5ns 1E

29 Minimum RAS to CAS Delay (tRCD) 15ns 3C

30 Minimum active to Precharge time (tRAS) 40ns 2D

31 Module ROW density 2 GB 01

32 Command and address setup time before clock(=tIS) 0.25ns 25

33 Command and address hold time after clock(=tIH) 0.37ns 37

34 Data input setup time before strobe(=tDS) 0.10ns 10

35 Data input hold time after strobe(=tDH) 0.22ns 22

36 Write recovery time(=tWR) 15ns 3C

U 240PIN DDR2 533 Unbuffered DIMM

2GB With 128Mx8 CL4

Transcend Information Inc. 11

37 Internal write to read command delay(=tWTR) 7.5ns 1E

38 Internal read to precharge command delay(=tRTP) 7.5ns 1E

39 Memory analysis probe characteristics - 00

40 Reserved - 00

41 DDR SDRAM Minimum Active to Active/Auto Refresh

Time(tRC) 55ns 3C

42 DDR SDRAM Minimum Auto-Refresh to

Active/Auto-Refresh Command Period (t RFC) 195ns 7F

43 DDR SDRAM Maximum Device Cycle Time (tCK max) 8ns 80

44 DDR SDRAM DQS-DQ Skew for DQS and associate d

DQ signals (t DQSQ max) 0.3ns 1E

45 DDR SDRAM Read Data Hold Skew Factor (tQHS) 0.4ns 28

46 PLL Relock Time - 00

47~61 Superset Information - 00

62 SPD Data Revision Code REV 1.1 11

63 Checksum for Bytes 0-62 - 27

64-71 Manufacturers JEDEC ID Transcend 7F, 4F

72 Manufacturing Location T 54

54 53 32 35 36 4D

4C 51 36 34 56 35

73-90 Manufacturers Part Nu mber TS256M LQ64V5U

55 20 20 20 20 20

91-92 Revision Code - -

93-94 Manufacturing Date By Manufacturer Variable

95-98 Assembly Serial Number By Manufacturer Variable

99-127 Manufacturer Specific Data - -

128~255 Open for customer u se Undefined -