INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT154 4-to-16 line decoder/demultiplexer Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer 74HC/HCT154 The 74HC/HCT154 decoders accept four active HIGH binary address inputs and provide 16 mutually exclusive active LOW outputs. The 2-input enable gate can be used to strobe the decoder to eliminate the normal decoding "glitches" on the outputs, or it can be used for the expansion of the decoder. FEATURES * 16-line demultiplexing capability * Decodes 4 binary-coded inputs into one of 16 mutually exclusive outputs * 2-input enable gate for strobing or expansion * Output capability: standard * ICC category: MSI The enable gate has two AND'ed inputs which must be LOW to enable the outputs. GENERAL DESCRIPTION The "154" can be used as a 1-to-16 demultiplexer by using one of the enable inputs as the multiplexed data input. When the other enable is LOW, the addressed output will follow the state of the applied data. The 74HC/HCT154 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER tPHL/ tPLH propagation delay An, En to Yn CI input capacitance CPD power dissipation capacitance per package CONDITIONS CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". September 1993 2 UNIT HC HCT 11 13 ns 3.5 3.5 pF 60 60 pF Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer 74HC/HCT154 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17 Y0 to Y15 outputs (active LOW) 18, 19 E0, E1 enable inputs (active LOW) 12 GND ground (0 V) 23, 22, 21, 20 A0 to A3 address inputs 24 VCC positive supply voltage (a) Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.4 Functional diagram. September 1993 3 (b) Fig.3 IEC logic symbol. Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer 74HC/HCT154 FUNCTION TABLE INPUTS E0 E1 A0 H H L H L H X X X L L L L L L L L L L L L A1 OUTPUTS A2 A3 Y0 Y1 Y2 Y3 X X X X X X X X X H H H H H H H H H H H H L H L H L L H H L L L L L L L L L H H H H L H H H H L H L L L L L H L H L L H H H H H H L L L L H H H H H H H H L L L L L L L L L H L H L L H H L L L L H H H H H H H H L L L L L L L L L H L H L L H H H H H H H H H H H H H H Y4 Y5 Y6 Y9 Y10 Y11 Y12 Y13 Y14 Y15 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L H H H H L H H H H L H H H H L H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L H H H H L H H H H L H H H H L H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L H H H H L H H H H L H H H H L Note 1. H = HIGH voltage level L = LOW voltage level X = don't care Fig.5 Logic diagram. September 1993 4 Y7 Y8 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer 74HC/HCT154 DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. -40 to +85 typ. max. min. max. -40 to +125 min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay An to Yn 36 13 10 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay En to Yn 39 14 11 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Figs 6 and 7 September 1993 5 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer 74HC/HCT154 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current ( ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT An En 1.0 1.0 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. -40 to +85 typ. max. min. max. -40 to +125 min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay An to Yn 16 35 44 53 ns 4.5 Fig.6 tPHL/ tPLH propagation delay En to Yn 15 32 40 48 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 6 and 7 September 1993 6 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer 74HC/HCT154 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Fig.7 Waveforms showing the address input (An) to output (Yn) propagation delays and the output transition times. Waveforms showing the enable input (En) to output (Yn) propagation delays and the output transition times. APPLICATION INFORMATION Fig.8 Fig.9 1-of-16 decoder; LOW level output is selected. 1-of-16 demultiplexer; logic level on selected outputs follow the logic level on the data input. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". September 1993 7