March 1996
NDC7001C
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description Features
____________________________________________________________________________________________
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter N-Channel P-Channel Units
VDSS Drain-Source Voltage 50 -50 V
VGSS Gate-Source Voltage - Continuous 20 -20 V
IDDrain Current - Continuous (Note 1a) 0.51 -0.34 A
- Pulsed 1.5 -1
PDMaximum Power Dissipation (Note 1a) 0.96 W
(Note 1b) 0.9
(Note 1c) 0.7
TJ,TSTG Operating and Storage Temperature Range -55 to 150°C
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 130 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W
NDC7001C.SAM
These dual N and P-channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process has been designed to minimize on-state resistance,
provide rugged and reliable performance and fast switching.
These devices is particularly suited for low voltage, low
current, switching, and power supply applications.
N-Channel 0.51A, 50V, RDS(ON) = 2Ω @ VGS=10V
P-Channel -0.34A, -50V. RDS(ON)= 5Ω @ VGS=-10V.
High density cell design for low RDS(ON).
Proprietary SuperSOTTM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High saturation current.
1
5
4
6
3
2
SuperSOTTM-6
© 1997 Fairchild Semiconductor Corporation
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Type Min Typ Max Units
OFF CHARACTERISTICS
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µAN-Ch 50 V
VGS = 0 V, ID = -250 µAP-Ch -50
IDSS Zero Gate Voltage Drain Current VDS = 40 V, VGS = 0 V N-Ch 1µA
TJ = 125°C 500
VDS = -40 V, VGS = 0 V P-Ch -1
TJ = 125°C -500
IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V All 100 nA
IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V All -100 nA
ON CHARACTERISTICS (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA N-Ch 11.9 2.5 V
TJ = 125°C 0.8 1.5 2.2
VDS = VGS, ID = -250 µ.A P-Ch -1 -2.5 -3.5
TJ = 125°C -0.8 -2.2 -3
RDS(ON) Static Drain-Source On-Resistance VGS = 10 V, ID = 0.51 A N-Ch 1 2 Ω
TJ = 125°C 1.7 3.5
VGS = 4.5 V, ID = 0.35 A1.6 4
VGS = -10 V, ID = -0.34 AP-Ch 2.5 5
TJ = 125°C 4 10
VGS = -4.5 V, ID = -0.25 A 5.3 7.5
ID(on) On-State Drain Current VGS = 10 V, VDS = 10 V N-Ch 1.5 A
VGS = -10 V, VDS = -10 V P-Ch -1
gFS Forward Transconductance VDS = 10 V, ID = 0.51 A N-Ch 400 mS
VDS = -10 V, ID = -0.34 A P-Ch 250
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance N-Channel
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
P-Channel
VDS = -25 V, VGS = 0 V,
f = 1.0 MHz
N-Ch 20 pF
P-Ch 40
Coss Output Capacitance N-Ch 13 pF
P-Ch 13
Crss Reverse Transfer Capacitance N-Ch 5 pF
P-Ch 4
NDC7001C.SAM
Electrical Characteristics (TA = 25oC unless otherwise noted)
Symbol Parameters Conditions Type Min Typ Max Units
SWITCHING CHARACTERISTICS (Note 2)
tD(on) Turn - On Delay Time N-Channel
VDD = 25 V, ID = 0.25 A,
VGS = 10 V, RGEN = 25 Ω
P-Channel
VDD = -25 V, ID = -0.25 A,
VGS = -10 V, RGEN = 25 Ω
N-Ch 6 20 nS
P-Ch 14 20
trTurn - On Rise Time N-Ch 6 20
P-Ch 6 20
tD(off) Turn - Off Delay Time N-Ch 11 20
P-Ch 13 20
tfTurn - Off Fall Time N-Ch 5 20
P-Ch 6 20
QgTotal Gate Charge N-Channel
VDS = 25 V,
ID = 0.51 A, VGS = 10 V
P-Channel
VDS = -25 V,
ID = -0.34 A, VGS = -10 V
N-Ch 1nC
P-Ch 1.3
Qgs Gate-Source Charge N-Ch 0.19 nC
P-Ch 0.23
Qgd Gate-Drain Charge N-Ch 0.33 nC
P-Ch 0.38
DRAIN-SOURCE DIODE CHARACTERISTICS
ISMaximum Continuous Source Current N-Ch 0.51 A
P-Ch -0.34
ISM Maximum Pulse Source Current (Note 2) N-Ch 1.5 A
P-Ch -1
VSD Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 0.51 A (Note 2) N-Ch 0.8 1.2 V
VGS = 0 V, IS = -0.34 A (Note 2) P-Ch -0.8 -1.2
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
PD(t)=TJ−TA
RθJA(t)=TJ−TA
RθJC+RθCA(t)=ID
2(t)×RDS(ON)TJ
Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 130oC/W when mounted on a 0.125 in2 pad of 2oz cpper.
b. 140oC/W when mounted on a 0.005 in2 pad of 2oz cpper.
c. 180oC/W when mounted on a 0.0015 in2 pad of 2oz cpper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDC7001C.SAM
1a 1b 1c
NDC7001C.SAM
0 1 2 3 4 5
0
0.3
0.6
0.9
1.2
1.5
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
6.0
V =10V
GS
DS
D
8.0 7.0
3.5
4.0
4.5
5.0
5.5
3.0
-50 -25 0 25 50 75 100 125 150
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE ON-RESISTANCE
J
V = 10V
GS
I = 0.51A
D
R , NORMALIZED
DS(ON)
-50 -25 025 50 75 100 125 150
0.7
0.8
0.9
1
1.1
1.2
T , JUNCTION TEMPERATURE (°C)
GATE-SOURCE THRESHOLD VOLTAGE
J
I = 250µA
D
V = V
DS GS
V , NORMALIZED
th
00.3 0.6 0.9 1.2 1.5
0.5
1
1.5
2
2.5
3
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
V = 3.5V
GS
R , NORMALIZED
DS(on)
6.0
4.0 4.5
5.0
5.5
10
8.0
7.0
00.3 0.6 0.9 1.2 1.5
0.5
1
1.5
2
2.5
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
T = 125°C
J
25°C
D
V = 10V
GS
-55°C
R , NORMALIZED
DS(on)
Typical Electrical Characteristics: N-Channel
Figure 1. N-Channel On-Region Characteristics. Figure 2. N-Channel On-Resistance Variation with
Gate Voltage and Drain Current.
Figure 3. N-Channel On-Resistance Variation with
Temperature. Figure 4. N-Channel On-Resistance Variation with
Drain Current and Temperature.
Figure 5. N-Channel Transfer Characteristics. Figure 6. N-Channel Gate Threshold Variation
with Temperature.
12345678
0
0.3
0.6
0.9
1.2
1.5
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25°C 125°C
V = 10V
DS
GS
D
T = -55°C
J
NDC7001C.SAM
-50 -25 0 25 50 75 100 125 150
0.88
0.92
0.96
1
1.04
1.08
1.12
1.16
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE BREAKDOWN VOLTAGE
I = 250µA
D
BV , NORMALIZED
DSS
J0.2 0.4 0.6 0.8 11.2
0.001
0.01
0.1
0.5
1
1.5
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
T = 125°C
J 25°C -55°C
V = 0V
GS
SD
S
00.2 0.4 0.6 0.8 11.2
0
2
4
6
8
10
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
I = 0.51A
D
V = 25V
DS
0.1 0.2 0.5 1 2 5 10 20 50
1
2
5
10
20
50
100
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
f = 1 MHz
V = 0V
GS
C
oss
C
rss
Figure 7. N-Channel Breakdown Voltage Variation
with Temperature. Figure 8. N-Channel Body Diode Forward Voltage
Variation with Current and Temperature.
Figure 9. N-Channel Capacitance Characteristics. Figure 10. N-Channel Gate Charge Characteristics.
Typical Electrical Characteristics: N-Channel (continued)
00.3 0.6 0.9 1.2 1.5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25°C
125°C
V = 10V
DS
GS
D
T = -55°C
J
Figure 11. N-Channel Transconductance Variation
with Drain Current and Temperature.
NDC7001C.SAM
-6-5-4-3-2-10
-1
-0.8
-0.6
-0.4
-0.2
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
-6.0
DS
D
V = -10V
GS -9.0-8.0
-5.0
-4.0
-7.0
-3.5
-50 -25 025 50 75 100 125 150
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE ON-RESISTANCE
J
V = -10V
GS
I = -0.34A
D
R , NORMALIZED
DS(ON)
-50 -25 025 50 75 100 125 150
0.8
0.85
0.9
0.95
1
1.05
1.1
T , JUNCTION TEMPERATURE (°C)
GATE-SOURCE THRESHOLD VOLTAGE
J
I = -250µA
D
V = V
DS GS
V , NORMALIZED
th
-1-0.8-0.6-0.4-0.2
0.5
1
1.5
2
2.5
3
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V =-4.5V
GS
D
-7.0
R , NORMALIZED
DS(ON)
-6.0
-5.0
-10
-9.0
-8.0
-1-0.8-0.6-0.4-0.2
0.5
1
1.5
2
2.5
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
R , NORMALIZED
DS(on)
V =-10 V
GS
T = 125°C
J
25°C
-55°C
Typical Electrical Characteristics: P-Channel (continued)
Figure 12. P-Channel On-Region Characteristics. Figure 13. P-Channel On-Resistance Variation with
Gate Voltage and Drain Current.
Figure 14. P-Channel On-Resistance Variation with
Temperature. Figure 15. P-Channel On-Resistance Variation with
Drain Current and Temperature.
Figure 16. P-Channel Transfer Characteristics. Figure 17. P-Channel Gate Threshold Variation
with Temperature.
-8-7-6-5-4-3-2-1
-1
-0.8
-0.6
-0.4
-0.2
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25°C 125°C
V =- 10V
DS
GS
D
T = -55°C
J
NDC7001C.SAM
-50 -25 025 50 75 100 125 150
0.9
0.95
1
1.05
1.1
1.15
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE BREAKDOWN VOLTAGE
I = 250µA
D
BV , NORMALIZED
DSS
J0.2 0.4 0.6 0.8 11.2 1.4 1.6 1.8
0.001
0.005
0.01
0.05
0.1
0.5
1
-V , BODY DIODE FORWARD VOLTAGE (V)
-I , REVERSE DRAIN CURRENT (A)
T = 125°C
J25°C -55°C
V =0V
GS
SD
S
00.2 0.4 0.6 0.8 11.2 1.4 1.6
-10
-8
-6
-4
-2
0
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
-48
V = -12V
DS
I = -0.34A
D
-24
0.1 0.2 0.5 1 2 5 10 20 50
1
2
5
10
20
50
100
-V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
f = 1 MHz
V = 0V
GS
C
oss
C
iss
C
rss
Figure 18. P-Channel Breakdown Voltage
Variation with Temperature. Figure 19. P-Channel Body Diode Forward
Voltage Variation with Current and
Temperature.
Figure 20. P-Channel Capacitance Characteristics. Figure 21. P-Channel Gate Charge Characteristics.
Typical Electrical Characteristics: P-Channel (continued)
-1-0.8-0.6-0.4-0.2
0
0.1
0.2
0.3
0.4
0.5
I , DRAIN CURRENT (A)
g , TRANSCONDUCTANCE (SIEMENS)
T = -55°C
J
D
FS
V =- 10V
DS
125°C
25°C
Figure 22. P-Channel Transconductance Variation with
Drain Current and Temperature.
NDC7001C.SAM
Typical Thermal Characteristics: N & P-Channel
00.2 0.4 0.6 0.8 1
0.6
0.7
0.8
0.9
1
1.1
1.2
2oz COPPER MOUNTING PAD AREA (in )
STEADY-STATE POWER DISSIPATION (W)
2
1c
1b
1a
4.5"x5" FR-4 Board
T = 25 C
Still Air
Ao
00.025 0.05 0.075 0.1 0.125
0.35
0.4
0.45
0.5
0.55
2oz COPPER MOUNTING PAD AREA (in )
I , STEADY-STATE DRAIN CURRENT (A)
2
1c
1b
1a
4.5"x5" FR-4 Board
T = 25 C
Still Air
V = 10V
Ao
GS
D
Figure 24. N-Ch Maximum Steady-State Drain
Current versus Copper Mounting Pad
Area.
Figure 23. SOT-6 Dual Package Maximum
Steady-State Power Dissipation versus Copper
Mounting Pad Area.
00.025 0.05 0.075 0.1 0.125
0.2
0.25
0.3
0.35
0.4
2oz COPPER MOUNTING PAD AREA (in )
-I , STEADY-STATE DRAIN CURRENT (A)
2
1c
1b
1a
4.5"x5" FR-4 Board
T = 25 C
Still Air
V = -10V
Ao
GS
D
Figure 25. P-Ch Maximum Steady-State
Drain Current versus Copper Mounting
Pad Area.
1 2 5 10 20 50 70
0.01
0.02
0.05
0.1
0.2
0.5
1
2
3
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
DS
D
RDS(ON) LIMIT
V = 10V
SINGLE PULSE
R = See Note 1c
T = 25°C
GS
A
θJA
1s
100ms
100us
DC
10ms
1ms
Figure 26. N-Channel Maximum Safe
Operating Area.
1 2 5 10 20 50 70
0.01
0.02
0.05
0.1
0.2
0.5
1
2
3
-V , DRAIN-SOURCE VOLTAGE (V)
-I , DRAIN CURRENT (A)
DS
D
RDS(ON) LIMIT
V = -10V
SINGLE PULSE
R = See Note 1c
T = 25°C
GS
A
θJA
1s
100ms
100us
DC
10ms
1ms
Figure 27. P-Channel Maximum Safe
Operating Area.
NDC7001C.SAM
G
D
S
VDD
RL
V
V
IN
OUT
VGS DUT
RGEN
10%
50%
90%
10%
90%
90%
50%
VIN
VOUT
on off
d(off) f
r
d(on)
t t
ttt
t
10%
PULSE WIDTH
Figure 29. N or P-Channel Switching Test Circuit.Figure 30. N or P-Channel Switching Waveforms.
Typical Thermal Characteristics: N & P-Channel
0.0001 0.001 0.01 0.1 110 100 300
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
r(t), NORMALIZED EFFECTIVE
Duty Cycle, D = t / t
12
R (t) = r(t) * R
R = See Note 1c
θJA
θJA
θJA
T - T = P * R (t)
θJA
A
J
P(pk)
t
1 t
2
Figure 28. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
TRADEMARKS
ACEx™
CoolFET™
CROSSVOLT™
E2CMOSTM
FACT™
FACT Quiet Series™
FAST®
FASTr™
GTO™
HiSeC™
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS P ATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
SyncFET™
TinyLogic™
UHC™
VCX™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
Rev. D
