1
Data sheet acquired from Harris Semiconductor
SCHS178C
Features
• Buffered Inputs
• Four Operating Modes: Shift Left, Shift Right, Load
and Store
• Can be Cascaded for N-Bit Word Lengths
• I/O0 - I/O7 Bus Drive Capability and Three-State for
Bus Oriented Applications
• Typical fMAX = 50MHz at VCC =5V,C
L= 15pF, TA=25
oC
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Pinout
CD54HC299, CD54HCT299
(CERDIP)
CD74HC299, CD74HCT299
(PDIP, SOIC)
TOP VIEW
Description
The ’HC259 and ’HCT299 are 8-bit shift/storage registers
with three-state bus interface capability. The register has four
synchronous-operating modes controlled by the two select
inputs as shown in the mode select (S0, S1) table. The mode
select, the serial data (DS0, DS7) and the parallel data (I/O0
- I/O7) respond only to the low-to-high transition of the clock
(CP) pulse. S0, S1 and data inputs must be stable one set-
up time prior to the clock positive transition.
The Master Reset (MR) is an asynchronous active low input.
When MR output is low, the register is cleared regardless of
the status of all other inputs. The register can be expanded
by cascading same units by tying the serial output (Q0) to
the serial data (DS7) input of the preceding register, and
tying the serial output (Q7) to the serial data (DS0) input of
the following register. Recirculating the (n x 8) bits is
accomplished by tying the Q7 of the last stage to the DS0 of
the first stage.
The three-state input/output I(/O) port has three modes of
operation:
1. Bothoutputenable(OE1andOE2)inputsarelow and S0
or S1 or both are low, the data in the register is presented
at the eight outputs.
2. When both S0 and S1 are high, I/O terminals are in the
high impedance state but being input ports, ready for par-
allel data to be loaded into eight registers with one clock
transition regardless of the status of OE1 and OE2.
3. Either one of the two output enable inputs being high will
force I/O terminals to be in the off-state. It is noted that
each I/O terminal is a three-state output and a CMOS
buffer input.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
S0
OE1
OE2
I/O6
I/O4
I/O2
Q0
I/O0
MR
GND
VCC
DS7
Q7
I/O7
S1
I/O5
I/O3
I/O1
CP
DS0
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD54HC299F3A -55 to 125 20 Ld CERDIP
CD54HCT299F3A -55 to 125 20 Ld CERDIP
CD74HC299E -55 to 125 20 Ld PDIP
CD74HC299M -55 to 125 20 Ld SOIC
CD74HC299M96 -55 to 125 20 Ld SOIC
CD74HCT299E -55 to 125 20 Ld PDIP
CD74HCT299M -55 to 125 20 Ld SOIC
CD74HCT299M96 -55 to 125 20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
January 1998 - Revised May 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD54HC299, CD74HC299,
CD54HCT299, CD74HCT299
High-Speed CMOS Logic
8-Bit Universal Shift Register; Three-State
[ /Title
(CD74
HC299
,
CD74
HCT29
9)
/
Sub-
j
ect
(High
Speed
CMOS
Logic
8-Bit
Uni-
versal
Shift
2
Functional Diagram
MODE SELECT FUNCTION TABLE THREE-STATE I/O PORT OPERATING MODE
FUNCTION
INPUTS INPUTS/OUTPUTS
OE1 OE2 S0 S1 Qn (REGISTER) I/O0 --- I/O7
Read Register L L L X L L
LLLXH H
LLXL L L
LLXL H H
Load Register X X H H Qn = I/On I/On = Inputs
Disable I/O H X X X X (Z)
XHXX X (Z)
TRUTH TABLE
FUNCTION
INPUTS REGISTER OUTPUTS
MR CP S0 S1 DS0 DS7 I/On Q0 Q1 --- Q6 Q7
RESET (CLEAR) L XXXXXXLL---LL
Shift Right H ↑hllXXLq
0--- q5q6
H↑hlhXXHq
0--- q5Q6
Shift Left H ↑lhXlXq
1q2 --- q7L
H↑lhXhXq
1q2--- q7H
Hold (Do Nothing) H ↑l l XXXq
0q1--- q6q7
Parallel Load H ↑hhXXlLL---LL
H↑h h X X h H H --- H H
H = Input Voltage High Level, h = Input voltage high one set-up timer prior clock transition; L = Input Voltage Low Level; l = Input voltage
low one set-up time prior to clock transition; qn = Lower case letter indicates the state of the reference output one set-up time prior to clock
transition; X - Voltage level on logic status don’t care; Z = Output in high impedance state, ↑ = Low to High Clock Transition.
I/O
THREE-STATE
OUTPUTS
I/O
THREE-STATE
OUTPUTS
SHIFT
REGISTER
MODE SELECTION
CP OE1 OE2 MR
12 2 3 9 20
VCC
7
6
5
4
8
1
I/O0
Q0
S0
STANDARD
OUTPUT
I/O2
I/O4
I/O6
BUS LINE
OUTPUTS
GND
10 11 18
DS0 DS7
13
14
15
16
17
19
I/O1
Q7
S1
STANDARD
OUTPUT
I/O3
I/O5
I/O7
BUS LINE
OUTPUTS
THREE-
STATE
CONTROL
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO, For -0.5V < VO < VCC + 0.5V
For Q Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
For I/O Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1) θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
Qn I/On ----- - - -V
-4 -6 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 -7.8 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
Qn I/On ----- - - -V
4 6 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 7.8 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
4
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
Three- State Leak-
age Current VIL or VIH VO=VCC
or GND -6--±0.5 - ±5-±10 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC and
GND 0 5.5 - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Three- State Leak-
age Current VIL or VIH VO=VCC
or GND -6--±0.5 - ±5-±10 µA
Additional Quies-
cent Device Cur-
rent Per
Input Pin: 1 Unit
Load
∆ICC
(Note 2) VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
S1, MR 0.25
I/O0 - I/O70.25
DS0, DS7 0.25
S0, CP 0.6
OE1, OE2 0.3
NOTE: Unit Load is ∆ICC limit specific in Static Specifications Table,
e.g., 360µA max. at 25oC.
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
5
Prerequisite for Switching Specifications
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
HC TYPES
Maximum Clock
Frequency fMAX 2 6 - - 5 - - 4 - - MHz
4.5 30 - - 25 - - 20 - - MHz
6 35 - - 29 - - 23 - - MHz
MR Pulse Width tW250- -65- -75--ns
4.5 10 - - 13 - - 15 - - ns
6 9 - - 11 - - 13 - - ns
Clock Pulse Width tW2 80 - - 100 - - 120 - - ns
4.5 16 - - 20 - - 24 - - ns
614- -17- -20--ns
Setup Time
DS0, DS7, I/On to Clock tSU 2 100 - - 125 - - 150 - - ns
4.5 20 - - 25 - - 30 - - ns
617- -21- -26--ns
Hold Time DS0, DS7,
I/On, S0, S1 to Clock tH20--0--0--ns
4.5 0 - - 0 - - 0 - - ns
60--0--0--ns
Recovery Time
MR to Clock tREC 25--5--5--ns
4.5 5 - - 5 - - 5 - - ns
65--5--5--ns
Setup Time
S1, S0 to Clock tSU 2 120 - - 150 - - 180 - - ns
4.5 24 - - 30 - - 36 - - ns
620- -26- -31--ns
HCT TYPES
Maximum Clock
Frequency fMAX 4.5 25 - - 20 - - 16 - - MHz
MR Pulse Width tW4.5 15 - - 19 - - 22 - - ns
Clock Pulse Width tW4.5 20 - - 25 - - 30 - - ns
Setup Time DS0, DS7,
I/On, S0, S1 to Clock tSU 4.5 20 - - 25 - - 30 - - ns
Hold Time DS0, DS7,
I/On, S0, S1 to Clock tH4.5 0 - - 0 - - 0 - - ns
Recovery Time MR to
Clock tREC 4.5 5 - - 5 - - 5 - - ns
Setup Time S1, S0 to
Clock tSU 4.5 27 - - 34 - - 41 - - ns
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
6
Switching Specifications CL = 50pF, Input tr, tf= 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay tPLH, tPHL CL = 50pF
Clock to I/O Output,
Clock to Q0 and Q7,
MR to Output
2 - - 200 - 250 - 300 ns
4.5 - - 40 - 50 - 60 ns
CL = 15pF 5 - 17 - - - - - ns
CL = 50pF 6 - - 34 - 43 - 51 ns
Output Enable and Disable
Times tPZL CL = 15pF 5 - 10 - - - - - ns
tPZH, tPLZ -13- - - - - ns
tPHZ -15- - - - - ns
Output High-Z to High Level tPZH CL = 50pF 2 - - 155 - 195 - 235 ns
4.5 - - 31 - 39 - 47 ns
6 - - 26 - 33 - 40 ns
Output High Level to High-Z tPHZ CL = 50pF 2 - - 185 - 230 - 280 ns
4.5 - - 37 - 46 - 56 ns
6 - - 31 - 39 - 48 ns
Output Low Level to High-Z tPLZ CL = 50pF 2 - - 155 - 195 - 235 ns
4.5 - - 31 - 39 - 47 ns
6 - - 26 - 33 - 40 ns
Output High-Z to Low Level tPZL CL = 50pF 2 - - 130 - 165 - 195 ns
4.5 - - 26 - 33 - 39 ns
6 - - 22 - 28 - 33 ns
Output Transition Time tTHL, tTLH CL = 50pF
Q0, Q7 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
I/O0 to I/O7tTHL, tTLH CL = 50pF 2 - - 60 - 75 - 90 ns
4.5 - - 12 - 15 - 18 ns
6 - - 10 - 13 - 15 ns
Input Capacitance CICL = 50pF - 10 - 10 - 10 - 10 pF
Three-State Output
Capacitance CO- - 20 - 20 - 20 - 20 pF
Power Dissipation Capacitance
(Notes 3, 4) CPD CL = 15pF 5 - 150 - - - - - pF
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
7
HCT TYPES
Propagation Delay tPHL, tPLH
Clock to I/O Output,
Clock to Q0 and Q7 CL = 50pF 4.5 - - 45 - 56 - 68 ns
CL = 15pF 5 - 19 - - - - - ns
MR to Output tPHL, tPLH CL = 50pF 4.5 - - 46 - 58 - 69 ns
Output Enable and Disable
Times tPZL,tPZH,
tPLZ, tPHZ CL = 15pF 5 - 10,
13, 15 --- - -ns
Output High-Z to High Level tPZH CL = 50pF 4.5 - - 32 - 40 - 48 ns
Output High Level to High-Z tPHZ CL = 50pF 4.5 - - 37 - 46 - 56 ns
Output Low Level to High-Z tPLZ CL = 50pF 4.5 - - 32 - 40 - 48 ns
Output High-Z to Low Level tPZL CL = 50pF 4.5 - - 30 - 38 - 45 ns
Output Transition Time tTLH, tTHL
Q0, Q7 CL = 50pF 4.5 - - 15 - 19 - 22 ns
I/O0 to I/O7CL = 50pF 4.5 - - 12 - 15 - 18 ns
Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF
Three-State Output
Capacitance CO- - 20 - 20 - 20 - 20 pF
Power Dissipation Capacitance
(Notes 3, 4) CPD CL = 15pF 5 - 170 - - - - - pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per register.
4. PD=C
PD VCC2fi+∑(CLVCC2fO) where fi= Input Frequency, fO= Output Frequency, CL= Output Load Capacitance,
VCC = Supply Voltage.
Switching Specifications CL = 50pF, Input tr, tf= 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
CLOCK 90% 50%
10% GND
VCC
trCLtfCL
50% 50%
tWL tWH
10%
tWL + tWH =fCL
I
CLOCK 2.7V 1.3V
0.3V GND
3V
trCL= 6ns tfCL= 6ns
1.3V 1.3V
tWL tWH
0.3V
tWL + tWH =fCL
I
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
8
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
Test Circuits and Waveforms (Continued)
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
trCLtfCL
GND
VCC
GND
VCC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
VCC 50%
50%
90%
10%
50%
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
tH(H)
trCLtfCL
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V 1.3V
1.3V
1.3V
90%
10%
1.3V
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
1.3V
tH(H)
1.3V
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
9
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto
VCC, CL = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
Test Circuits and Waveforms (Continued)
50% 10%
90%
GND
VCC
10%
90% 50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
0.3
2.7
GND
3V
10%
90%
1.3V
1.3V
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
tr6ns
tPZH
tPHZ
tPZL
tPLZ
6ns tf
1.3
IC WITH
THREE-
STATE
OUTPUT
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZH
OUTPUT
RL = 1kΩ
CL
50pF
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8780601RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8780601RA
CD54HC299F3A
5962-8943601MRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8943601MR
A
CD54HCT299F3A
CD54HC299F ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC299F
CD54HC299F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8780601RA
CD54HC299F3A
CD54HCT299F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8943601MR
A
CD54HCT299F3A
CD74HC299E ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC299E
CD74HC299EE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC299E
CD74HC299M ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC299M
CD74HC299M96 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC299M
CD74HC299M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC299M
CD74HC299M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC299M
CD74HC299ME4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC299M
CD74HC299MG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC299M
CD74HCT299E ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT299E
CD74HCT299EE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT299E
CD74HCT299M ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT299M
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD74HCT299M96 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT299M
CD74HCT299M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT299M
CD74HCT299M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT299M
CD74HCT299ME4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT299M
CD74HCT299MG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT299M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC299, CD54HCT299, CD74HC299, CD74HCT299 :
•Catalog: CD74HC299, CD74HCT299
•Military: CD54HC299, CD54HCT299
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC299M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
CD74HCT299M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC299M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74HCT299M96 SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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