LTC6603 Dual Adjustable Lowpass Filter FEATURES DESCRIPTION n The LTC(R)6603 is a dual, matched, programmable lowpass filter for communications receivers and transmitters. The selectivity of the LTC6603, combined with its linear phase, phase matching and dynamic range, make it suitable for filtering in many communications systems. With 1.5 phase matching between channels, the LTC6603 can be used in applications requiring pairs of matched filters, such as transceiver I and Q channels. Furthermore, the differential inputs and outputs provide a simple interface for most communications systems. n n n n n n n n n n n Guaranteed Phase and Gain Matching Specs Programmable BW Up to 2.5MHz Programmable Gain (0dB/6dB/12dB/24dB) 9th Order Linear Phase Response Differential, Rail-to-Rail Inputs and Outputs Low Noise: -145dBm/Hz (Input Referred) Low Distortion: -75dBc at 200kHz Simple Pin Programming or SPI Interface Set the Max Speed/Power with an External R Operates from 2.7V to 3.6V Input Range from 0V to 5.5V 4mm x 4mm QFN Package APPLICATIONS n n n n Small/Low Cost Basestations: IDEN, PHS, TD-SCDMA, CDMA2000, WCDMA, UMTS Low Cost Repeaters, Radio Links, and Modems 802.11x Receivers JTRS L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. The sampled data filter does not require an external clock yet its cutoff frequency can be set with a single external resistor with an accuracy of 3.5% or better. The external resistor programs an internal oscillator whose frequency is divided prior to being applied to the filter networks. This allows up to three cutoff frequencies that can be obtained for each external resistor value, allowing the cutoff frequency to be programmed over a range of more than six octaves. Alternatively, the cutoff frequency can be set with an external clock. The filter gain can also be programmed to 1, 2, 4 or 16. The LTC6603 features a low power shutdown mode that can be programmed through the serial interface and is available in a 24-pin 4mm x 4mm QFN package. TYPICAL APPLICATION 2.5MHz I and Q Lowpass Filter and Dual ADC 5V 3V LTC2297 49.9 100nH* 0.1F 0.1F Phase Matching 180pF 10pF 180pF 10pF I OUTPUT V+A V+D 49.9 100nH* IIN QIN 30.9k 0.1F +INA -INA -OUTA +INB +OUTB -INB LTC6603 -OUTB RBIAS CLKIO VOCM SER 180pF 49.9 100nH* GAIN1 GAIN0 VS = 3V, BW = 156.25kHz f = 125kHz, TA = 25C 1000 UNITS 40 49.9 100nH* 10pF Q OUTPUT CAP 50 +OUTA 0.1F BASEBAND GAIN CONTROL 14-BIT ADC CLKCNTL UNITS (%) V+IN 60 3V 20 14-BIT ADC 180pF 10pF 10 VCM 0 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 MISMATCH (DEG) 2.2F SDO LPFO GND LPF1 1.5 2 2.5 6603 TA01b SDI GND 30 3V *COILCRAFT 0603HP 6603 TA01a 6603fa 1 LTC6603 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) +OUTA CAP GAIN0(D0) GAIN1 -INA +INA TOP VIEW 24 23 22 21 20 19 V+IN 1 18 -OUTA V+A 2 17 SER VOCM 3 16 V+D 25 RBIAS 4 15 CLKIO CLKCNTL 5 14 GND LPF1(CS) 6 -OUTB LPFO(SCLK) SDO 9 10 11 12 SDI 8 -INB 13 +OUTB 7 +INB V+IN to GND ................................................................6V V+A , V+D to GND .........................................................4V V+A to V+D .............................................. -0.3V to +0.3V Filter Inputs to GND ....................... -0.3V to V+IN + 0.3V Pins 3, 4 to GND ............................. -0.3V to V+A + 0.3V Pins 5, 6, 9-11, 15, 17, 21, 22 to GND ..................... -0.3V to V+D + 0.3V Output Short-Circuit Duration .......................... Indefinite Operating Temperature Range (Note 2) LTC6603CUF .......................................-40C TO 85C LTC6603IUF ........................................-40C TO 85C Specified Temperature Range (Note 3) LTC6603CUF ...........................................0C TO 70C LTC6603IUF ........................................-40C TO 85C Storage Temperature Range................... -65C to 150C UF PACKAGE 24-LEAD (4mm x 4mm) PLASTIC QFN TJMAX = 150C, JA = 37C/W, JC = 4.3C/W EXPOSED PAD (PIN 25) IS GND. MUST BE SOLDERED TO THE PCB. ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION LTC6603CUF#PBF LTC6603CUF#TRPBF 6603 24-Lead (4mm x 4mm) Plastic QFN 0C to 70C SPECIFIED TEMPERATURE RANGE LTC6603IUF#PBF LTC6603IUF#TRPBF 6603 24-Lead (4mm x 4mm) Plastic QFN -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted. PARAMETER CONDITIONS Filter Gain Either Channel External Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open DC Gain, Gain Set = 0dB fIN = 62.5kHz (0.4 * fC), Relative to DC Gain fIN = 125kHz (0.8 * fC), Relative to DC Gain fIN = 156.25kHz (fC), Relative to DC Gain fIN = 234.375kHz (1.5 * fC), Relative to DC Gain Matching of Filter Gain External Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open DC Gain, Gain Set = 0dB fIN = 62.5kHz (0.4 * fC) fIN = 125kHz (0.8 * fC) fIN = 156.25kHz (fC) l l l l l l l l l MIN TYP MAX UNITS 0.25 -0.5 0.4 -0.6 0.4 -0.3 0.6 -0.4 -32 0.55 -0.1 0.8 -0.2 -29.5 dB dB dB dB dB 0.03 0.03 0.03 0.03 0.1 0.1 0.1 0.15 dB dB dB dB 6603fa 2 LTC6603 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted. PARAMETER CONDITIONS Filter Phase Either Channel External Clock = 80MHz, Filter Cutoff (fC) = 156.25kHz, VIN = 3.6VP-P, Pin 3 Open fIN = 62.5kHz (0.4 * fC) fIN = 125kHz (0.8 * fC) fIN = 156.25kHz (fC) l l l Matching of Filter Phase External Clock = 80MHz, Filter Cutoff (fC) = 156.25kHz, VIN = 3.6VP-P, Pin 3 Open fIN = 62.5kHz (0.4 * fC) fIN = 125kHz (0.8 * fC) fIN = 156.25kHz (fC) l l l Filter Gain Either Channel External Clock = 80MHz, Filter Cutoff (fC) = 2.5MHz, VIN = 3.6VP-P, Pin 3 Open DC Gain, Gain Set = 0dB fIN = 1MHz (0.4 * fC), Relative to DC Gain fIN = 2MHz (0.8 * fC), Relative to DC Gain fIN = 2.5MHz (fC), Relative to DC Gain fIN = 4MHz (1.5 * fC), Relative to DC Gain l l l l l Matching of Filter Gain External Clock = 80MHz, Filter Cutoff (fC) = 2.5MHz, VIN = 3.6VP-P, Pin 3 Open fIN = 2MHz (0.8 * fC) fIN = 2.5MHz (fC) l l Filter Phase Either Channel External Clock = 80MHz, Filter Cutoff (fC) = 2.5MHz, VIN = 3.6VP-P, Pin 3 Open fIN = 1MHz (0.4 * fC) fIN = 2MHz (0.8 * fC) fIN = 2.5MHz (fC) l l l Matching of Filter Phase External Clock = 80MHz, Filter Cutoff (fC) = 2.5MHz, VIN = 3.6VP-P, Pin 3 Open fIN = 1MHz (0.4 * fC) fIN = 2MHz (0.8 * fC) fIN = 2.5MHz (fC) Filter Cutoff Accuracy CLKCNTL = 3V (Note 4) when Self Clocked RBIAS = 200k RBIAS = 54.9k RBIAS = 30.9k DC Gain DC Gain Matching Noise At 200kHz MIN TYP MAX UNITS 158 -44 -152 161 -39 -146 163 -36 -142 deg deg deg 0.2 0.4 0.5 1.5 3 4 deg deg deg 0.5 -0.8 0.4 0.1 -43 1.2 -0.1 1.5 1 -32.6 dB dB dB dB dB 0.05 0.2 0.2 0.4 dB dB 155 -39 -141 159 -28 -126 deg deg deg l l l 2.5 4 4 deg deg deg l l l 3 3 3.5 % % % 0.5 6 11.8 23.2 1.2 6.6 12.5 24 dB dB dB dB 0.1 0.05 0.05 0.1 0.2 0.1 0.15 0.2 dB dB dB dB Filter Cutoff (fC) = 2.5MHz, 0.6V to 2.4V Each Output, Pin 3 Open Gain Setting = 0dB Gain Setting = 6dB Gain Setting = 12dB Gain Setting = 24dB l l l l Filter Cutoff (fC) = 2.5MHz, 0.6V to 2.4V Each Output, Pin 3 Open Gain Setting = 0dB Gain Setting = 6dB Gain Setting = 12dB Gain Setting = 24dB l l l l 0 -2 -0.7 -1.1 150 -45 -152 0 5.6 11.2 22.5 Voltage Noise Referred to the Input Gain = 0dB Gain = 6dB Gain = 12dB Gain = 24dB -124 -129 -135 -145 dBm/Hz dBm/Hz dBm/Hz dBm/Hz Noise Bandwidth = 5MHz, Referred to the Input Gain = 0dB Gain = 6dB Gain = 12dB Gain = 24dB -53 -59 -65 -76 dBm dBm dBm dBm THD VIN = 2VP-P, fIN = 200kHz, Gain Setting = 24dB -75 dB Input Impedance Gain = 24dB, RBIAS = 30.9k, Filter Cutoff (fC) = 2.5MHz Differential Common Mode 1.6 5 k k Integrated Noise 6603fa 3 LTC6603 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted. PARAMETER CONDITIONS VOS Differential Input Referred Differential Offset Voltage at Either Output Lowest Cutoff Frequency, Gain Setting = 24dB Highest Cutoff Frequency, Gain Setting = 24dB Lowest Cutoff Frequency, Gain Setting = 0dB Highest Cutoff Frequency, Gain Setting = 0dB l l l l fC = 625kHz Common Mode Input from 0V to 3V, V+IN = 3V Common Mode Input from 0V to 5V, V+IN = 5V l l 60 60 90 90 VOCM Pin Voltage V+A = V+D = 3V, Pin 3 Open, fC = 156.25kHz l 1.3 1.45 1.5 V VOCM Pin Input Impedance V+A = V+D = 3V, Pin 3 Open, fC = 156.25kHz l 2.5 3.4 4.5 k VOSCM Common Mode Offset Voltage, VOCM = 1.5V, Supplies = 3V VOSCM = VOUT-CM - VOCM l 100 185 mV Output Swing fC = 156.25kHz Source 1mA, Relative to V+A Sink 1mA, Relative to GND l l 200 150 500 400 mV mV fC = 156.25kHz Sourcing Sinking l l Internal Clock (RBIAS = 30.9k); Sum of the Currents into V+D, V+A, and V+IN All Supplies Set to 3V fC = 156.25kHz fC = 625kHz fC = 2.5MHz l l l 88 121 162 96 130 175 mA mA mA Supply Current, Shutdown Mode Sum of the Currents into V+D, V+A, and V+IN; All Supplies Set to 3V Shutdown Via Serial Interface l 170 235 A Supply Voltage V+D, V+A Relative to GND V+IN Relative to GND l l 2.7 2.7 3.6 5.5 V V PSRR V+D = V+A = V+IN, All from 2.7V to 3.6V V+D = V+A = 3V, V+IN from 4.5V to 5.5V l l 40 65 l l 30.9 54.9 CMRR Differential Short-Circuit Current Supply Current RBIAS Resistor Range CLKCNTL = 3V Clock Frequency Error < 3.5% Clock Frequency Error < 3% RBIAS Pin Voltage MIN 7 11 30.9k < RBIAS < 200k UNITS 8 14 40 60 mV mV mV mV dB dB 25 30 mA mA 50 85 dB dB 54.9 200 l Output Clock Duty Cycle l 45 CLKIO Pin High Level CLKCNTL = 0V (Note 5) Input Voltage l V+D - 0.3 CLKIO Pin Low Level Input Voltage CLKCNTL = 0V (Note 5) l CLKIO Pin Input Current CLKCNTL = 0V CLKIO = 0V (Note 6) CLKIO = V+D l l k k V 40 Clock Frequency Drift V+A, V+D from 2.7V to 3.6V, RBIAS = 30.9k Over Supply CLKCNTL Pin Open CLKIO Pin High Level V+A = V+D = 3V, CLKCNTL = 3V Output Voltage IOH = -1mA IOH = -4mA MAX 1.17 Clock Frequency Drift RBIAS = 30.9k CLKCNTL Pin Open Over Temperature RBIAS = 30.9k TYP ppm/C 0.2 0.5 %/V 50 55 % V 0.3 V 10 A A -1 2.95 2.9 V V 6603fa 4 LTC6603 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted. PARAMETER CONDITIONS MIN CLKIO Pin Low Level Output Voltage V+A = V+D = 3V, CLKCNTL = 3V IOL = 1mA IOL = 4mA 0.05 0.1 V V CLKIO Pin Rise Time V+A = V+D = CLKCNTL = 3V, CLOAD = 5pF 0.3 ns CLKIO Pin Fall Time V+A = V+D = CLKCNTL = 3V, CLOAD = 5pF 0.3 ns SER High Level Input Voltage Pin 17 l SER Low Level Input Voltage Pin 17 l SER Input Current Pin 17 = 0V (Note 6) Pin 17 = V+D l l -10 CLKCNTL High Level Input Voltage Pin 5 l V+D - 0.5 CLKCNTL Low Level Input Voltage Pin 5 CLKCNTL Input Current CLKCNTL = 0V (Note 6) CLKCNTL = V+D l l TYP MAX V+D - 0.3 -25 UNITS V 0.3 V 2 A A V -15 15 0.5 V 25 A A Pin Programmable Control Mode Specifications. Specifications apply to Pins 6, 9, 21 and 22 in pin programmable control mode. SYMBOL PARAMETER CONDITIONS MIN VIH Digital Input High Voltage Pins 6, 9, 21, 22 l VIL Digital Input Low Voltage Pins 6, 9, 21, 22 l IIN Digital Input Current Pins 6, 9, 21, 22 (Note 6) l TYP MAX UNITS V+D = 2.7V to 3.6V 2 V -1 0.8 V 1 A Serial Port DC and Timing Specifications. Specifications apply to Pins 6, 9-11, and 21 in serial programming mode. SYMBOL PARAMETER CONDITIONS MIN VIH Digital Input High Voltage Pins 6, 9, 10 l VIL Digital Input Low Voltage Pins 6, 9, 10 l -1 VSUPPLY - 0.3 TYP MAX UNITS V+D = 2.7V to 3.6V 2 V 0.8 V 1 A IIN Digital Input Current Pins 6, 9, 10 (Note 6) l VOH Digital Output High Voltage Pins 11, 21 Sourcing 500A l VOL Digital Output Low Voltage Pins 11, 21 Sinking 500A l t1 (Note 5) SDI Valid to SCLK Setup l 60 ns t2 (Note 5) SDI Valid to SCLK Hold l 0 ns V 0.3 V t3 SCLK Low l 100 ns t4 SCLK High l 100 ns t5 CS Pulse Width l 60 ns t6 (Note 5) LSB SCLK to CS l 60 ns t7 (Note 5) CS Low to SCLK l 30 t8 SDO Output Delay t9 (Note 5) SCLK Low to CS Low CL = 15pF l l ns 125 0 ns ns 6603fa 5 LTC6603 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: LTC6603C and LTC6603I are guaranteed functional over the operating temperature range of -40C to 85C. Note 3: LTC6603C is guaranteed to meet specified performance from 0C to 70C. The LTC6603C is designed, characterized and expected to meet specified performance from -40C to 85C but is not tested or QA sampled at these temperatures. The LTC6603I is guaranteed to meet the specified performance limits from -40C to 85C. Note 4: This test measures the internal oscillator accuracy (deviation from the fCLK equation). Variations in the internal oscillator cause variations in the filter cutoff frequency. See the "Applications Information" section. Note 5: Guaranteed by design, not subject to test. Note 6: To conform to the logic IC standard, current out of a pin is arbitrarily given a negative value. TYPICAL PERFORMANCE CHARACTERISTICS DC Gain Matching DC Gain Matching VS = 3V, BW = 2.5MHz GAIN SETTING = 0dB, TA = 25C 60 1000 UNITS VS = 3V, BW = 156.25kHz GAIN SETTING = 0dB, TA = 25C 60 1000 UNITS 50 50 40 30 30 20 40 30 20 20 10 10 5 0 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 MISMATCH (dB) 6603 G01 6603 G02 20 800 GAIN = 24dB 760 10 720 GAIN (dB) 0 35 30 20 10 1.5 2 2.5 6603 G04 -10 -20 -30 680 GAIN = 0dB 640 GAIN = 12dB 600 GAIN = 6dB 560 GROUP DELAY -40 520 -50 480 RBIAS = 30.9k, VS = 3V -60 LPF1 = 1, BW = 2.5MHz TA = 25C -70 10k 100k 1M FREQUENCY (Hz) GROUP DELAY (ns) 40 UNITS (%) 6603 G03 30 VS = 3V, BW = 156.25kHz f = 125kHz, TA = 25C 1000 UNITS 0 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 MISMATCH (DEG) 0 -2.5 -2-1.5-1-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 MISMATCH (DEG) Gain and Group Delay vs Frequency Phase Matching 50 15 10 0 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 MISMATCH (dB) 60 VS = 3V, BW = 2.5MHz f = 2MHz, TA = 25C 1000 UNITS 25 UNITS (%) UNITS (%) UNITS (%) Phase Matching 70 70 440 400 10M 6603 G05 6603fa 6 LTC6603 TYPICAL PERFORMANCE CHARACTERISTICS Gain and Group Delay vs Frequency Gain and Group Delay vs Frequency 10 3.1 10 2.9 0 -10 2.7 -20 2.5 -30 GROUP DELAY 2.3 -40 2.1 RBIAS = 30.9k, VS = 3V -50 LPF1 = 0, LPF0 = 1, -60 BW = 625kHz TA = 25C -70 10k 100k 1M FREQUENCY (Hz) 11.0 10.5 GAIN = 12dB -10 10.0 GAIN = 6dB GAIN = 0dB -20 9.5 GROUP DELAY -30 9.0 8.5 RBIAS = 30.9k, VS = 3V -50 LPF1 = LPF0 = 0, -60 BW = 156.25kHz TA = 25C -70 1k 10k 100k FREQUENCY (Hz) 1.7 1.5 10M Distortion vs Input Frequency 7.0 1M -75 HD2, GAIN = 0dB HD2, GAIN = 24dB 700 500 900 INPUT FREQUENCY (kHz) -75 HD3, GAIN = 24dB -80 HD2, GAIN = 24dB HD2, GAIN = 0dB -90 20 120 220 420 320 INPUT FREQUENCY (kHz) 6603 G09 HD3, f = 1MHz HD2, f = 1MHz -80 HD3, f = 200kHz HD2, f = 200kHz -100 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 OUTPUT VOLTAGE (VP-P) 6603 G11 HD3, GAIN = 24dB -80 HD2, GAIN = 24dB -85 HD2, GAIN = 0dB -90 -95 RBIAS = 30.9k, VS = 3V LPF1 = LPF0 = 0, BW = 156.25kHz VOUT = 2VP-P, TA = 25C -100 50 90 110 130 10 30 70 INPUT FREQUENCY (kHz) 0.2 Filter Cutoff Accuracy vs Temperature LPF1 = LPF0 = 0, BW = 156.25kHz 0.1 0.0 -0.1 -0.2 LPF1 = 0, LPF0 = 1, BW = 625kHz -0.3 -0.4 150 6603 G11 Filter Cutoff Accuracy vs Supply Voltage FILTER CUTOFF FREQUENCY DEVIATION (%) DISTORTION (dBc) 520 HD3, GAIN = 0dB -75 6603 G10 Distortion vs Output Voltage -90 6603 G08 Distortion vs Input Frequency -70 -85 1100 RBIAS = 30.9k, VS = 3V, LPF1 = 0, LPF0 = 1, BW = 2.5MHz, GAIN = 24dB, TA = 25C 500 900 1300 1700 INPUT FREQUENCY (kHz) -70 HD3, GAIN = 24dB 300 HD2, GAIN = 24dB -90 100 DISTORTION (dBc) -70 -90 100 HD2, GAIN = 0dB 7.5 RBIAS = 30.9k, VS = 3V LPF1 = 0, LPF0 = 1, BW = 625kHz -65 VOUT = 2VP-P, TA = 25C HD3, GAIN = 0dB DISTORTION (dBc) DISTORTION (dBc) HD3, GAIN = 0dB -85 -70 Distortion vs Input Frequency RBIAS = 54.9k, VS = 3V LPF1 = 1, BW = 1.41MHz TA = 25C -80 HD3, GAIN = 0dB -80 -60 -65 HD3, GAIN = 24dB 6603 G07 -60 -70 -60 8.0 6603 G06 -60 RBIAS = 30.9k, VS = 3V LPF1 = 1, BW = 2.5MHz VOUT = 2VP-P, TA = 25C 11.5 GAIN = 24dB -40 1.9 -50 LPF1 = 1, BW = 2.5MHz -0.5 -0.6 -0.7 -0.8 RBIAS = 30.9k TA = 25C -0.9 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) 6603 G13 FILTER CUTOFF FREQUENCY DEVIATION (%) GAIN (dB) 20 Distortion vs Input Frequency 12.0 GROUP DELAY (s) GAIN = 0dB 3.3 GROUP DELAY (ns) 0 30 DISTORTION (dBc) GAIN = 12dB GAIN = 6dB GAIN = 24dB 20 3.5 GAIN (dB) 30 1.0 VS = 3V 0.8 RBIAS = 30.9k 0.6 0.4 0.2 BW = 156.25kHz BW = 625kHz 0.0 -0.2 -0.4 BW = 2.5MHz -0.6 -0.8 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 6603 G14 6603fa 7 LTC6603 TYPICAL PERFORMANCE CHARACTERISTICS Common Mode Rejection Ratio Common Mode Rejection Ratio 110 GAIN = 0dB 90 80 50 VS = 3V, RBIAS = 30.9k 30 LPF1 = 1, BW = 2.5MHz TA = 25C 20 10k 100k 1M FREQUENCY (Hz) GAIN = 12dB 60 40 90 GAIN = 0dB 70 40 50 20 10k 100k 1M FREQUENCY (Hz) COMMON MODE REJECTION (dB) 10M 80 GAIN = 6dB 70 GAIN = 12dB 60 GAIN = 24dB 50 100 70 VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF1 = 1, BW = 625kHz, TA = 25C GAIN = 0dB GAIN = 6dB GAIN = 12dB GAIN = 24dB 60 CMR = VIN-CM/VOUT-DIFF 50 10k 100k 1M FREQUENCY (Hz) 10M 6603 G18 80 GAIN = 24dB GAIN = 0dB 70 60 50 10M GAIN = 6dB CMR = VIN-CM/VOUT-DIFF VS = 3V, RBIAS = 30.9k LPF1 = LPF0 = 0, BW = 156.25kHz, TA = 25C 1k 10k 100k FREQUENCY (Hz) 1M 6603 G20 OIP3 vs Average Signal Frequency 46 43 GAIN = 12dB GAIN = 6dB GAIN = 0dB 42 40 44 GAIN = 12dB GAIN = 0dB 41 39 GAIN = 12dB GAIN = 6dB OIP3 (dBm) OIP3 (dBm) 90 OIP3 vs Average Signal Frequency 41 GAIN = 24dB 37 36 GAIN = 12dB 6603 G19 OIP3 vs Average Signal Frequency 38 Common Mode Rejection 100 90 80 1M 6603 G17 42 GAIN = 24dB 40 GAIN = 0dB VS = 3V, RBIAS = 30.9k, TA = 25C 35 LPF1 = 0, LPF0 = 1, BW = 625kHz VOUT = 6dBm PER TONE FOR 2-TONE TEST f = 10kHz 34 100 500 900 1300 1700 2100 2500 AVERAGE FREQUENCY OF TWO TONES (kHz) 6603 G21 38 VS = 3V, RBIAS = 30.9k, TA = 25C LPF1 = 0, LPF0 = 1, BW = 625kHz VOUT = 6dBm PER TONE FOR 2-TONE TEST f = 10kHz 36 0 100 200 300 400 500 600 AVERAGE FREQUENCY OF TWO TONES (kHz) 6603 G22 OIP3 (dBm) COMMON MODE REJECTION (dB) 110 CMR = VIN-CM/VOUT-DIFF 40 VS = 3V, RBIAS = 30.9k LPF1 = 1, BW = 2.5MHz, TA = 25C 30 10k 100k 1M FREQUENCY (Hz) VS = 3V, RBIAS = 30.9k 40 LPF1 = LPF0 = 0, BW = 156.25kHz, TA = 25C 30 1k 10k 100k FREQUENCY (Hz) Common Mode Rejection GAIN = 0dB GAIN = 6dB 6603 G16 Common Mode Rejection 90 GAIN = 0dB 70 60 6603 G15 100 80 50 30 10M GAIN = 12dB 100 GAIN = 24dB CMRR (dB) 60 GAIN = 24dB 110 80 GAIN = 6dB GAIN = 12dB GAIN = 24dB CMRR (dB) CMRR (dB) 70 VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF0 = 1, BW = 625kHz, TA = 25C 100 GAIN = 6dB 90 Common Mode Rejection Ratio 120 COMMON MODE REJECTION (dB) 100 40 39 GAIN = 6dB GAIN = 24dB 38 37 36 35 VS = 3V, RBIAS = 30.9k, TA = 25C LPF1 = 0, LPF0 = 1, BW = 156.25kHz VOUT = 6dBm PER TONE FOR 2-TONE TEST f = 10kHz 20 40 60 80 100 120 140 160 AVERAGE FREQUENCY OF TWO TONES (kHz) 6603 G23 6603fa 8 LTC6603 TYPICAL PERFORMANCE CHARACTERISTICS Output Impedance vs Frequency 41 39 BW = 625kHz, FREQUENCY = 200kHz 38 BW = 156.25kHz, FREQUENCY = 60kHz 37 36 VS = 3V, RBIAS = 30.9k, TA = 25C 180 LPF1 = 0, LPF0 = 1, BW = 625kHz 1 LPF1 = LPF0 = 0, BW = 156.25kHz 0.1 LPF1 = 1, BW = 2.5MHz 0.01 0.001 -30 -10 10 30 50 TEMPERATURE (C) 70 90 1k 10k 100k 1M FREQUENCY (Hz) TA = 25C RBIAS = 30.9k BW = 625kHz 100 BW = 156.25kHz -10 10 30 50 TEMPERATURE (C) 70 2 1 -2 -14 -12 -10 90 -2 0 2 VOLTAGE NOISE DENSITY (nV/Hz) GAIN = 12dB GAIN = 24dB 1 VS = 3V, RBIAS = 30.9k LPF1 = 1, BW = 2.5MHz TA = 25C 10M 6603 G30 0 5 10 15 IRBIAS (A) 20 25 6603 G29 Input Referred Noise Density GAIN = 0dB GAIN = 6dB 100k 1M FREQUENCY (Hz) 1.15 1.10 -8 -6 -4 TIME (ns) Input Referred Noise Density 1000 1000 0.1 10k 1.20 6603 G28 Input Referred Noise Density 10 TA = 25C VS = 3V -1 1000 VOLTAGE NOISE DENSITY (nV/Hz) 6603 G26 RBIAS = 30.9k, VS = 3V TA = 25C 6603 G27 100 BW = 156.25kHz RBIAS Pin Voltage vs IRBIAS 0 -30 100 1.25 3 140 VOLTAGE (V) SUPPLY CURRENT (mA) 4 BW = 2.5MHz 60 -50 BW = 625kHz 120 60 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) 10M RBIAS PIN VOLTAGE (V) 5 80 140 Clock Output Operating at 80MHz Supply Current vs Temperature 120 BW = 2.5MHz 160 6603 G25 6603 G23 160 TA = 25C RBIAS = 30.9k 80 BW = 2.5MHz, FREQUENCY = 1MHz 35 -50 180 Supply Current vs Supply Voltage 200 VOLTAGE NOISE DENSITY (nV/Hz) OIP3 (dBm) 40 OUTPUT IMPEDANCE () VS = 3V, RBIAS = 30.9k PASSBAND GAIN = 24dB VOUT = 6dBm PER TONE FOR 2-TONE TEST f = 10kHz 10 SUPPLY CURRENT (mA) OIP3 vs Temperature 42 GAIN = 0dB GAIN = 6dB 100 GAIN = 12dB GAIN = 24dB 10 VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF0 = 1, BW = 625kHz TA = 25C 1 10k 100k 1M FREQUENCY (Hz) GAIN = 0dB GAIN = 6dB 100 GAIN = 24dB 10 1 10M 6603 G31 GAIN = 12dB VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF0 = 0, BW = 156.25kHz TA = 25C 1k 10k 100k FREQUENCY (Hz) 1M 6603 G32 6603fa 9 LTC6603 TYPICAL PERFORMANCE CHARACTERISTICS Integral Input Referred Noise VS = 3V, RBIAS = 30.9k LPF1 = 1,BW = 2.5MHz TA = 25C GAIN = 6dB 100 VOLTAGE NOISE (V) VOLTAGE NOISE (V) 1000 GAIN = 0dB 10 GAIN = 12dB Integral Input Referred Noise 1000 VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF0 = 1, BW = 625kHz TA = 25C GAIN = 0dB GAIN = 6dB 100 GAIN = 12dB GAIN = 24dB 10 VOLTAGE NOISE (V) Integral Input Referred Noise 1000 VS = 3V, RBIAS = 30.9k LPF1 = LPF0 = 0, BW = 156.25kHz TA = 25C GAIN = 0dB 100 GAIN = 6dB GAIN = 12dB GAIN = 24dB 10 GAIN = 24dB 1 10k 100k 1M INTEGRATION BW (Hz) 10M 1 10k 100k 1M INTEGRATION BW (Hz) 6603 G33 10M 6603 G34 1 10k 100k INTEGRATION BW (Hz) 1M 6603 G35 PIN FUNCTIONS V+IN (Pin 1): Input Voltage Supply (2.7V V 5.5V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1F capacitor unless it is tied to V+A (Pin 2). The bypass should be as close as possible to the IC, but is not as critical as the bypassing of V+A and V+D (Pin16). V+A (Pin 2): Analog Voltage Supply (2.7V V 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1F capacitor. The bypass should be as close as possible to the IC. VOCM (Pin 3): Output Common Mode Voltage Reference. If floated, an internal resistive divider sets the voltage on this pin to half the supply voltage (typically 1.5V), maximizing the dynamic range of the filter. If this pin is floated, it must be bypassed with a quality 1F capacitor to ground. This pin has a typical input impedance of 3.4k and may be overdriven. Driving this pin to a voltage other than the default value will reduce the signal range the filter can handle before clipping. RBIAS (Pin 4): Oscillator Frequency-Setting Resistor Input. The value of the resistor connected between this pin and ground determines the frequency of the master oscillator, and sets the bias currents for the filter networks. The voltage on this pin is held by the LTC6603 to approximately 1.17V. For best performance, use a precision metal film resistor with a value between 30.9k and 200k and limit the capacitance on this pin to less than 10pF. This resistor is necessary even if an external clock is used. CLKCNTL (Pin 5): Clock Control Input. This three-state input selects the function of CLKIO (Pin 15). Tying the CLKCNTL pin to ground allows the CLKIO pin to be driven by an external clock (CLKIO is the master clock input). If the CLKCNTL pin is floated, the internal oscillator is enabled, but the master clock is not present at the CLKIO pin (CLKIO is a no-connect). If the CLKCNTL pin is tied to V+D (Pin 16), the internal oscillator is enabled and the master clock is present at the CLKIO pin (CLKIO is the master clock output). To detect a floating CLKCNTL pin, the LTC6603 attempts to pull the pin toward mid-supply. This is realized with two internal 15A current sources, one tied to V+D and CLKCNTL and the other one tied to ground and CLKCNTL. Therefore, driving the CLKCNTL pin high requires sourcing approximately 15A. Likewise, driving the CLKCNTL pin low requires sinking 15A. When the CLKCNTL pin is floated, it should be bypassed by a 1nF capacitor to ground or be surrounded by a ground shield to prevent excessive coupling from other PCB traces. 6603fa 10 LTC6603 PIN FUNCTIONS LPF1(CS) (Pin 6): TTL Level Input. When in pin programmable control mode, this pin is the MSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the chip select input (active low). +INB, -INB (Pins 7, 8): Channel B Differential Inputs. The input range and input resistance are described in the Applications Information section. Input voltages which exceed V+IN (Pin 1) should be avoided. LPF0 (SCLK) (Pin 9): TTL Level Input. When in pin programmable control mode, this pin is the LSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the clock of the serial interface. SDI (Pin 10): TTL Level Input. When in pin programmable control mode, this pin is left floating; in serial control mode, this pin is the serial data input. SDO (Pin 11): TTL Level Input. When in pin programmable control mode, this pin is left floating; in serial control mode, this pin is the serial data output. -OUTB, +OUTB (Pins 12, 13): Channel B Differential Filter Outputs. These pins can drive 1k and/or 50pF loads. For larger capacitive loads, an external 100 series resistor is recommended for each output. The common mode voltage of the filter outputs is the same as the voltage at VOCM (Pin 3). GND (Pin 14): Ground. Should be tied to a ground plane for best performance. CLKIO (Pin 15): When CLKCNTL (Pin 5) is tied to ground, CLKIO is the master clock input. When CLKCNTL is floated, CLKIO is pulled to ground by a weak pulldown. When CLKCNTL is tied to V+D (Pin 16), CLKIO is the master clock output. When configured as a clock output, this pin can drive 1k and/or 5pF loads (heavier loads will cause inaccuracies). V+D (Pin 16): Digital Voltage Supply (2.7V V 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1F capacitor. The bypass should be as close as possible to the IC. SER (Pin 17): Interface Selection Input. When tied to V+D (Pin 16) or floated, the interface is in pin programmable control mode, i.e. the filter gain and cutoff frequencies are programmed by the GAIN1, GAIN0, LPF1 and LPF0 pins. When SER is tied to ground, the filter gain, the filter cutoff frequency and shutdown mode are programmed by the serial interface. -OUTA, +OUTA (Pins 18, 19): Channel A Differential Filter Outputs. These pins can drive 1k and/or 50pF loads. For larger capacitive loads, an external 100 series resistor is recommended for each output. The common mode voltage of the filter outputs is the same as the voltage at VOCM (Pin 3). CAP (Pin 20): Connect a 0.1F bypass capacitor to this pin. Pin 20 is a buffered version of Pin 3. GAIN0(D0) (Pin 21): TTL Level Input. When in pin programmable control mode, this pin is the LSB of the gain control code; in serial control mode, this pin is the LSB of the serial control register, an output. GAIN1 (Pin 22): TTL Level Input. When in pin programmable control mode, this pin is the MSB of the gain control code; in serial control mode, this pin is a no-connect. -INA, +INA (Pins 23, 24): Channel A Differential Inputs. The input range and input resistance are described in the Applications Information section. Input voltages which exceed V+IN (Pin 1) should be avoided. Exposed Pad (Pin 25): Ground. The Exposed Pad must be soldered to PCB. 6603fa 11 LTC6603 BLOCK DIAGRAM +INA -INA GAIN1 GAIN0(D0) CAP +OUTA 24 23 22 21 20 19 V+IN 1 18 -OUTA CHANNEL A GAIN LPF 17 SER V+A 2 CONTROL BIAS CLK V+A TO PIN 20 VOCM 3 16 V+D CONTROL LOGIC BIAS/OSC GND CLOCK GENERATOR RBIAS 4 15 CLKIO BIAS CLKCNTL 5 CONTROL GAIN CLK 14 GND LPF CHANNEL B LPF1(CS) 6 13 +OUTB 7 8 9 10 11 12 +INB -INB LPF0(SCLK) SDI SDO -OUTB 6603 BD TIMING DIAGRAM Timing Diagram of the Serial Interface t4 t1 t2 t6 t3 t7 SCLK t9 D3 SDI D2 D1 D0 D7 * * * * D4 D3 t5 CS t8 SDO D4 PREVIOUS BYTE D3 D2 D1 D0 D7 * * * * D4 CURRENT BYTE D3 6603 TD 6603fa 12 LTC6603 APPLICATIONS INFORMATION Theory of Operation (Refer to Block Diagram) pull-up to V+D. None of the logic inputs have an internal pull-up or pull-down. The LTC6603 features two matched filter channels, each containing gain control and lowpass filter networks that are controlled by a single control block and clocked by a single clock generator. The gain and cutoff frequency can be separately programmed. The two channels are not independent, i.e. if the gain is set to 24dB then both channels have a gain of 24dB. The filter can be clocked with an external clock source, or using the internal oscillator. A resistor connected to the RBIAS pin sets the bias currents for the filter networks and the internal oscillator frequency (unless driven by an external clock). Altering the clock frequency changes the filter bandwidth. This allows the filters to be "tuned" to many different bandwidths. Serial Interface Connecting SER to ground allows the filter to be controlled through the SPI serial interface. When CS is low, the serial data on SDI is shifted into an 8-bit shift register on the rising edge of the clock (SCLK), with the MSB transferred first (see Figure 3). Serial data on SDO is shifted out on the clock's falling edge. A high CS will load the 8 bits of the shift register into an 8-bit D-latch, which is the serial control register. The clock is disabled internally when CS is pulled high. Note: SCLK must be low before CS is pulled low to avoid an extra internal clock pulse. SDO is always active in serial mode (never tri-stated) and cannot be "wire-ORed" to other SPI outputs. In addition, SDO is not forced to zero when CS is pulled high. Pin Programmable Interface As shown in Figure 1, connecting SER to V+D allows the filter to be directly controlled through the pin programmable control lines GAIN1, GAIN0, LPF1 and LPF0. The GAIN0(D0) pin is bidirectional (input in pin programmable control mode, output in serial mode). In pin programmable control mode, the voltage at GAIN0(D0) cannot exceed V+D; otherwise, large currents can be injected to V+D through the parasitic diodes (see Figure 2). Connecting a 10k resistor at the GAIN0(D0) pin (see Figure 1) is recommended for current limiting, to less than 10mA. SER has an internal An LTC6603 may be daisy-chained with other LTC6603s or other devices having serial interfaces. Daisy chaining is accomplished by connecting the SDO of the lead chip to the SDI of the next chip, while SCLK and CS remain common to all chips in the daisy chain. The serial data is clocked to all the chips then the CS signal is pulled high to update all of them simultaneously. Figure 4 shows an example of two LTC6603s in a daisychained SPI configuration. 3.3V 3.3V LTC6603 0.1F + V+IN V+A V+A V+D V+D +INA +OUTA -INA -OUTA + + VOUT VIN - LTC6603 0.1F V+IN +INA +OUTA -INA -OUTA - + VOUT VIN - SER - SER LPF1 LPF1(CS) LPF1(CS) LPF0 LPF0(SCLK) LPF0(SCLK) P GAIN1 GAIN0(D0) GND LOWPASS CUTOFF = 2.5MHz (fCLK = 80MHz) GAIN = 4 GAIN1 GAIN1 GAIN0 10k GAIN0(D0) GND GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR. 10k RESISTORS ON GAIN0(OUT) PROTECTS THE DEVICE WHEN VGAIN0 > V+D 6603 F01 Figure 1. Filter in Pin Programmable Control Mode 6603fa 13 LTC6603 APPLICATIONS INFORMATION SHUTDOWN NO 4-BIT GAIN, BW FUNCTION CONTROL CODE OUT V+D CS GAIN0(D0) (INTERNAL NODE) 8-BIT LATCH Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8-BIT SHIFT-REGISTER SDI SDO SCLK 6603 F02 6603 F03 Figure 2. Bidirectional Design of GAIN0(OUT) Pin Figure 3. Diagram of Serial Interface (MSB First Out) 3.3V 3.3V 0.1F V+IN + LTC6603 #1 0.1F V+A V+A V+D V+D SCLK +OUTA + -INA -OUTA - SER SER LPF1(CS) LPF1(CS) LPF0(SCLK) SDI +INA VOUT2 - - -OUTA -INA LTC6603 #2 VIN2 VOUT1 CSX P + + +OUTA +INA VIN1 - V+IN GAIN0(D0) OUT1 LPF0(SCLK) SDO SDI GAIN0(D0) SDO SDO SDI GND OUT2 GND SCLK SDI D15 D11 D10 D9 D8 GAIN, BW CONTROL WORD FOR #2 SHUTDOWN FOR #2 D7 D3 D2 D1 D0 GAIN, BW CONTROL WORD FOR #1 SHUTDOWN FOR #1 CS 6603 F04 Figure 4. Two Devices in a Daisy Chain Serial Control Register Definition D7 D6 D5 D4 GAIN0 GAIN1 LPF0 LPF1 D3 D2 NO FUNCTION NO FUNCTION D1 D0 SHDN OUT 6603fa 14 LTC6603 APPLICATIONS INFORMATION GAIN1 and GAIN0 are the gain control bits (register bits D6 and D7 when in serial mode). Their function is shown in Table 1. In serial mode, register bit D1 can be set to 1 to put the device into a low power shutdown mode. Register bit D0 is a general purpose output (Pin 21) when in serial mode. Table 1. Gain Control GAIN 1 GAIN 0 PASSBAND GAIN (dB) 0 0 0 0 1 6 1 0 12 1 1 24 Self-Clocking Operation The LTC6603 features a unique internal oscillator which sets the filter cutoff frequency using a single external resistor connected to the RBIAS pin. The clock frequency is determined by the following simple formula (see Figure 5): fCLK = 247.2MHz * 10k/RBIAS be accurately varied from 24.14kHz to 2.5MHz. Table 2 summarizes the cutoff frequencies that can be obtained with an external resistor (RBIAS) value of 30.9k. Note that the cutoff frequencies scale with the clock frequency. For example, if LPF1 and LPF0 are both equal to zero, and RBIAS is increased from 30.9k to 200k, fCLK will decrease from 80MHz to 12.36MHz and the cutoff frequency will be reduced from 156.25kHz to 24.14kHz. The cutoff frequencies that can be obtained with external resistor values of 54.9k and 200k are shown in Table 3 and Table 4, respectively. When the LTC6603 is programmed for the cutoff frequencies lower than the maximum, the power is automatically reduced. The power savings at the middle bandwidth setting (LPF1 = 0, LPF0 = 1), is about 23%, while the power savings at the lowest bandwidth setting (LPF1 = 0, LPF0 = 0) is about 60%. Table 2. Cutoff Frequency Control, RBIAS = 30.9k, fCLK = 80MHz LPF1 LPF0 LOWPASS BW(kHz) 0 0 156.25 0 1 625 1 0 2500 1 1 2500 Note: RBIAS 200k The design is optimized for V+A, V+D = 3V, fCLK = 45MHz, where the filter cutoff frequency error is typically <3% when a 0.1% external 54.9k resistor is used (any resistor (RBIAS) tolerance, will shift the clock frequency). With different resistor values and cutoff frequency control settings (LPF1 and LPF0), the lowpass cutoff frequency can LPF1 LPF0 LOWPASS BW(kHz) 0 0 87.94 0 1 351.78 1 0 1407 1 1 1407 Table 4. Cutoff Frequency Control, RBIAS = 200k, fCLK = 12.36MHz 200 175 150 RBIAS (k) Table 3. Cutoff Frequency Control, RBIAS = 54.9k, fCLK = 45MHz LPF1 LPF0 LOWPASS BW(kHz) 0 0 24.14 0 1 96.56 125 1 0 386.25 100 1 1 386.25 75 50 25 10 20 30 40 50 60 70 DESIRED CLOCK FREQUENCY (MHz) 80 6603 F05 Figure 5. RBIAS vs Desired Clock Frequency 6603fa 15 LTC6603 APPLICATIONS INFORMATION The following graphs show a few of the possible lowpass filters. Gain and Group Delay vs Frequency (2.5MHz Lowpass Response) 1.2 GAIN -20 1.0 -40 0.8 0.6 -60 GROUP DELAY -80 0.4 -100 0.2 -120 100k 1M FREQUENCY (Hz) GROUP DELAY (s) GAIN (dB) 0 2N * R1 k , Gain and Group Delay vs Frequency (650kHz Lowpass Response) 4 0 GAIN GAIN (dB) -80 100k 2 GROUP DELAY GROUP DELAY (s) 3 -20 1 -60 In this circuit, the LTC2621 (a 12-bit DAC) is daisy-chained with the LTC6603. Because the sinking current from the RBIAS pin is: 2N * R1 the equivalent RBIAS is: 6603 G17 -40 The oscillator may be programmed by any method that sinks a current out of the RBIAS pin. The circuit in Figure 6 sets the clock frequency by using a programmable current source and in the expression for fCLK, the resistor RBIAS is replaced by the ratio of 1.17V/ICONTROL. Because the voltage of the RBIAS pin is approximately 1.17V 5%, the Figure 6 circuit is less accurate than if a resistor controls the clock frequency. VRBIAS * k 0 10M Alternative Methods of Setting the Clock Frequency of the LTC6603 0 1M FREQUENCY (Hz) 6603 G18 The oscillator is sensitive to transients on the positive supply. The IC should be soldered to the PC board and the PCB layout should include a 0.1F ceramic capacitor between V+A (Pin 2) and ground, as close as possible to the IC to minimize inductance. The PCB layout should also include an additional 0.1F ceramic capacitor between V+D (Pin 16) and ground. Avoid parasitic capacitance on RBIAS (Pin 4) and avoid routing noisy signals near RBIAS. Use a ground plane connected to Pin 14 and the Exposed Pad (Pin 25). where k is the binary DAC input code and N is the resolution. Figure 7 shows some of the frequency responses that can be obtained using this circuit. Figure 8 shows the LTC6603's oscillator configured as a VCO. A voltage source is connected in series with the RBIAS resistor. The clock frequency, fCLK, will vary with VCONTROL. Again, this circuit decouples the relationship between the current out of the RBIAS pin and the voltage of the RBIAS pin; the frequency accuracy will be degraded. The clock frequency, however, will increase monotonically with decreasing VCONTROL. Operation Using an External Clock The LTC6603 may be clocked by an external oscillator for tighter bandwidth control by pulling CLKCNTL (Pin 5) to ground and driving a clock into CLKIO (Pin 15). If an external clock is used, the RBIAS resistor is still necessary. The value of RBIAS must be no larger than the value that would be required for using the internal oscillator. For example, a 100k resistor would program the internal oscillator for 24.705MHz, so an external oscillator frequency of 24.705MHz would require an RBIAS resistance of no more 6603fa 16 LTC6603 APPLICATIONS INFORMATION -INB 5V +INB 3V V+IN 5V +INA -INA V+ I RANGE = 6A TO 38.4A C7 100nF LTC6078 2 3 -IN R23 50k R24 50k C2 2.2F C1 100nF C3 2.2F R25 50k C4 100nF R26 50k V+ OUT +IN USE NARROW SHORT TRACES FOR MINIMUM CAPACITANCE. 1 2 Q1 RK7002AT116CT VOCM V- R1 30.5k 5V LTC6078 V+ 7 -IN OUT +IN V- 5V C16 50pF C17 50pF 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 V+IN +INA V+A -INA VOCM GAIN1 RBIAS GAIN0(D0) CLKCNTL VOCM CAP LPF1(CS) +OUTA +INB LTC6603 -OUTA -INB SER LPF0(SCLK) V+D CLK IO SDI GND SDO +OUTB -OUTB R4 100k C18 50pF C19 50pF +OUTA -OUTA C15 10nF +OUTB 6603 F06 -OUTB C8 100nF SPI INTERFACE VREF VCC 7 VOUT SDO SDI SCK LTC2621-1 CLR CS/LD GND LDAC 1 2 3 4 5 10 SDI SCLK CS 5V C9 1F CLR LOW WILL SET DAC TO MID-SCALE (WITH A LTC6603-1 VERSION). HAS ~100ms TC AT START-UP TO RESET TO ZERO-SCALE. DATA FORMAT DATA IS SHIFTED FROM MOSI (MASTER OUT, SLAVE IN) THRU LTC6603 INTO THE LTC2621. THE TOTAL PACKET IS 32 BITS. IT STARTS WITH A CONTROL BYTE (0011 XXXX) THEN MSB OF THE DAC, WITH DUMMY BITS AT THE END, 16 BITS (24 BITS TOTAL). THEN 8 BITS TO THE FILTER. D6 AND D7 = GAIN, D4 AND D5 = LPF, D1 = SHDN. D0 = GEN. PURPOSE OUTPUT. Figure 6. Current Controlled Clock Frequency 10 0 -10 GAIN (dB) -20 RBIAS -30 RBIAS -40 -50 VCONTROL -60 -70 VS = 3V TA = 25C -80 1k 10k 100k 1M FREQUENCY (Hz) 10M + - fCLK = 247.2MHz * (10k/RBIAS) * (1 - VCONTROL/1.17V) 6603 F08 6603 F07 Figure 7. Frequency Response Controlled by LTC2621-1 Figure 8. Voltage Controlled Clock Frequency 6603fa 17 LTC6603 APPLICATIONS INFORMATION than 100k. If the value of RBIAS is too large, the filters will not receive a large enough bias current, possibly causing errors due to insufficient settling. Be sure to obey the absolute maximum specifications when driving a clock into CLKIO (Pin 15). Input Common Mode and Differential Voltage Range The input signal range extends from zero to the V+IN supply voltage. This input supply can be tied to V+A and V+D, or driven up to 5.5V for increased input signal range. Figure 9 shows the distortion of the filter versus common mode input voltage with a 2VP-P differential input signal (V+IN = 5V). -60 DISTORTION (dBc) HD3, f = 1MHz -70 HD3, f = 200kHz -80 RBIAS = 30.9k, VS = 3V, V+IN = 5.5V LPF1 = 1, BW = 2.5MHz, GAIN = 24dB VOUT = VP-P, TA = 25C -90 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 COMMON MODE INPUT VOLTAGE (V) 5.0 control bits LPF1 and LPF0. The differential input impedance is a function of the clock frequency and the control bits LPF1, LPF0, GAIN1 and GAIN0. Table 5 shows the typical input impedances for a clock frequency of 80MHz. These input impedances are all proportional to 1/fCLK, so if the clock frequency were reduced by half to 40MHz, the impedances would be doubled. The typical variation in dynamic input impedance for a given clock frequency is -20% to +35%. Table 5. Differential, Common Mode Input Impedances, fCLK = 80MHz GAIN1 GAIN0 LPF1 DIFFERENTIAL COMMON MODE INPUT IMPEDANCE INPUT IMPEDANCE LPF0 (k) (k) 0 0 0 0 38 40 0 0 0 1 16 20 0 0 1 0 2.5 5 0 0 1 1 2.5 5 0 1 0 0 20 40 0 1 0 1 9.5 20 0 1 1 0 2.5 5 0 1 1 1 2.5 5 1 0 0 0 10 40 1 0 0 1 5.4 20 1 0 1 0 1.9 5 6603 F09 Figure 9. Distortion vs Common Mode Input Voltage (5V) For best performance, the inputs should be driven differentially. For single-ended signals, connect the unused input to VOCM (Pin 3) or to a quiet DC reference voltage. To achieve the best distortion performance, the input signal should be centered around the DC voltage of the unused input. Refer to the Typical Performance Characteristics section to estimate the distortion for a given input level. Dynamic Input Impedance The unique input sampling structure of the LTC6603 has a dynamic input impedance which depends on the configuration and the clock frequency. This dynamic input impedance has both a differential component and a common mode component. The common mode input impedance is a function of the clock frequency and the 1 0 1 1 1.9 5 1 1 0 0 5.2 40 1 1 0 1 2.8 20 1 1 1 0 1.6 5 1 1 1 1 1.6 5 Output Common Mode and Differential Voltage Range The output voltage is a fully differential signal with a common mode level equal to the voltage at VOCM. Any of the filter outputs may be used as single-ended outputs, although this will degrade the performance. The output voltage range is typically 0.5V to V+A - 0.5V (V+A = 2.7V to 3.6V). The common mode output voltage can be adjusted by overdriving the voltage present on VOCM. To maximize the undistorted peak-to-peak signal swing of the filter, the VOCM voltage should be set to V+A /2. Note that the output common mode voltages of the two channels are 6603fa 18 LTC6603 APPLICATIONS INFORMATION not independent as they are both set by the VOCM pin. Figure 10 illustrates the distortion versus output common mode voltage for a 2VP-P differential input voltage and a common mode input voltage that is equal to mid-supply. DISTORTION (dBc) -60 RBIAS = 30.9k, VS = 3V, GAIN = 24dB, TA = 25C SIGNAL FREQUENCY = 200kHz -65 HD3, LPF1 = 0, LPF0 = 1 -70 HD2, LPF1 = 0, LPF0 = 1 V RPULLUP = RCM SUPPLY 1 VICM where RCM = 40k*80MHz/fCLK for LPF1=0, LPF0=0 RCM = 20k*80MHz/fCLK for LPF1=0, LPF0=1 HD2, LPF1 = 1 -75 RCM = 5k*80MHz/fCLK for LPF1=1 HD3, LPF1 = 1 -80 0.8 1.0 1.4 1.2 1.6 1.8 COMMON MODE OUTPUT VOLTAGE (V) 6603 F10 Figure 10. Distortion vs Common Mode Output Voltage Interfacing to the LTC6603 The input and output common mode voltages of the LTC6603 are independent. The input common mode voltage is set by the signal source if DC-coupled, as shown in Figure 11. If the inputs are AC-coupled, as shown in Figure 12 (Circuit A), the input common mode voltage will be pulled to ground by an equivalent resistance of RCM, shown in Table 5. This does not affect the filter's performance as long as the input amplitude is less than 0.5VP-P. At low filter gain settings, a larger input voltage swing may be desired. VSUPPLY LTC6603 0.1F V+IN V+A V+D VIN+ + - VIN- + - 1F Connecting resistors between each input and V+IN will pull the input common mode voltage up, increasing the input signal swing. The resistance, RPULL-UP, necessary to set the input common mode voltage, VICM, to any desired level can be calculated by +INA +OUTA VOUT+ -INA -OUTA VOUT- VOCM GND DC-COUPLED INPUT VIN (COMMON MODE) = (VIN+ + VIN-)/2 VOUT (COMMON MODE) = (VOUT+ + VOUT-)/2 = VSUPPLY/2 6603 F11 Figure 11. DC-Coupled Inputs For example, if the lowpass cutoff frequency is set to 2.5MHz, 5k resistors connected between each input and V+IN will set the input common mode voltage to midsupply. Circuit A of Figure 12 is for a fixed CLK and LPF0, LPF1 setting. If the clock varies or the LPF0, LPF1 setting changes then Circuit B of Figure 12 should be used. Due to the sampled data nature of the filter, an anti-aliasing filter at the inputs is recommended. The output common mode voltage is equal to the voltage of the VOCM pin. The VOCM pin is biased to one-half of the supply voltage by an internal resistive divider (see Block Diagram). To alter the common mode output voltage, VOCM can be driven with an external voltage source or resistor network. If external resistors are used, it is important to note that the internal 2k resistors can vary 30% (their ratio varies only 1%). The filter outputs can also be AC-coupled. The LTC6603 can be interfaced to an A/D converter by pulling CLKCNTL (Pin 5) to V+D. This configures CLKIO (Pin 15) as a clock output, which can be used to drive the clock input of the A/D converter. This allows the A/D converter to be synchronized with the filter sampling clock, avoiding "beat frequencies" and simplifying the board layout. Any routing attached to the CLKIO pin should be as short as possible, in order to minimize reflections. Similarly, the LTC6603 can be interfaced to another LTC6603 in a master/slave configuration as shown in Figure 13. This 6603fa 19 LTC6603 APPLICATIONS INFORMATION CIRCUIT A VSUPPLY VSUPPLY LTC6603 0.1F RPULL-UP V+IN RPULL-UP V+A V+D 0.1F VIN+ + - VIN- + - 0.1F +INA +OUTA VOUT+ -INA -OUTA VOUT- VOCM 1F GND AC-COUPLED INPUT VIN (COMMON MODE) = VOUT (COMMON MODE) = VSUPPLY/2 CIRCUIT B V+IN 0.1F V+A VSUPPLY LTC6603 0.1F 1.87k V+IN V+A 1.87k 0.1F + - VIN+ 1.87k + - VIN- 0.1F V+D 1.87k 1F +INA +OUTA VOUT+ -INA -OUTA VOUT- VOCM GND AC-COUPLED INPUT VIN (COMMON MODE) = RCM * V 2 * RCM IN 1.87k 6603 F12 Figure 12. AC-Coupled Inputs 3.3V 3.3V LTC6603 MASTER 0.1F + V+IN V+IN V+A V+A V+D V+D +INA +OUTA VIN1 - LTC6603 SLAVE 0.1F -INA -OUTA + + VOUT1 VIN2 - - +INA +OUTA + VOUT2 -INA CLKCNTL CLKCNTL CLKIO CLKIO GND GND -OUTA - 6603 F13 Figure 13. Two Devices in a Master/Slave Clocking Configuration 6603fa 20 LTC6603 APPLICATIONS INFORMATION results in four matched filter channels, all synchronized to the same clock. The master has its CLKCNTL pin pulled to V+D, configuring its CLKIO pin as an output, while the slave has its CLKCNTL pin pulled to ground, configuring its CLKIO pin as an input. Note that in order to synchronize the two filters, the clock frequency must not be buffered. This requires that the filters be close together on the PC board. If the clock is buffered, the filters would have matching bandwidths, but would not be synchronized. Output Drive The filter outputs can drive 1k and/or 50pF loads connected to AC ground with a 0.5V to 2.5V signal (corresponding to a 4VP-P differential signal). For differential loads (loads connected between +OUTA and -OUTA or +OUTB and -OUTB) the outputs can produce a 4VP-P signal across 2k and/or 25pF. For smaller signal amplitudes, the outputs can drive correspondingly larger loads. For larger capacitive loads, an external 50 series resistor is recommended for each output. Clock Feedthrough Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics that are present at the filter's output. The clock feedthrough is measured with +INA and -INA (or +INB, -INB) tied to VOCM and depends on the PC board layout and the power supply decoupling. The clock feedthrough can be reduced with a simple RC post filter. Decoupling Capacitors The LTC6603 uses sampling techniques, therefore its performance is sensitive to supply noise. 0.1F ceramic decoupling capacitors must be connected from V+A (Pin 2) and V+D (Pin 16) to ground with leads as short as possible. A ground plane should be used. Noisy signals should be isolated from the filter's input pins. In addition, a 0.1F decoupling capacitor at Pin 20 is recommended since this pin receives clocked current injection. Aliasing Aliasing is an inherent phenomenon of sampled data filters. Significant aliasing only occurs when the frequency of the input signal approaches the sampling frequency or multiples of the sampling frequency. The ratio of the LTC6603 input sampling frequency to the clock frequency, fCLK, is determined by the state of control bits LPF1 and LPF0. Table 6 shows the possible input sampling frequencies for a clock frequency of 80MHz. The input sampling frequency is proportional to the clock frequency. For example, if the clock frequency is lowered from 80MHz to 40MHz, the input sampling frequency will be lowered by half. Input signals with frequencies near the input sampling frequency will be aliased to the passband of the filter and appear at the output unattenuated. Table 6. Input Sampling Frequency (fCLK = 80MHz) LPF1 LPF0 Input Sampling Frequency (MHz) 0 0 20 0 1 40 1 0 160 1 1 160 A simple LC anti-aliasing filter is recommended at the filter inputs to attenuate frequencies near the input sampling frequency that will be aliased to the passband. For example, if the clock frequency is set to 80MHz and the cutoff frequency of the filter is set to its maximum (LPF1 = 1), the lowest frequency that would be aliased to the passband would be fCLK - fCUTOFF, i.e., 160MHz - 2.5MHz = 157.5MHz. The LTC6603 filter inputs should be driven by a low impedance output (<100). Wideband Noise The wideband noise of the filter is the RMS value of the device's output noise spectral density. The wideband noise is nearly independent of the value of the clock frequency and excludes the clock feedthrough. Most of the wideband noise is concentrated in the filter passband and cannot be removed with post filtering. Power Supply Current The power supply current depends on the state of the lowpass cutoff frequency controls (LPF1, LPF0) and the value of RBIAS. When the LTC6603 is programmed for the middle cutoff frequency (LPF1 = 0, LPF0 = 1), the supply current is reduced by about 23% relative to the supply current for the higher bandwidth setting. Programming 6603fa 21 LTC6603 APPLICATIONS INFORMATION the LTC6603 for the lowest cutoff frequency (LPF1 = 0, LFP0 = 0) reduces the supply current by about 60%. Power supply current vs. cutoff frequency for various bandwidth settings is shown in the Typical Performance Characteristicst section. The LTC6603 can be programmed through the serial interface to enter into a low power shutdown mode. The power supply current during shutdown is less than 235A. To extend the filter's operational frequency range, the master clock is divided down before reaching the filter. LPF1 and LPF0 set the division ratio of the lowpass clock. Figure 14 shows the possible cutoff frequencies versus fCLK, LPF1 and LPF0. Overlapping frequency ranges allow more than one possible choice of bandwidth settings for some cutoff frequencies. Figure 15 shows supply current as a function of the filter cutoff frequency, LPF1 and LPF0. Note that the higher bandwidth setting always gives the minimum supply current for a given cutoff frequency. The input referred integrated noise voltage for a passband gain of 24dB is shown in Table 7. Note that the noise is higher for the higher bandwidth settings. This creates a tradeoff between supply current and noise. For a given cutoff frequency, using the highest possible bandwidth setting gives the minimum supply current at the expense of higher noise. Supply Current vs Noise Trade-Off The passband of the LTC6603 is determined by the master clock frequency (which is set by RBIAS when the internal oscillator is used), LPF1 and LPF0. The LTC6603 is optimized for use with RBIAS having a value between 200k and 30.9k to set the internal oscillation frequency from 12.36MHz to 80MHz. The lowpass corner frequency is proportional to the clock frequency (internal or external). 180 100 160 SUPPLY CURRENT (mA) fCLK (MHz) LPF1 = 0 LPF0 = 0 LPF1 = 1 100k 1M FILTER CUTOFF FREQUENCY (Hz) 120 LPF1 = 0 LPF0 = 1 100 80 60 LPF1 = 1 LPF1 = 0 LPF0 = 0 40 LPF1 = 0 LPF0 = 1 10 10k 140 TA = 25C VS = 3V CLKCNTL PIN FLOATING GAIN = 0dB 20 0 10k 10M 100k 1M FILTER CUTOFF FREQUENCY (Hz) 10M 6603 F15 6603 F14 Figure 14. fCLK vs Filter Cutoff Frequencies Figure 15. Supply Current vs Filter Cutoff Frequency Table 7. Total Input Referred Integrated Noise Voltage (Passband Gain = 24dB) LPF1 LPF0 NOISE VOLTAGE 0 0 -81dBm 0 1 -80dBm 1 X -76dBm 6603fa 22 LTC6603 TYPICAL APPLICATIONS LTC6603 SPI Clock Control LTC6603 Parallel Clock Control 3V 24 23 7 8 4 R3 R2 R1 DIODES INC DMN2004DWK 0.1F 3 0.1F VOCM 20 22 21 14 CLK1 25 CLK0 1 2 V+IN V+A 3V 16 0.1 V+D +INA +OUTA -INA -OUTA +INB +OUTB -INB LTC6603 -OUTB RBIAS CLKIO SER VOCM CAP CLKCNTL GAIN1 SDO GAIN0(D0) SDI GND LPF0(SCLK) GND LPF1(CS) 24 19 23 18 DAC VOUT RANGE 0V TO 2.5V (USING THE LTC2630 INTERNAL REFERENCE) 13 7 8 12 15 1 17 2 3V 3 5 CS SCLK SDI VOUT GND V+ VC R2 6 VB 4 0.1F 5 0.1F 3 R1 4 LTC2630 8-BIT DAC 0.1F 3V 20 22 11 21 10 14 9 25 6 1 2 V+IN V+A 16 0.1F V+D +INA +OUTA -INA -OUTA +INB +OUTB -INB LTC6603 -OUTB RBIAS CLKIO VOCM SER CAP CLKCNTL GAIN1 SDO GAIN0(D0) SDI GND LPF0(SCLK) GND LPF1(CS) 19 18 13 12 15 17 5 3V 11 10 9 6 LPF1 LPF0 CS1 GAIN1 GAIN0 CLK1 0 0 1 1 IF R1 = 51.1k and R2 = 78.7k THEN THE fCLK RANGE IS 12.36MHz to 80MHz 6603 TA02 CLK0 0 1 0 1 RBIAS1 RBIAS2 RBIAS3 RBIAS4 RBIAS1 > RBIAS2 OR RBIAS3 RBIAS = 2472 fCLK RBIAS IN k fCLK in MHz R1 = RBIAS1 R2 = RBIAS1 * RBIAS2 RBIAS1 - RBIAS2 fCLK1 fCLK2 fCLK3 fCLK4 R1 = 12 5.282 * 1012 , R2 = 5.282 * 10 1.137fCLKHI + fCLKLO fCLKHI - fCLKLO fCLK SCK SDI CS2 6603 TA03 R1+ R2 VC = 2.472 * 1012 R1* R2 VB * R2 VC RANGE 0V to 2.5V, VB = 1.17V IF VC = 0V THEN fCLK= fCLKHI IF VC = 2.5V THEN fCLK= fCLKLO DESIGN PROCEDURE 1. CHOOSE fCLK1, fCLK2 AND fCLK3 2. CALCULATE RBIAS1, RBIAS2 AND RBIAS3 3. CALCULATE R2, R3 AND RBIAS4 R3 = RBIAS1 * RBIAS3 RBIAS1 - RBIAS3 RBIAS4 = R1 * R2 * R3 R1 * (R2 + R3) + R2 * R3 PACKAGE DESCRIPTION UF Package 24-Lead Plastic QFN (4mm x 4mm) (Reference LTC DWG # 05-08-1697) BOTTOM VIEW--EXPOSED PAD 4.00 0.10 (4 SIDES) 0.70 0.05 R = 0.115 TYP 0.75 0.05 PIN 1 TOP MARK (NOTE 6) PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45 CHAMFER 23 24 0.40 0.10 1 2 4.50 0.05 2.45 0.05 3.10 0.05 (4 SIDES) 2.45 0.10 (4-SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS (UF24) QFN 0105 0.200 REF 0.00 - 0.05 0.25 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6603fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC6603 TYPICAL APPLICATION Direct Conversion Demodulator and I and Q Baseband Filter, fCUTOFF =1.92MHz (UTMS WCDMA) 5V 3V 49.9 3.9pF 0.1F 56nH* 56nH* 0.1F 10pF RF IN 1 10pF 4 3 2 10pF 1 GND GND RF GND 5 EN 6 VCC 7 V 5V IOUT + 15 - I LTC5575 OUT QOUT + 14 - 13 Q CC 8 V CC 1F 0.1F 1000pF V+IN 100pF 24 10pF 56nH* 16 23 7 8 56nH* 4 OUT GND 10pF LO GND VCC 9 10 10pF 11 12 5.6pF 40.2k 0.1F 3 100pF 56nH* 2 V+A +INA 100pF 16 V+D +OUTA -INA -OUTA +INB +OUTB -INB LTC6603 -OUTB RBIAS CLKIO VOCM SER 19 49.9 56nH* 49.9 56nH* 10pF 18 13 12 15 100pF 17 49.9 56nH* 10pF QOUT 10pF 0.1F 10pF 20 1000pF 22 LO IN 21 14 25 CAP CLKCNTL GAIN1 SDO GAIN0(D0) SDI GND LPFO(SCLK) GND LPF1(CS) 5 3V 11 10 9 6 3V GAIN1 GAIN0 BASEBAND GAIN CONTROL *COILCRAFT 0603HP IOUT 6603 TA04 RELATED PARTS PART NUMBER DESCRIPTION (R) COMMENTS LTC 1565-31 650kHz Linear Phase Lowpass Filter Continuous Time, SO8 Package, Fully Differential LTC1566-1 Low Noise, 2.3MHz Lowpass Filter Continuous Time, SO8 Package LTC1567 Very Low Noise, High Frequency Filter Building Block 1.4nV/Hz Op Amp, MSOP Package, Differential Outputs LTC1568 Very Low Noise, 4th Order Building Block Lowpass and Bandpass Filter Designs Up to 10MHz, Differential Outputs LTC1569-6 Low Power 10-Pole Delay Equalized Elliptic Lowpass fC 64kHz, One Resistor Sets fC, SO-8 Differential Inputs LTC1569-7 10-Pole Delay Equalized Elliptic Lowpass fC 256kHz, One Resistor Sets fC, SO-8 Differential Inputs LT1994 Low Distortion, Low Noise Differential Amplifier/ADC Driver Adjustable, Low Power, VS = 2.375V to 12.6V LTC6406 3GHz Low Noise, Rail-to-Rail Input Differential ADC Driver Low Noise: 1.6nV/Hz, Low Power: 18A LT6600-2.5 Very Low Noise, Fully Differential Amplifier and 2.5MHz Filter 86dB S/N with 3V Supply, SO-8 Package LT6600-5 Very Low Noise, Fully Differential Amplifier and 5MHz Filter 82dB S/N with 3V Supply, SO-8 Package LT6600-10 Very Low Noise, Fully Differential Amplifier and 10MHz Filter 82dB S/N with 3V Supply, SO-8 Package LT6600-15 Very Low Noise, Fully Differential Amplifier and 15MHz Filter 76dB S/N with 3V Supply, SO-8 Package LT6600-20 Very Low Noise, Fully Differential Amplifier and 20MHz Filter 76dB S/N with 3V Supply, SO-8 Package LTC6601 Pin-Configurable Second Order Filter/Driver fC 7MHz to 27MHz Fully Differential 4mm x 4mm QFN Package LTC6602 Dual Baseband Bandpass Filter for UHF RFID Fully Differential 4mm x 4mm QFN Package LTC6604-2.5 Dual Very Low Noise, Differential Amp and 2.5MHz Filter 86dB S/N with 3V Supply, 4mm x 7mm QFN Package LTC6604-5 Dual Very Low Noise, Differential Amp and 5MHz Filter 82dB S/N with 3V Supply, 4mm x 7mm QFN Package LTC6604-10 Dual Very Low Noise, Differential Amp and 10MHz Filter 82dB S/N with 3V Supply, 4mm x 7mm QFN Package LTC6604-15 Dual Very Low Noise, Differential Amp and 15MHz Filter 76dB S/N with 3V Supply, 4mm x 7mm QFN Package 6603fa 24 Linear Technology Corporation LT 0709 REV A * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2008