LTC6603CUF#TRPBF - Linear Technology Corporation

LTC6603

6603fa

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Dual Adjustable

Lowpass Filter

The LTC

6603 is a dual, matched, programmable lowpass

ﬁ lter for communications receivers and transmitters. The

selectivity of the LTC6603, combined with its linear phase,

phase matching and dynamic range, make it suitable for

ﬁ ltering in many communications systems. With 1.5°

phase matching between channels, the LTC6603 can be

used in applications requiring pairs of matched ﬁ lters,

such as transceiver I and Q channels. Furthermore, the

differential inputs and outputs provide a simple interface

for most communications systems.

The sampled data ﬁ lter does not require an external clock

yet its cutoff frequency can be set with a single external

resistor with an accuracy of 3.5% or better. The external

resistor programs an internal oscillator whose frequency

is divided prior to being applied to the ﬁ lter networks.

This allows up to three cutoff frequencies that can be

obtained for each external resistor value, allowing the

cutoff frequency to be programmed over a range of more

than six octaves. Alternatively, the cutoff frequency can

be set with an external clock. The ﬁ lter gain can also be

programmed to 1, 2, 4 or 16.

The LTC6603 features a low power shutdown mode that

can be programmed through the serial interface and is

available in a 24-pin 4mm × 4mm QFN package.

2.5MHz I and Q Lowpass Filter and Dual ADC

n Guaranteed Phase and Gain Matching Specs

n Programmable BW Up to 2.5MHz

n Programmable Gain (0dB/6dB/12dB/24dB)

n 9th Order Linear Phase Response

n Differential, Rail-to-Rail Inputs and Outputs

n Low Noise: –145dBm/Hz (Input Referred)

n Low Distortion: –75dBc at 200kHz

n Simple Pin Programming or SPI Interface

n Set the Max Speed/Power with an External R

n Operates from 2.7V to 3.6V

n Input Range from 0V to 5.5V

n 4mm × 4mm QFN Package

n Small/Low Cost Basestations:

IDEN, PHS, TD-SCDMA, CDMA2000, WCDMA,

UMTS

n Low Cost Repeaters, Radio Links, and Modems

n 802.11x Receivers

n JTRS

6603 TA01a

+INA

V+IN V+AV+D

–INA

+INB

–INB

CAP

GAIN1

GAIN0

GND

RBIAS

VOCM

+OUTA

–OUTA

+OUTB

–OUTB

CLKCNTL

SDO

SDI

LPFO

LPF1

CLKIO

SER

LTC6603

0.1µF 0.1µF 180pF

180pF

10pF

180pF

10pF

49.9Ω 100nH*

*COILCRAFT 0603HP

49.9Ω 100nH*

5V 3V

0.1µF

30.9k

2.2µF

BASEBAND

GAIN CONTROL

LTC2297

14-BIT

ADC

14-BIT

ADC

VCM

IIN

QIN

I OUTPUT

Q OUTPUT

MISMATCH (DEG)

UNITS (%)

6603 TA01b

–2.5 2.5–2 –1.5 –1 –0.5 0 0.5 1 1.5 2

VS = 3V, BW = 156.25kHz

f = 125kHz, TA = 25°C

1000 UNITS

Phase Matching

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

LTC6603

6603fa

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

V+IN to GND ................................................................6V

V+A, V+D to GND .........................................................4V

V+A to V+D .............................................. –0.3V to +0.3V

Filter Inputs to GND ....................... –0.3V to V+IN + 0.3V

Pins 3, 4 to GND ............................. –0.3V to V+A + 0.3V

Pins 5, 6, 9-11,

15, 17, 21, 22 to GND .....................–0.3V to V+D + 0.3V

Output Short-Circuit Duration .......................... Indeﬁ nite

Operating Temperature Range (Note 2)

LTC6603CUF .......................................–40°C TO 85°C

LTC6603IUF ........................................–40°C TO 85°C

Speciﬁ ed Temperature Range (Note 3)

LTC6603CUF ...........................................0°C TO 70°C

LTC6603IUF ........................................–40°C TO 85°C

Storage Temperature Range ................... –65°C to 150°C

(Note 1)

24 23 22 21 20 19

789

TOP VIEW

UF PACKAGE

24-LEAD (4mm × 4mm) PLASTIC QFN

10 11 12

V+IN

V+A

VOCM

RBIAS

CLKCNTL

LPF1(CS)

–OUTA

SER

V+D

CLKIO

GND

+OUTB

+INA

–INA

GAIN1

GAIN0(D0)

CAP

+OUTA

+INB

–INB

LPFO(SCLK)

SDI

SDO

–OUTB

TJMAX = 150°C, θJA = 37°C/W, θJC = 4.3°C/W

EXPOSED PAD (PIN 25) IS GND. MUST BE SOLDERED TO THE PCB.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Filter Gain Either

Channel

External Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open

DC Gain, Gain Set = 0dB

fIN = 62.5kHz (0.4 • fC), Relative to DC Gain

fIN = 125kHz (0.8 • fC), Relative to DC Gain

fIN = 156.25kHz (fC), Relative to DC Gain

fIN = 234.375kHz (1.5 • fC), Relative to DC Gain

0.25

–0.5

0.4

–0.6

0.4

–0.3

0.6

–0.4

–32

0.55

–0.1

0.8

–0.2

–29.5

Matching of Filter

Gain

External Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open

DC Gain, Gain Set = 0dB

fIN = 62.5kHz (0.4 • fC)

fIN = 125kHz (0.8 • fC)

fIN = 156.25kHz (fC)

±0.03

±0.1

±0.15

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE

LTC6603CUF#PBF LTC6603CUF#TRPBF 6603 24-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C

LTC6603IUF#PBF LTC6603IUF#TRPBF 6603 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass

cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.

LTC6603

6603fa

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass

cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Filter Phase Either

Channel

External Clock = 80MHz, Filter Cutoff (fC) = 156.25kHz, VIN = 3.6VP-P, Pin 3 Open

fIN = 62.5kHz (0.4 • fC)

fIN = 125kHz (0.8 • fC)

fIN = 156.25kHz (fC)

158

–44

–152

161

–39

–146

163

–36

–142

deg

Matching of Filter

Phase

External Clock = 80MHz, Filter Cutoff (fC) = 156.25kHz, VIN = 3.6VP-P, Pin 3 Open

fIN = 62.5kHz (0.4 • fC)

fIN = 125kHz (0.8 • fC)

fIN = 156.25kHz (fC)

±0.2

±0.4

±0.5

±1.5

±3

±4

deg

Filter Gain Either

Channel

External Clock = 80MHz, Filter Cutoff (fC) = 2.5MHz, VIN = 3.6VP-P, Pin 3 Open

DC Gain, Gain Set = 0dB

fIN = 1MHz (0.4 • fC), Relative to DC Gain

fIN = 2MHz (0.8 • fC), Relative to DC Gain

fIN = 2.5MHz (fC), Relative to DC Gain

fIN = 4MHz (1.5 • fC), Relative to DC Gain

–2

–0.7

–1.1

0.5

–0.8

0.4

0.1

–43

1.2

–0.1

1.5

–32.6

Matching of Filter

Gain

External Clock = 80MHz, Filter Cutoff (fC) = 2.5MHz, VIN = 3.6VP-P, Pin 3 Open

fIN = 2MHz (0.8 • fC)

fIN = 2.5MHz (fC)

±0.05

±0.2

±0.4

Filter Phase

Either Channel

External Clock = 80MHz, Filter Cutoff (fC) = 2.5MHz, VIN = 3.6VP-P, Pin 3 Open

fIN = 1MHz (0.4 • fC)

fIN = 2MHz (0.8 • fC)

fIN = 2.5MHz (fC)

150

–45

–152

155

–39

–141

159

–28

–126

deg

Matching of Filter

Phase

External Clock = 80MHz, Filter Cutoff (fC) = 2.5MHz, VIN = 3.6VP-P, Pin 3 Open

fIN = 1MHz (0.4 • fC)

fIN = 2MHz (0.8 • fC)

fIN = 2.5MHz (fC)

±2.5

±4

deg

Filter Cutoff Accuracy

when Self Clocked

CLKCNTL = 3V (Note 4)

RBIAS = 200k

RBIAS = 54.9k

RBIAS = 30.9k

±3

±3.5

DC Gain Filter Cutoff (fC) = 2.5MHz, 0.6V to 2.4V Each Output, Pin 3 Open

Gain Setting = 0dB

Gain Setting = 6dB

Gain Setting = 12dB

Gain Setting = 24dB

5.6

11.2

22.5

0.5

11.8

23.2

1.2

6.6

12.5

DC Gain Matching Filter Cutoff (fC) = 2.5MHz, 0.6V to 2.4V Each Output, Pin 3 Open

Gain Setting = 0dB

Gain Setting = 6dB

Gain Setting = 12dB

Gain Setting = 24dB

±0.1

±0.05

±0.1

±0.2

±0.1

±0.15

±0.2

Noise At 200kHz Voltage Noise Referred to the Input

Gain = 0dB

Gain = 6dB

Gain = 12dB

Gain = 24dB

–124

–129

–135

–145

dBm/Hz

Integrated Noise Noise Bandwidth = 5MHz, Referred to the Input

Gain = 0dB

Gain = 6dB

Gain = 12dB

Gain = 24dB

–53

–59

–65

–76

dBm

THD VIN = 2VP-P, fIN = 200kHz, Gain Setting = 24dB –75 dB

Input Impedance Gain = 24dB, RBIAS = 30.9k, Filter Cutoff (fC) = 2.5MHz

Differential

Common Mode

1.6

k

LTC6603

6603fa

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass

cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Differential Input Referred Differential Offset Voltage at Either Output

Lowest Cutoff Frequency, Gain Setting = 24dB

Highest Cutoff Frequency, Gain Setting = 24dB

Lowest Cutoff Frequency, Gain Setting = 0dB

Highest Cutoff Frequency, Gain Setting = 0dB

±8

±14

±40

±60

CMRR Differential fC = 625kHz

Common Mode Input from 0V to 3V, V+IN = 3V

Common Mode Input from 0V to 5V, V+IN = 5V

VOCM Pin Voltage V+A = V+D = 3V, Pin 3 Open, fC = 156.25kHz l1.3 1.45 1.5 V

VOCM Pin Input

Impedance

V+A = V+D = 3V, Pin 3 Open, fC = 156.25kHz l2.5 3.4 4.5 k

VOSCM Common Mode Offset Voltage, VOCM = 1.5V, Supplies = 3V

VOSCM = VOUT-CM – VOCM

l100 185 mV

Output Swing fC = 156.25kHz

Source 1mA, Relative to V+A

Sink 1mA, Relative to GND

200

150

500

400

Short-Circuit Current fC = 156.25kHz

Sourcing

Sinking

Supply Current Internal Clock (RBIAS = 30.9k); Sum of the Currents into V+D, V+A, and V+IN All

Supplies Set to 3V

fC = 156.25kHz

fC = 625kHz

fC = 2.5MHz

121

162

130

175

Supply Current,

Shutdown Mode

Sum of the Currents into V+D, V+A, and V+IN; All Supplies Set to 3V

Shutdown Via Serial Interface l170 235 µA

Supply Voltage V+D, V+A Relative to GND

V+IN Relative to GND

2.7

3.6

5.5

PSRR V+D = V+A = V+IN, All from 2.7V to 3.6V

V+D = V+A = 3V, V+IN from 4.5V to 5.5V

RBIAS Resistor Range CLKCNTL = 3V

Clock Frequency Error < ±3.5%

Clock Frequency Error < ±3%

30.9

54.9

200

k

RBIAS Pin Voltage 30.9k < RBIAS < 200k 1.17 V

Clock Frequency Drift

Over Temperature

RBIAS = 30.9k

CLKCNTL Pin Open

40 ppm/ºC

Clock Frequency Drift

Over Supply

V+A, V+D from 2.7V to 3.6V, RBIAS = 30.9k

CLKCNTL Pin Open

l0.2 0.5 %/V

Output Clock Duty

Cycle

RBIAS = 30.9k l45 50 55 %

CLKIO Pin High Level

Input Voltage

CLKCNTL = 0V (Note 5) lV+D – 0.3 V

CLKIO Pin Low Level

Input Voltage

CLKCNTL = 0V (Note 5) l0.3 V

CLKIO Pin Input

Current

CLKCNTL = 0V

CLKIO = 0V (Note 6)

CLKIO = V+D

–1

µA

CLKIO Pin High Level

Output Voltage

V+A = V+D = 3V, CLKCNTL = 3V

IOH = –1mA

IOH = –4mA

2.95

2.9

LTC6603

6603fa

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =

2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

CLKIO Pin Low Level

Output Voltage

V+A = V+D = 3V, CLKCNTL = 3V

IOL = 1mA

IOL = 4mA

0.05

0.1

CLKIO Pin Rise Time V+A = V+D = CLKCNTL = 3V, CLOAD = 5pF 0.3 ns

CLKIO Pin Fall Time V+A = V+D = CLKCNTL = 3V, CLOAD = 5pF 0.3 ns

SER High Level

Input Voltage

Pin 17 lV+D – 0.3 V

SER Low Level

Input Voltage

Pin 17 l0.3 V

SER Input Current Pin 17 = 0V (Note 6)

Pin 17 = V+D

–10

µA

CLKCNTL High Level

Input Voltage

Pin 5 lV+D – 0.5 V

CLKCNTL Low Level

Input Voltage

Pin 5 0.5 V

CLKCNTL Input

Current

CLKCNTL = 0V (Note 6)

CLKCNTL = V+D

–25 –15

15 25

µA

Pin Programmable Control Mode Speciﬁ cations. Speciﬁ cations apply to Pins 6, 9, 21 and 22 in pin programmable control mode.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V+D = 2.7V to 3.6V

VIH Digital Input High Voltage Pins 6, 9, 21, 22 l2V

VIL Digital Input Low Voltage Pins 6, 9, 21, 22 l0.8 V

IIN Digital Input Current Pins 6, 9, 21, 22 (Note 6) l–1 1 µA

Serial Port DC and Timing Speciﬁ cations. Speciﬁ cations apply to Pins 6, 9-11, and 21 in serial programming mode.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V+D = 2.7V to 3.6V

VIH Digital Input High Voltage Pins 6, 9, 10 l2V

VIL Digital Input Low Voltage Pins 6, 9, 10 l0.8 V

IIN Digital Input Current Pins 6, 9, 10 (Note 6) l–1 1 µA

VOH Digital Output High Voltage Pins 11, 21 Sourcing 500µA lVSUPPLY – 0.3 V

VOL Digital Output Low Voltage Pins 11, 21 Sinking 500µA l0.3 V

t1 (Note 5) SDI Valid to SCLK Setup l60 ns

t2 (Note 5) SDI Valid to SCLK Hold l0ns

t3SCLK Low l100 ns

t4SCLK High l100 ns

t5CS Pulse Width l60 ns

t6 (Note 5) LSB SCLK to CS l60 ns

t7 (Note 5) CS Low to SCLK l30 ns

t8SDO Output Delay CL = 15pF l125 ns

t9 (Note 5) SCLK Low to CS Low l0ns

LTC6603

6603fa

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: LTC6603C and LTC6603I are guaranteed functional over the

operating temperature range of –40°C to 85°C.

Note 3: LTC6603C is guaranteed to meet speciﬁ ed performance from

0°C to 70°C. The LTC6603C is designed, characterized and expected to

meet speciﬁ ed performance from –40°C to 85°C but is not tested or QA

sampled at these temperatures. The LTC6603I is guaranteed to meet the

speciﬁ ed performance limits from –40°C to 85°C.

TYPICAL PERFORMANCE CHARACTERISTICS

DC Gain Matching DC Gain Matching Phase Matching

Phase Matching

Gain and Group Delay

vs Frequency

Note 4: This test measures the internal oscillator accuracy (deviation from

the fCLK equation). Variations in the internal oscillator cause variations in

the ﬁ lter cutoff frequency. See the “Applications Information” section.

Note 5: Guaranteed by design, not subject to test.

Note 6: To conform to the logic IC standard, current out of a pin is

arbitrarily given a negative value.

MISMATCH (dB)

UNITS (%)

6603 G01

–0.2 0.2–0.15 –0.1 –0.05 0 0.05 0.1 0.15

VS = 3V, BW = 2.5MHz

GAIN SETTING = 0dB, TA = 25°C

1000 UNITS

MISMATCH (dB)

UNITS (%)

6603 G02

–0.06 0.1–0.04–0.02 0 0.02 0.04 0.06 0.08

VS = 3V, BW = 156.25kHz

GAIN SETTING = 0dB, TA = 25°C

1000 UNITS

MISMATCH (DEG)

UNITS (%)

6603 G03

–2.5 4–2–1.5–1–0.5 0 0.5 1 1.5 2 2.5 3 3.5

VS = 3V, BW = 2.5MHz

f = 2MHz, TA = 25°C

1000 UNITS

MISMATCH (DEG)

UNITS (%)

6603 G04

–2.5 2.5–2 –1.5 –1 –0.5 0 0.5 1 1.5 2

VS = 3V, BW = 156.25kHz

f = 125kHz, TA = 25°C

1000 UNITS

FREQUENCY (Hz)

GAIN (dB)

6603 G05

–60

–40

–50

–30

–20

–10

–70

GROUP DELAY (ns)

800

720

680

760

440

520

480

560

600

640

400

10k 1M 10M100k

RBIAS = 30.9k, VS = 3V

LPF1 = 1, BW = 2.5MHz

TA = 25°C

GAIN = 24dB

GAIN = 12dB

GAIN = 6dB

GAIN = 0dB

GROUP DELAY

LTC6603

6603fa

TYPICAL PERFORMANCE CHARACTERISTICS

Gain and Group Delay

vs Frequency Distortion vs Input Frequency

Distortion vs Input Frequency

Gain and Group Delay

vs Frequency

Distortion vs Input Frequency Distortion vs Input Frequency

Distortion vs Output Voltage

Filter Cutoff Accuracy

vs Supply Voltage

Filter Cutoff Accuracy

vs Temperature

FREQUENCY (Hz)

GAIN (dB)

6603 G06

–60

–40

–50

–30

–20

–10

–70

GROUP DELAY (ns)

3.5

3.1

2.9

3.3

1.7

2.1

1.9

2.3

2.5

2.7

1.5

10k 1M 10M100k

RBIAS = 30.9k, VS = 3V

LPF1 = 0, LPF0 = 1,

BW = 625kHz

TA = 25°C

GAIN = 24dB

GAIN = 0dB

GROUP DELAY

GAIN = 6dB

GAIN = 12dB

FREQUENCY (Hz)

GAIN (dB)

6603 G07

–60

–40

–50

–30

–20

–10

–70

GROUP DELAY (µs)

12.0

11.0

10.5

11.5

7.5

8.5

8.0

9.0

9.5

10.0

7.0

1k 100k 1M10k

RBIAS = 30.9k, VS = 3V

LPF1 = LPF0 = 0,

BW = 156.25kHz

TA = 25°C

GAIN = 24dB

GAIN = 0dB

GROUP DELAY

GAIN = 6dB

GAIN = 12dB

INPUT FREQUENCY (kHz)

100

DISTORTION (dBc)

–50

–60

–80

–70

–90 900 1700500 1300

6603 G08

RBIAS = 30.9k, VS = 3V

LPF1 = 1, BW = 2.5MHz

VOUT = 2VP-P, TA = 25°C

HD2, GAIN = 24dB

HD3, GAIN = 24dB

HD3, GAIN = 0dB

HD2, GAIN = 0dB

INPUT FREQUENCY (kHz)

100

DISTORTION (dBc)

–60

–65

–80

–85

–70

–75

–90 900500

6603 G09

700300 1100

RBIAS = 54.9k, VS = 3V

LPF1 = 1, BW = 1.41MHz

TA = 25°C

HD2, GAIN = 24dB

HD3, GAIN = 24dB

HD3, GAIN = 0dB

HD2, GAIN = 0dB

INPUT FREQUENCY (kHz)

DISTORTION (dBc)

–60

–65

–80

–85

–70

–75

–90 420220

6603 G10

320120 520

RBIAS = 30.9k, VS = 3V

LPF1 = 0, LPF0 = 1, BW = 625kHz

VOUT = 2VP-P, TA = 25°C

HD2, GAIN = 24dB

HD3, GAIN = 0dB

HD2, GAIN = 0dB

HD3, GAIN = 24dB

INPUT FREQUENCY (kHz)

DISTORTION (dBc)

–70

–75

–90

–95

–80

–85

–100 9050

6603 G11

7030 110 130 150

RBIAS = 30.9k, VS = 3V

LPF1 = LPF0 = 0, BW = 156.25kHz

VOUT = 2VP-P, TA = 25°C

HD2, GAIN = 24dB

HD3, GAIN = 0dB

HD2, GAIN = 0dB

HD3, GAIN = 24dB

OUTPUT VOLTAGE (VP-P)

1.0

DISTORTION (dBc)

–60

–70

–90

–80

–100 1.81.4

6603 G11

1.61.2 2.0 2.2 2.4 2.6 2.8 3.0

RBIAS = 30.9k, VS = 3V, LPF1 = 0, LPF0 = 1,

BW = 2.5MHz, GAIN = 24dB, TA = 25°C

HD2, f = 1MHz

HD2, f = 200kHz

HD3, f = 1MHz

HD3, f = 200kHz

SUPPLY VOLTAGE (V)

2.7

FILTER CUTOFF FREQUENCY DEVIATION (%)

0.2

–0.6

–0.4

–0.5

–0.3

–0.2

–0.1

0.0

0.1

–0.8

–0.7

–0.9 3.12.9

6603 G13

3.02.8 3.2 3.3 3.4 3.5 3.6

RBIAS = 30.9k

TA = 25°C

LPF1 = LPF0 = 0, BW = 156.25kHz

LPF1 = 0, LPF0 = 1,

BW = 625kHz

LPF1 = 1, BW = 2.5MHz

TEMPERATURE (°C)

–50

FILTER CUTOFF FREQUENCY DEVIATION (%)

1.0

–0.6

–0.2

–0.4

0.0

0.2

0.4

0.6

0.8

–0.8 30–10

6603 G14

10–30 50 70 90

VS = 3V

RBIAS = 30.9k

BW = 2.5MHz

BW = 156.25kHz

BW = 625kHz

LTC6603

6603fa

TYPICAL PERFORMANCE CHARACTERISTICS

Common Mode Rejection Common Mode Rejection

OIP3 vs Average Signal

Frequency

OIP3 vs Average Signal

Frequency

OIP3 vs Average Signal

Frequency

Common Mode Rejection Ratio Common Mode Rejection Ratio

Common Mode Rejection

FREQUENCY (Hz)

CMRR (dB)

6603 G16

110

100

10k 1M 10M100k

VS = 3V, RBIAS = 30.9k

LPF1 = 0, LPF0 = 1,

BW = 625kHz, TA = 25°C

GAIN = 0dB

GAIN = 24dB

GAIN = 12dB

GAIN = 6dB

FREQUENCY (Hz)

CMRR (dB)

6603 G17

120

110

100

301k 100k 1M10k

VS = 3V, RBIAS = 30.9k

LPF1 = LPF0 = 0, BW = 156.25kHz,

TA = 25°C

GAIN = 0dB

GAIN = 24dB GAIN = 12dB

GAIN = 6dB

FREQUENCY (Hz)

COMMON MODE REJECTION (dB)

6603 G18

100

10k 1M 10M100k

VS = 3V, RBIAS = 30.9k

LPF1 = 1, BW = 2.5MHz,

TA = 25°C

GAIN = 0dB

GAIN = 24dB

CMR = ΔVIN-CM/ΔVOUT-DIFF

GAIN = 12dB

GAIN = 6dB

FREQUENCY (Hz)

COMMON MODE REJECTION (dB)

6603 G19

110

100

10k 1M 10M100k

VS = 3V, RBIAS = 30.9k

LPF1 = 0, LPF1 = 1, BW = 625kHz,

TA = 25°C

GAIN = 0dB

GAIN = 24dB

CMR = ΔVIN-CM/ΔVOUT-DIFF

GAIN = 12dB

GAIN = 6dB

FREQUENCY (Hz)

COMMON MODE REJECTION (dB)

6603 G20

100

501k 100k 1M10k

CMR = ΔVIN-CM/ΔVOUT-DIFF

VS = 3V, RBIAS = 30.9k

LPF1 = LPF0 = 0, BW = 156.25kHz,

TA = 25°C

GAIN = 0dB

GAIN = 24dB

GAIN = 12dB

GAIN = 6dB

AVERAGE FREQUENCY OF TWO TONES (kHz)

OIP3 (dBm)

6603 G21

100 2500500 900 1300 1700 2100

VS = 3V, RBIAS = 30.9k, TA = 25°C

LPF1 = 0, LPF0 = 1, BW = 625kHz

VOUT = 6dBm PER TONE FOR 2-TONE TEST

Δf = 10kHz

GAIN = 0dB

GAIN = 24dB

GAIN = 12dB

GAIN = 6dB

AVERAGE FREQUENCY OF TWO TONES (kHz)

OIP3 (dBm)

6603 G22

36 0 500 600100 200 300 400

VS = 3V, RBIAS = 30.9k, TA = 25°C

LPF1 = 0, LPF0 = 1, BW = 625kHz

VOUT = 6dBm PER TONE FOR 2-TONE TEST

Δf = 10kHz

GAIN = 0dB

GAIN = 24dB

GAIN = 12dB

GAIN = 6dB

AVERAGE FREQUENCY OF TWO TONES (kHz)

OIP3 (dBm)

6603 G23

3520 140 1606040 80 100 120

VS = 3V, RBIAS = 30.9k, TA = 25°C

LPF1 = 0, LPF0 = 1, BW = 156.25kHz

VOUT = 6dBm PER TONE FOR 2-TONE TEST

Δf = 10kHz

GAIN = 0dB

GAIN = 24dB

GAIN = 12dB

GAIN = 6dB

Common Mode Rejection Ratio

FREQUENCY (Hz)

CMRR (dB)

6603 G15

100

10k 1M 10M100k

VS = 3V, RBIAS = 30.9k

LPF1 = 1, BW = 2.5MHz

TA = 25°C

GAIN = 0dB

GAIN = 6dB

GAIN = 24dB

GAIN = 12dB

LTC6603

6603fa

TYPICAL PERFORMANCE CHARACTERISTICS

Clock Output Operating at 80MHz RBIAS Pin Voltage vs IRBIAS

Input Referred Noise Density Input Referred Noise Density Input Referred Noise Density

Output Impedance vs Frequency Supply Current vs Supply Voltage

Supply Current vs Temperature

OIP3 vs Temperature

TEMPERATURE (°C)

OIP3 (dBm)

6603 G23

–50 70 90–10–30 10 30 50

VS = 3V, RBIAS = 30.9k

PASSBAND GAIN = 24dB

VOUT = 6dBm PER TONE FOR 2-TONE TEST

Δf = 10kHz

BW = 625kHz,

FREQUENCY = 200kHz

BW = 156.25kHz,

FREQUENCY = 60kHz

BW = 2.5MHz, FREQUENCY = 1MHz

FREQUENCY (Hz)

OUTPUT IMPEDANCE (Ω)

6603 G25

0.1

0.01

0.0011k 1M 10M100k10k

LPF1 = 0, LPF0 = 1,

BW = 625kHz

LPF1 = 1, BW = 2.5MHz

LPF1 = LPF0 = 0,

BW = 156.25kHz

VS = 3V, RBIAS = 30.9k, TA = 25°C

SUPPLY VOLTAGE (V)

2.7

SUPPLY CURRENT (mA)

200

100

120

140

160

180

60 3.1 3.2 3.32.9

6603 G26

3.02.8 3.4 3.5 3.6

TA = 25°C

RBIAS = 30.9k

BW = 2.5MHz

BW = 156.25kHz

BW = 625kHz

TEMPERATURE (°C)

–50

SUPPLY CURRENT (mA)

180

100

120

140

160

60 30 50 70–10

6603 G27

10–30 90

TA = 25°C

RBIAS = 30.9k

BW = 2.5MHz

BW = 156.25kHz

BW = 625kHz

TIME (ns)

–14

VOLTAGE (V)

–2

–1

–6 –4 –2 0–10

6603 G28

–8–12 2

RBIAS = 30.9k, VS = 3V

TA = 25°C

IRBIAS (µA)

RBIAS PIN VOLTAGE (V)

1.25

1.15

1.20

1.10 10 15 205

6603 G29

TA = 25°C

VS = 3V

FREQUENCY (Hz)

VOLTAGE NOISE DENSITY (nV/√Hz)

6603 G30

1000

100

0.1

10k 1M 10M100k

VS = 3V, RBIAS = 30.9k

LPF1 = 1, BW = 2.5MHz

TA = 25°C

GAIN = 0dB

GAIN = 6dB

GAIN = 12dB

GAIN = 24dB

FREQUENCY (Hz)

VOLTAGE NOISE DENSITY (nV/√Hz)

6603 G31

1000

100

10k 1M 10M100k

VS = 3V, RBIAS = 30.9k

LPF1 = 0, LPF0 = 1,

BW = 625kHz

TA = 25°C

GAIN = 0dB

GAIN = 6dB

GAIN = 12dB

GAIN = 24dB

FREQUENCY (Hz)

VOLTAGE NOISE DENSITY (nV/√Hz)

6603 G32

1000

100

11k 100k 1M10k

VS = 3V, RBIAS = 30.9k

LPF1 = 0, LPF0 = 0,

BW = 156.25kHz

TA = 25°C

GAIN = 0dB

GAIN = 6dB

GAIN = 12dB

GAIN = 24dB

LTC6603

6603fa

V+IN (Pin 1): Input Voltage Supply (2.7V ≤ V ≤ 5.5V). This

supply must be kept free from noise and ripple. It should

be bypassed directly to a ground plane with a 0.1µF ca-

pacitor unless it is tied to V+A (Pin 2). The bypass should

be as close as possible to the IC, but is not as critical as

the bypassing of V+A and V+D (Pin16).

V+A (Pin 2): Analog Voltage Supply (2.7V ≤ V ≤ 3.6V). This

supply must be kept free from noise and ripple. It should be

bypassed directly to a ground plane with a 0.1µF capacitor.

The bypass should be as close as possible to the IC.

VOCM (Pin 3): Output Common Mode Voltage Reference.

If ﬂ oated, an internal resistive divider sets the voltage

on this pin to half the supply voltage (typically 1.5V),

maximizing the dynamic range of the ﬁ lter. If this pin is

ﬂ oated, it must be bypassed with a quality 1µF capacitor

to ground. This pin has a typical input impedance of 3.4k

and may be overdriven. Driving this pin to a voltage other

than the default value will reduce the signal range the ﬁ lter

can handle before clipping.

RBIAS (Pin 4): Oscillator Frequency-Setting Resistor Input.

The value of the resistor connected between this pin and

ground determines the frequency of the master oscillator,

and sets the bias currents for the ﬁ lter networks. The voltage

on this pin is held by the LTC6603 to approximately 1.17V.

For best performance, use a precision metal ﬁ lm resis-

tor with a value between 30.9k and 200k and limit the

capacitance on this pin to less than 10pF. This resistor is

necessary even if an external clock is used.

CLKCNTL (Pin 5): Clock Control Input. This three-state

input selects the function of CLKIO (Pin 15). Tying the

CLKCNTL pin to ground allows the CLKIO pin to be driven

by an external clock (CLKIO is the master clock input).

If the CLKCNTL pin is ﬂ oated, the internal oscillator is

enabled, but the master clock is not present at the CLKIO

pin (CLKIO is a no-connect). If the CLKCNTL pin is tied

to V+D (Pin 16), the internal oscillator is enabled and the

master clock is present at the CLKIO pin (CLKIO is the

master clock output). To detect a ﬂ oating CLKCNTL pin,

the LTC6603 attempts to pull the pin toward mid-supply.

This is realized with two internal 15µA current sources, one

tied to V+D and CLKCNTL and the other one tied to ground

and CLKCNTL. Therefore, driving the CLKCNTL pin high

requires sourcing approximately 15µA. Likewise, driving

the CLKCNTL pin low requires sinking 15µA. When the

CLKCNTL pin is ﬂ oated, it should be bypassed by a 1nF

capacitor to ground or be surrounded by a ground shield

to prevent excessive coupling from other PCB traces.

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Input Referred Noise Integral Input Referred Noise

PIN FUNCTIONS

INTEGRATION BW (Hz)

VOLTAGE NOISE (µV)

6603 G34

1000

100

10k 1M 10M100k

VS = 3V, RBIAS = 30.9k

LPF1 = 0, LPF0 = 1, BW = 625kHz

TA = 25°C GAIN = 0dB

GAIN = 6dB

GAIN = 12dB

GAIN = 24dB

INTEGRATION BW (Hz)

VOLTAGE NOISE (µV)

6603 G35

1000

100

10k 100k 1M

VS = 3V, RBIAS = 30.9k

LPF1 = LPF0 = 0, BW = 156.25kHz

TA = 25°C

GAIN = 24dB

GAIN = 12dB

GAIN = 0dB

GAIN = 6dB

Integral Input Referred Noise

INTEGRATION BW (Hz)

VOLTAGE NOISE (µV)

6603 G33

1000

100

10k 1M 10M100k

VS = 3V, RBIAS = 30.9k

LPF1 = 1,BW = 2.5MHz

TA = 25°C

GAIN = 0dB

GAIN = 6dB

GAIN = 12dB

GAIN = 24dB

LTC6603

6603fa

PIN FUNCTIONS

LPF1(CS) (Pin 6): TTL Level Input. When in pin program-

mable control mode, this pin is the MSB of the lowpass

cutoff frequency control code; in serial control mode, this

pin is the chip select input (active low).

+INB, –INB (Pins 7, 8): Channel B Differential Inputs.

The input range and input resistance are described in the

Applications Information section. Input voltages which

exceed V+IN (Pin 1) should be avoided.

LPF0 (SCLK) (Pin 9): TTL Level Input. When in pin pro-

grammable control mode, this pin is the LSB of the lowpass

cutoff frequency control code; in serial control mode, this

pin is the clock of the serial interface.

SDI (Pin 10): TTL Level Input. When in pin programmable

control mode, this pin is left ﬂ oating; in serial control

mode, this pin is the serial data input.

SDO (Pin 11): TTL Level Input. When in pin programmable

control mode, this pin is left ﬂ oating; in serial control

mode, this pin is the serial data output.

–OUTB, +OUTB (Pins 12, 13): Channel B Differential Filter

Outputs. These pins can drive 1k and/or 50pF loads. For

larger capacitive loads, an external 100 series resistor

is recommended for each output. The common mode

voltage of the ﬁ lter outputs is the same as the voltage at

VOCM (Pin 3).

GND (Pin 14): Ground. Should be tied to a ground plane

for best performance.

CLKIO (Pin 15): When CLKCNTL (Pin 5) is tied to ground,

CLKIO is the master clock input. When CLKCNTL is ﬂ oated,

CLKIO is pulled to ground by a weak pulldown. When

CLKCNTL is tied to V+D (Pin 16), CLKIO is the master

clock output. When conﬁ gured as a clock output, this pin

can drive 1k and/or 5pF loads (heavier loads will cause

inaccuracies).

V+D (Pin 16): Digital Voltage Supply (2.7V ≤ V ≤ 3.6V).

This supply must be kept free from noise and ripple. It

should be bypassed directly to a ground plane with a 0.1µF

capacitor. The bypass should be as close as possible to

the IC.

SER (Pin 17): Interface Selection Input. When tied to V+D

(Pin 16) or ﬂ oated, the interface is in pin programmable

control mode, i.e. the ﬁ lter gain and cutoff frequencies

are programmed by the GAIN1, GAIN0, LPF1 and LPF0

pins. When SER is tied to ground, the ﬁ lter gain, the ﬁ lter

cutoff frequency and shutdown mode are programmed

by the serial interface.

–OUTA, +OUTA (Pins 18, 19): Channel A Differential Filter

Outputs. These pins can drive 1k and/or 50pF loads. For

larger capacitive loads, an external 100 series resistor

is recommended for each output. The common mode

voltage of the ﬁ lter outputs is the same as the voltage at

VOCM (Pin 3).

CAP (Pin 20): Connect a 0.1µF bypass capacitor to this

pin. Pin 20 is a buffered version of Pin 3.

GAIN0(D0) (Pin 21): TTL Level Input. When in pin pro-

grammable control mode, this pin is the LSB of the gain

control code; in serial control mode, this pin is the LSB

of the serial control register, an output.

GAIN1 (Pin 22): TTL Level Input. When in pin programmable

control mode, this pin is the MSB of the gain control code;

in serial control mode, this pin is a no-connect.

–INA, +INA (Pins 23, 24): Channel A Differential Inputs.

The input range and input resistance are described in the

Applications Information section. Input voltages which

exceed V+IN (Pin 1) should be avoided.

Exposed Pad (Pin 25): Ground. The Exposed Pad must

be soldered to PCB.

LTC6603

6603fa

BLOCK DIAGRAM

Timing Diagram of the Serial Interface

V+A

GND

V+A

V+IN

RBIAS 4

VOCM 3

CLKCNTL

LPF1(CS)

6603 BD

20 19

22 21

2324

11 12

9 10

–INB

+INB SDI

LPF0(SCLK) SDO –OUTB

–INA

+INA GAIN0(D0)

GAIN1 CAP +OUTA

SER

–OUTA

CLKIO

V+D

GND

+OUTB

GAIN LPF

CONTROL BIAS CLK

CONTROLBIAS CLK

BIAS/OSC CLOCK

GENERATOR

CONTROL

LOGIC

CHANNEL A

CHANNEL B

TO PIN 20

D3D3 D2 D1 D0 D7 • • • • D4

D3D3D4 D2 D1 D0 D7 • • • • D4

PREVIOUS BYTE CURRENT BYTE

SCLK

SDI

SDO

6603 TD

TIMING DIAGRAM

LTC6603

6603fa

APPLICATIONS INFORMATION

Theory of Operation (Refer to Block Diagram)

The LTC6603 features two matched ﬁ lter channels, each

containing gain control and lowpass ﬁ lter networks that

are controlled by a single control block and clocked by

a single clock generator. The gain and cutoff frequency

can be separately programmed. The two channels are

not independent, i.e. if the gain is set to 24dB then both

channels have a gain of 24dB. The ﬁ lter can be clocked

with an external clock source, or using the internal oscil-

lator. A resistor connected to the RBIAS pin sets the bias

currents for the ﬁ lter networks and the internal oscillator

frequency (unless driven by an external clock). Altering the

clock frequency changes the ﬁ lter bandwidth. This allows

the ﬁ lters to be “tuned” to many different bandwidths.

Pin Programmable Interface

As shown in Figure 1, connecting SER to V+D allows the

ﬁ lter to be directly controlled through the pin program-

mable control lines GAIN1, GAIN0, LPF1 and LPF0. The

GAIN0(D0) pin is bidirectional (input in pin programmable

control mode, output in serial mode). In pin programmable

control mode, the voltage at GAIN0(D0) cannot exceed V+D;

otherwise, large currents can be injected to V+D through the

parasitic diodes (see Figure 2). Connecting a 10k resistor

at the GAIN0(D0) pin (see Figure 1) is recommended for

current limiting, to less than 10mA. SER has an internal

Figure 1. Filter in Pin Programmable Control Mode

pull-up to V+D. None of the logic inputs have an internal

pull-up or pull-down.

Serial Interface

Connecting SER to ground allows the ﬁ lter to be controlled

through the SPI serial interface. When CS is low, the serial

data on SDI is shifted into an 8-bit shift register on the

rising edge of the clock (SCLK), with the MSB transferred

ﬁ rst (see Figure 3). Serial data on SDO is shifted out on

the clock’s falling edge. A high CS will load the 8 bits of

the shift register into an 8-bit D-latch, which is the serial

control register. The clock is disabled internally when

CS is pulled high. Note: SCLK must be low before CS is

pulled low to avoid an extra internal clock pulse. SDO is

always active in serial mode (never tri-stated) and cannot

be “wire-ORed” to other SPI outputs. In addition, SDO is

not forced to zero when CS is pulled high.

An LTC6603 may be daisy-chained with other LTC6603s

or other devices having serial interfaces. Daisy chain-

ing is accomplished by connecting the SDO of the lead

chip to the SDI of the next chip, while SCLK and CS

remain common to all chips in the daisy chain. The se-

rial data is clocked to all the chips then the CS signal

is pulled high to update all of them simultaneously.

Figure 4 shows an example of two LTC6603s in a daisy-

chained SPI conﬁ guration.

V+IN

V+A

V+D

+INA

–INA

SER

LPF1(CS)

LPF0(SCLK)

GAIN1

GAIN0(D0)

GND

LTC6603

VOUT

VIN

0.1µF

LOWPASS CUTOFF = 2.5MHz (fCLK = 80MHz)

GAIN = 4

GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR.

10k RESISTORS ON GAIN0(OUT) PROTECTS THE

DEVICE WHEN VGAIN0 > V+D

µP

–

10k

6603 F01

+OUTA

–OUTA

V+IN

V+A

V+D

+INA

–INA

SER

LPF1(CS)

LPF0(SCLK)

GAIN1

GAIN0(D0)

GND

VOUT

VIN

+OUTA

–OUTA

3.3V

0.1µF

3.3V

LTC6603

LPF1

LPF0

GAIN1

GAIN0

LTC6603

6603fa

APPLICATIONS INFORMATION

Figure 2. Bidirectional Design of GAIN0(OUT) Pin Figure 3. Diagram of Serial Interface (MSB First Out)

Figure 4. Two Devices in a Daisy Chain

V+D

GAIN0(D0)

6603 F02

(INTERNAL

NODE)

4-BIT GAIN, BW

CONTROL CODE

FUNCTION

8-BIT LATCH

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

8-BIT

SHIFT-REGISTER

SDO

SCLK

SDI

6603 F03

OUT

SHUTDOWN

µP

6603 F04

CSX

SCLK

SDI

SCLK

SDI

D15 D11 D10 D9 D8 D7 D3 D2 D1 D0

GAIN, BW CONTROL WORD FOR #2 GAIN, BW CONTROL WORD FOR #1 SHUTDOWN FOR #1SHUTDOWN FOR #2

V+IN

V+A

V+D

+INA

–INA

SER

LPF1(CS)

LPF0(SCLK)

SDI

GND

LTC6603

VOUT1

VIN1

0.1µF

–

VIN2

3.3V

+OUTA

–OUTA

OUT1

V+IN

V+A

V+D

+INA

–INA

SER

LPF1(CS)

LPF0(SCLK)

SDI

GND

LTC6603

VOUT2

0.1µF

3.3V

+OUTA

–OUTA

OUT2

GAIN0(D0)

SDO

GAIN0(D0)

SDO SDO

Serial Control Register Deﬁ nition

D7 D6 D5 D4 D3 D2 D1 D0

GAIN0 GAIN1 LPF0 LPF1 NO FUNCTION NO FUNCTION SHDN OUT

LTC6603

6603fa

APPLICATIONS INFORMATION

GAIN1 and GAIN0 are the gain control bits (register bits

D6 and D7 when in serial mode). Their function is shown

in Table 1. In serial mode, register bit D1 can be set to 1

to put the device into a low power shutdown mode. Reg-

ister bit D0 is a general purpose output (Pin 21) when in

serial mode.

Table 1. Gain Control

GAIN 1 GAIN 0

PASSBAND GAIN

(dB)

000

016

1012

1124

Self-Clocking Operation

The LTC6603 features a unique internal oscillator which sets

the ﬁ lter cutoff frequency using a single external resistor

connected to the RBIAS pin. The clock frequency is deter-

mined by the following simple formula (see Figure 5):

CLK = 247.2MHz • 10k/RBIAS

Note: RBIAS ≤ 200k

The design is optimized for V+A, V+D = 3V, fCLK = 45MHz,

where the ﬁ lter cutoff frequency error is typically <3%

when a 0.1% external 54.9k resistor is used (any resis-

tor (RBIAS) tolerance, will shift the clock frequency). With

different resistor values and cutoff frequency control set-

tings (LPF1 and LPF0), the lowpass cutoff frequency can

Figure 5. RBIAS vs Desired Clock Frequency

be accurately varied from 24.14kHz to 2.5MHz. Table 2

summarizes the cutoff frequencies that can be obtained

with an external resistor (RBIAS) value of 30.9k. Note that

the cutoff frequencies scale with the clock frequency. For

example, if LPF1 and LPF0 are both equal to zero, and

RBIAS is increased from 30.9k to 200k, fCLK will decrease

from 80MHz to 12.36MHz and the cutoff frequency will

be reduced from 156.25kHz to 24.14kHz. The cutoff

frequencies that can be obtained with external resistor

values of 54.9k and 200k are shown in Table 3 and Table 4,

respectively. When the LTC6603 is programmed for the

cutoff frequencies lower than the maximum, the power is

automatically reduced. The power savings at the middle

bandwidth setting (LPF1 = 0, LPF0 = 1), is about 23%,

while the power savings at the lowest bandwidth setting

(LPF1 = 0, LPF0 = 0) is about 60%.

Table 2. Cutoff Frequency Control, RBIAS = 30.9k, fCLK = 80MHz

LPF1 LPF0 LOWPASS BW(kHz)

0 0 156.25

0 1 625

1 0 2500

1 1 2500

Table 3. Cutoff Frequency Control, RBIAS = 54.9k, fCLK = 45MHz

LPF1 LPF0 LOWPASS BW(kHz)

0 0 87.94

0 1 351.78

1 0 1407

1 1 1407

Table 4. Cutoff Frequency Control, RBIAS = 200k, fCLK = 12.36MHz

LPF1 LPF0 LOWPASS BW(kHz)

0 0 24.14

0 1 96.56

1 0 386.25

1 1 386.25

DESIRED CLOCK FREQUENCY (MHz)

RBIAS (kΩ)

6603 F05

200

175

100

125

150

2510 8020 30 40 50 60 70

LTC6603

6603fa

APPLICATIONS INFORMATION

The following graphs show a few of the possible lowpass

ﬁ lters.

Gain and Group Delay vs Frequency

(2.5MHz Lowpass Response)

Gain and Group Delay vs Frequency

(650kHz Lowpass Response)

The oscillator is sensitive to transients on the positive

supply. The IC should be soldered to the PC board and

the PCB layout should include a 0.1µF ceramic capacitor

between V+A (Pin 2) and ground, as close as possible to

the IC to minimize inductance. The PCB layout should also

include an additional 0.1µF ceramic capacitor between

V+D (Pin 16) and ground. Avoid parasitic capacitance on

RBIAS (Pin 4) and avoid routing noisy signals near RBIAS.

Use a ground plane connected to Pin 14 and the Exposed

Pad (Pin 25).

FREQUENCY (Hz)

GAIN (dB)

GROUP DELAY (µs)

6603 G17

–20

–100

–80

–60

–40

–120

1.2

1.0

0.2

0.4

0.6

0.8

100k 10M1M

GAIN

GROUP DELAY

FREQUENCY (Hz)

GAIN (dB)

GROUP DELAY (µs)

6603 G18

–60

–40

–20

–80

100k 1M

GAIN

GROUP DELAY

Alternative Methods of Setting the Clock Frequency of

the LTC6603

The oscillator may be programmed by any method that

sinks a current out of the RBIAS pin. The circuit in Figure 6

sets the clock frequency by using a programmable current

source and in the expression for fCLK, the resistor RBIAS

is replaced by the ratio of 1.17V/ICONTROL. Because the

voltage of the RBIAS pin is approximately 1.17V ±5%, the

Figure 6 circuit is less accurate than if a resistor controls

the clock frequency.

In this circuit, the LTC2621 (a 12-bit DAC) is daisy-chained

with the LTC6603. Because the sinking current from the

RBIAS pin is:

RBIAS •k

2N•R1

the equivalent RBIAS is:

2N•R1

where k is the binary DAC input code and N is the resolu-

tion. Figure 7 shows some of the frequency responses

that can be obtained using this circuit.

Figure 8 shows the LTC6603’s oscillator conﬁ gured as

a VCO. A voltage source is connected in series with the

RBIAS resistor. The clock frequency, fCLK, will vary with

VCONTROL. Again, this circuit decouples the relationship

between the current out of the RBIAS pin and the voltage

of the RBIAS pin; the frequency accuracy will be degraded.

The clock frequency, however, will increase monotonically

with decreasing VCONTROL.

Operation Using an External Clock

The LTC6603 may be clocked by an external oscillator

for tighter bandwidth control by pulling CLKCNTL (Pin 5)

to ground and driving a clock into CLKIO (Pin 15). If an

external clock is used, the RBIAS resistor is still necessary.

The value of RBIAS must be no larger than the value that

would be required for using the internal oscillator. For

example, a 100k resistor would program the internal oscil-

lator for 24.705MHz, so an external oscillator frequency of

24.705MHz would require an RBIAS resistance of no more

LTC6603

6603fa

APPLICATIONS INFORMATION

Figure 6. Current Controlled Clock Frequency

Figure 8. Voltage Controlled Clock Frequency

6603 F06

V+IN

V+A

VOCM

RBIAS

CLKCNTL

LPF1(CS)

+INB

–INB

LPF0(SCLK)

SDI

SDO

–OUTB

+INA

–INA

GAIN1

GAIN0(D0)

VOCM CAP

+OUTA

–OUTA

SER

V+D

CLK IO

GND

+OUTB

LTC6603

100nF

2.2µF C4

100nF

2.2µF

C19

50pF

C18

50pF

C15

10nF

+OUTA

–OUTA

+OUTB

–OUTB

R23

50k

R24

50k

–INB +INB

R25

50k

R26

50k

+INA –INA

C17

50pF

C16

50pF

–IN

+IN

7OUT

–IN

+IN OUT

30.5k

100nF

V+

V–

SDO

SDI

SCK

CLR

CS/LD

LDAC

100nF

100k

1µF

VOUT

VREF VCC

GND

LTC2621-1

SDI

SCLK

5V 3V

I RANGE = 6µA TO 38.4µA

USE NARROW SHORT

TRACES FOR MINIMUM

CAPACITANCE.

RK7002AT116CT

LTC6078

CLR LOW WILL SET DAC TO MID-SCALE (WITH A LTC6603-1 VERSION).

HAS ~100ms TC AT START-UP TO RESET TO ZERO-SCALE.

DATA FORMAT

DATA IS SHIFTED FROM MOSI (MASTER OUT, SLAVE IN) THRU LTC6603 INTO THE LTC2621.

THE TOTAL PACKET IS 32 BITS. IT STARTS WITH A CONTROL BYTE (0011 XXXX) THEN MSB OF THE DAC,

WITH DUMMY BITS AT THE END, 16 BITS (24 BITS TOTAL). THEN 8 BITS TO THE FILTER.

D6 AND D7 = GAIN, D4 AND D5 = LPF, D1 = SHDN. D0 = GEN. PURPOSE OUTPUT.

SPI INTERFACE

VOCM

V+

V–

V+

V+IN

RBIAS

6603 F08

VCONTROL

fCLK = 247.2MHz • (10k/RBIAS) • (1 – VCONTROL/1.17V)

RBIAS

–

FREQUENCY (Hz)

GAIN (dB)

6603 F07

–10

–20

–30

–40

–50

–60

–70

–801k 1M 10M100k10k

VS = 3V

TA = 25°C

Figure 7. Frequency Response Controlled by LTC2621-1

LTC6603

6603fa

APPLICATIONS INFORMATION

than 100k. If the value of RBIAS is too large, the ﬁ lters will

not receive a large enough bias current, possibly causing

errors due to insufﬁ cient settling. Be sure to obey the

absolute maximum speciﬁ cations when driving a clock

into CLKIO (Pin 15).

Input Common Mode and Differential Voltage Range

The input signal range extends from zero to the V+IN

supply voltage. This input supply can be tied to V+A and

V+D, or driven up to 5.5V for increased input signal range.

Figure 9 shows the distortion of the ﬁ lter versus common

mode input voltage with a 2VP-P differential input signal

(V+IN = 5V).

control bits LPF1 and LPF0. The differential input imped-

ance is a function of the clock frequency and the control

bits LPF1, LPF0, GAIN1 and GAIN0. Table 5 shows the

typical input impedances for a clock frequency of 80MHz.

These input impedances are all proportional to 1/fCLK, so

if the clock frequency were reduced by half to 40MHz,

the impedances would be doubled. The typical variation

in dynamic input impedance for a given clock frequency

is –20% to +35%.

Table 5. Differential, Common Mode Input Impedances,

fCLK = 80MHz

GAIN1 GAIN0 LPF1 LPF0

DIFFERENTIAL

INPUT IMPEDANCE

(k)

COMMON MODE

INPUT IMPEDANCE

(k)

0000 38 40

0001 16 20

0010 2.5 5

0011 2.5 5

0100 20 40

0101 9.5 20

0 1 1 0 2.5 5

0 1 1 1 2.5 5

1 0 0 0 10 40

1 0 0 1 5.4 20

1010 1.9 5

1011 1.9 5

1 1 0 0 5.2 40

1 1 0 1 2.8 20

1110 1.6 5

1111 1.6 5

Output Common Mode and Differential Voltage Range

The output voltage is a fully differential signal with a

common mode level equal to the voltage at VOCM. Any of

the ﬁ lter outputs may be used as single-ended outputs,

although this will degrade the performance. The output

voltage range is typically 0.5V to V+A – 0.5V (V+A = 2.7V

to 3.6V).

The common mode output voltage can be adjusted by

overdriving the voltage present on VOCM. To maximize

the undistorted peak-to-peak signal swing of the ﬁ lter,

the VOCM voltage should be set to V+A/2. Note that the

output common mode voltages of the two channels are

Figure 9. Distortion vs Common Mode Input Voltage (5V)

COMMON MODE INPUT VOLTAGE (V)

1.0

DISTORTION (dBc)

–60

–70

–80

–90 3.02.0 4.0

6603 F09

5.02.5 4.51.5 3.5

RBIAS = 30.9k, VS = 3V, V+IN = 5.5V

LPF1 = 1, BW = 2.5MHz, GAIN = 24dB

VOUT = VP-P, TA = 25°C

HD3, f = 1MHz

HD3, f = 200kHz

For best performance, the inputs should be driven dif-

ferentially. For single-ended signals, connect the unused

input to VOCM (Pin 3) or to a quiet DC reference voltage.

To achieve the best distortion performance, the input

signal should be centered around the DC voltage of the

unused input.

Refer to the Typical Performance Characteristics section

to estimate the distortion for a given input level.

Dynamic Input Impedance

The unique input sampling structure of the LTC6603

has a dynamic input impedance which depends on the

conﬁ guration and the clock frequency. This dynamic

input impedance has both a differential component and

a common mode component. The common mode input

impedance is a function of the clock frequency and the

LTC6603

6603fa

APPLICATIONS INFORMATION

not independent as they are both set by the VOCM pin.

Figure 10 illustrates the distortion versus output common

mode voltage for a 2VP-P differential input voltage and a

common mode input voltage that is equal to mid-supply.

Figure 10. Distortion vs Common Mode Output Voltage

Connecting resistors between each input and V+IN will

pull the input common mode voltage up, increasing the

input signal swing. The resistance, RPULL-UP, necessary to

set the input common mode voltage, VICM, to any desired

level can be calculated by

RPULL UP =RCM

VSUPPLY

ICM

1











where

CM = 40k•80MHz/fCLK for LPF1=0, LPF0=0

CM = 20k•80MHz/fCLK for LPF1=0, LPF0=1

CM = 5k•80MHz/fCLK for LPF1=1

For example, if the lowpass cutoff frequency is set to

2.5MHz, 5k resistors connected between each input and

V+IN will set the input common mode voltage to mid-

supply.

Circuit A of Figure 12 is for a ﬁ xed CLK and LPF0, LPF1

setting. If the clock varies or the LPF0, LPF1 setting changes

then Circuit B of Figure 12 should be used.

Due to the sampled data nature of the ﬁ lter, an anti-aliasing

ﬁ lter at the inputs is recommended.

The output common mode voltage is equal to the voltage

of the VOCM pin. The VOCM pin is biased to one-half of

the supply voltage by an internal resistive divider (see

Block Diagram). To alter the common mode output volt-

age, VOCM can be driven with an external voltage source

or resistor network. If external resistors are used, it is

important to note that the internal 2k resistors can vary

±30% (their ratio varies only ±1%). The ﬁ lter outputs can

also be AC-coupled.

The LTC6603 can be interfaced to an A/D converter by pull-

ing CLKCNTL (Pin 5) to V+D. This conﬁ gures CLKIO (Pin 15)

as a clock output, which can be used to drive the clock

input of the A/D converter. This allows the A/D converter

to be synchronized with the ﬁ lter sampling clock, avoiding

“beat frequencies” and simplifying the board layout. Any

routing attached to the CLKIO pin should be as short as

possible, in order to minimize reﬂ ections.

Similarly, the LTC6603 can be interfaced to another LTC6603

in a master/slave conﬁ guration as shown in Figure 13. This

COMMON MODE OUTPUT VOLTAGE (V)

0.8

DISTORTION (dBc)

–60

–70

–65

–75

–80 1.0 1.4

6603 F10

1.81.61.2

RBIAS = 30.9k, VS = 3V,

GAIN = 24dB, TA = 25°C

SIGNAL FREQUENCY = 200kHz

HD3, LPF1 = 0, LPF0 = 1

HD3, LPF1 = 1

HD2, LPF1 = 0,

LPF0 = 1

HD2, LPF1 = 1

Interfacing to the LTC6603

The input and output common mode voltages of the LTC6603

are independent. The input common mode voltage is set

by the signal source if DC-coupled, as shown in Figure 11.

If the inputs are AC-coupled, as shown in Figure 12

(Circuit A), the input common mode voltage will be pulled to

ground by an equivalent resistance of RCM, shown in Table 5.

This does not affect the ﬁ lter’s performance as long as

the input amplitude is less than 0.5VP-P. At low ﬁ lter gain

settings, a larger input voltage swing may be desired.

Figure 11. DC-Coupled Inputs

V+IN

V+A

V+D

+INA

–INA

VOCM

GND

LTC6603

0.1µF

DC-COUPLED INPUT

VIN (COMMON MODE) = (VIN+ + VIN–)/2

VOUT (COMMON MODE) = (VOUT+ + VOUT–)/2 = VSUPPLY/2

6603 F11

+OUTA

–OUTA

VSUPPLY

–+

–1µF

VOUT+

VOUT–

VIN+VIN–

LTC6603

6603fa

APPLICATIONS INFORMATION

Figure 12. AC-Coupled Inputs

Figure 13. Two Devices in a Master/Slave Clocking Conﬁ guration

AC-COUPLED INPUT

VIN (COMMON MODE) = VOUT (COMMON MODE) = VSUPPLY/2

6603 F12

VSUPPLY

–+

–0.1µF

0.1µF

RPULL-UP RPULL-UP

V+IN

V+A

V+D

+INA

–INA

VOCM

GND

LTC6603

VOUT+

VOUT–

0.1µF

+OUTA

–OUTA

VSUPPLY

1µF

VIN+VIN–

AC-COUPLED INPUT

VIN (COMMON MODE) =

VSUPPLY

–+

–0.1µF

0.1µF 1.87k

1.87k1.87k

1.87k V+IN

V+A

V+D

+INA

–INA

VOCM

GND

LTC6603

VOUT+

VOUT–

0.1µF

+OUTA

–OUTA

V+A

1µF

VIN+VIN–

CIRCUIT A

CIRCUIT B

0.1µF

V+IN

RCM •VIN

2•R

CM 1.87k

V+IN

V+A

V+D

+INA

–INA

CLKCNTL

CLKIO

GND

LTC6603

MASTER

VOUT1

VIN1

0.1µF

–

6603 F13

+OUTA

–OUTA

3.3V

LTC6603

SLAVE

VOUT2

VIN2

0.1µF

+OUTA

–OUTA

3.3V

V+IN

V+A

V+D

+INA

–INA

CLKCNTL

CLKIO

GND

LTC6603

6603fa

APPLICATIONS INFORMATION

results in four matched ﬁ lter channels, all synchronized to

the same clock. The master has its CLKCNTL pin pulled

to V+D, conﬁ guring its CLKIO pin as an output, while the

slave has its CLKCNTL pin pulled to ground, conﬁ guring its

CLKIO pin as an input. Note that in order to synchronize the

two ﬁ lters, the clock frequency must not be buffered. This

requires that the ﬁ lters be close together on the PC board.

If the clock is buffered, the ﬁ lters would have matching

bandwidths, but would not be synchronized.

Output Drive

The ﬁ lter outputs can drive 1k and/or 50pF loads connected

to AC ground with a 0.5V to 2.5V signal (corresponding

to a 4VP-P differential signal). For differential loads (loads

connected between +OUTA and –OUTA or +OUTB and

–OUTB) the outputs can produce a 4VP-P signal across 2k

and/or 25pF. For smaller signal amplitudes, the outputs can

drive correspondingly larger loads. For larger capacitive

loads, an external 50 series resistor is recommended

for each output.

Clock Feedthrough

Clock feedthrough is deﬁ ned as the RMS value of the clock

frequency and its harmonics that are present at the ﬁ lter’s

output. The clock feedthrough is measured with +INA and

–INA (or +INB, –INB) tied to VOCM and depends on the PC

board layout and the power supply decoupling. The clock

feedthrough can be reduced with a simple RC post ﬁ lter.

Decoupling Capacitors

The LTC6603 uses sampling techniques, therefore its

performance is sensitive to supply noise. 0.1µF ceramic

decoupling capacitors must be connected from V+A (Pin 2)

and V+D (Pin 16) to ground with leads as short as possible.

A ground plane should be used. Noisy signals should be

isolated from the ﬁ lter’s input pins. In addition, a 0.1µF

decoupling capacitor at Pin 20 is recommended since this

pin receives clocked current injection.

Aliasing

Aliasing is an inherent phenomenon of sampled data ﬁ lters.

Signiﬁ cant aliasing only occurs when the frequency of

the input signal approaches the sampling frequency or

multiples of the sampling frequency. The ratio of the

LTC6603 input sampling frequency to the clock frequency,

fCLK, is determined by the state of control bits LPF1 and

LPF0. Table 6 shows the possible input sampling frequen-

cies for a clock frequency of 80MHz. The input sampling

frequency is proportional to the clock frequency. For

example, if the clock frequency is lowered from 80MHz

to 40MHz, the input sampling frequency will be lowered

by half. Input signals with frequencies near the input

sampling frequency will be aliased to the passband of

the ﬁ lter and appear at the output unattenuated.

Table 6. Input Sampling Frequency (fCLK = 80MHz)

LPF1 LPF0 Input Sampling Frequency (MHz)

00 20

01 40

1 0 160

1 1 160

A simple LC anti-aliasing ﬁ lter is recommended at the

ﬁ lter inputs to attenuate frequencies near the input sam-

pling frequency that will be aliased to the passband. For

example, if the clock frequency is set to 80MHz and the

cutoff frequency of the ﬁ lter is set to its maximum (LPF1

= 1), the lowest frequency that would be aliased to the

passband would be fCLK – fCUTOFF, i.e., 160MHz – 2.5MHz

= 157.5MHz. The LTC6603 ﬁ lter inputs should be driven

by a low impedance output (<100).

Wideband Noise

The wideband noise of the ﬁ lter is the RMS value of the

device’s output noise spectral density. The wideband noise

is nearly independent of the value of the clock frequency

and excludes the clock feedthrough. Most of the wideband

noise is concentrated in the ﬁ lter passband and cannot be

removed with post ﬁ ltering.

Power Supply Current

The power supply current depends on the state of the

lowpass cutoff frequency controls (LPF1, LPF0) and the

value of RBIAS. When the LTC6603 is programmed for the

middle cutoff frequency (LPF1 = 0, LPF0 = 1), the supply

current is reduced by about 23% relative to the supply

current for the higher bandwidth setting. Programming

LTC6603

6603fa

APPLICATIONS INFORMATION

the LTC6603 for the lowest cutoff frequency (LPF1 = 0,

LFP0 = 0) reduces the supply current by about 60%. Power

supply current vs. cutoff frequency for various bandwidth

settings is shown in the Typical Performance Characteris-

ticst section. The LTC6603 can be programmed through

the serial interface to enter into a low power shutdown

mode. The power supply current during shutdown is less

than 235µA.

Supply Current vs Noise Trade-Off

The passband of the LTC6603 is determined by the master

clock frequency (which is set by RBIAS when the internal

oscillator is used), LPF1 and LPF0. The LTC6603 is op-

timized for use with RBIAS having a value between 200k

and 30.9k to set the internal oscillation frequency from

12.36MHz to 80MHz. The lowpass corner frequency is

proportional to the clock frequency (internal or external).

Figure 14. fCLK vs Filter Cutoff Frequencies Figure 15. Supply Current vs Filter Cutoff Frequency

Table 7. Total Input Referred Integrated Noise Voltage (Passband Gain = 24dB)

LPF1 LPF0 NOISE VOLTAGE

0 0 –81dBm

0 1 –80dBm

1 X –76dBm

To extend the ﬁ lter’s operational frequency range, the

master clock is divided down before reaching the ﬁ lter.

LPF1 and LPF0 set the division ratio of the lowpass clock.

Figure 14 shows the possible cutoff frequencies versus

fCLK, LPF1 and LPF0. Overlapping frequency ranges allow

more than one possible choice of bandwidth settings for

some cutoff frequencies. Figure 15 shows supply current

as a function of the ﬁ lter cutoff frequency, LPF1 and LPF0.

Note that the higher bandwidth setting always gives the

minimum supply current for a given cutoff frequency. The

input referred integrated noise voltage for a passband

gain of 24dB is shown in Table 7. Note that the noise is

higher for the higher bandwidth settings. This creates a

tradeoff between supply current and noise. For a given

cutoff frequency, using the highest possible bandwidth

setting gives the minimum supply current at the expense

of higher noise.

FILTER CUTOFF FREQUENCY (Hz)

fCLK (MHz)

6603 F14

100

10k 1M 10M100k

LPF1 = 1

LPF1 = 0

LPF0 = 1

LPF1 = 0

LPF0 = 0

FILTER CUTOFF FREQUENCY (Hz)

SUPPLY CURRENT (mA)

6603 F15

180

160

140

120

100

10k 1M 10M100k

LPF1 = 1

LPF1 = 0

LPF0 = 1

LPF1 = 0

LPF0 = 0

TA = 25°C

VS = 3V

CLKCNTL PIN FLOATING

GAIN = 0dB

LTC6603

6603fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

TYPICAL APPLICATIONS

UF Package

24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1697)

LTC6603 Parallel Clock Control LTC6603 SPI Clock Control

4.00 ± 0.10

(4 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

2423

BOTTOM VIEW—EXPOSED PAD

2.45 ± 0.10

(4-SIDES)

0.75 ± 0.05 R = 0.115

TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UF24) QFN 0105

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.70 ±0.05

0.25 ±0.05

0.50 BSC

2.45 ± 0.05

(4 SIDES)

3.10 ± 0.05

4.50 ± 0.05

PACKAGE

OUTLINE

PIN 1 NOTCH

R = 0.20 TYP OR

0.35 × 45° CHAMFER

6603 TA02

+INA

V+IN V+AV+D

–INA

+INB

–INB

CAP

GAIN1

GAIN0(D0)

GND

RBIAS

VOCM

+OUTA

–OUTA

+OUTB

–OUTB

CLKCNTL

SDO

SDI

LPF0(SCLK)

LPF1(CS)

CLKIO

SER

LTC6603

1216

0.1µF

R3 R1

VOCM

DIODES INC

DMN2004DWK

CLK1

CLK1 CLK0

0 0 RBIAS1 f

CLK1

0 1 RBIAS2 f

CLK2

1 0 RBIAS3 f

CLK3

1 1 RBIAS4 f

CLK4

RBIAS1 > RBIAS2 OR RBIAS3

RBIAS =

RBIAS IN k

fCLK in MHz

R1 = RBIAS1 R2 = R3 = RBIAS4 =

CLK0

LPF1

LPF0

GAIN1

GAIN0

2472

fCLK

DESIGN PROCEDURE

1. CHOOSE fCLK1, fCLK2 AND fCLK3

2. CALCULATE RBIAS1, RBIAS2 AND RBIAS3

3. CALCULATE R2, R3 AND RBIAS4

RBIAS1 • RBIAS2

RBIAS1 – RBIAS2

RBIAS1 • RBIAS3

RBIAS1 – RBIAS3

R1 • R2 • R3

R1 • (R2 + R3) + R2 • R3

6603 TA03

+INA

V+IN V+AV+D

–INA

+INB

–INB

CAP

GAIN1

GAIN0(D0)

GND

RBIAS

VOCM

+OUTA

–OUTA

+OUTB

–OUTB

CLKCNTL

SDO

SDI

LPF0(SCLK)

LPF1(CS)

CLKIO

SER

LTC6603

0.1µF

1216

0.1µF

SCLK

SDI

VOUT

GND

V+

0.1µF

VCR2

CS1 CS2SCK SDI

LTC2630

8-BIT DAC

IF R1 = 51.1k and R2 = 78.7k THEN

THE fCLK RANGE IS 12.36MHz to 80MHz

DAC VOUT RANGE 0V TO 2.5V

(USING THE LTC2630 INTERNAL REFERENCE)

R1 = VC RANGE 0V to 2.5V, VB= 1.17V

IF VC = 0V THEN fCLK= fCLKHI

IF VC = 2.5V THEN fCLK= fCLKLO

5.282 • 1012

1.137fCLKHI + fCLKLO , R2 = 5.282 • 1012

fCLKHI – fCLKLO

CLK =2.472 • 1012 R1+R2

R1• R2 VC

B•R2











PACKAGE DESCRIPTION

LTC6603

6603fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0709 REV A • PRINTED IN USA

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6603 TA04

+INA

V+IN V+AV+D

–INA

+INB

–INB

CAP

GAIN1

GAIN0(D0)

GND

RBIAS

VOCM

+OUTA

–OUTA

+OUTB

–OUTB

CLKCNTL

SDO

SDI

LPFO(SCLK)

LPF1(CS)

CLKIO

SER

LTC6603

0.1µF 0.1µF

100pF 10pF

10pF

100pF 10pF

10pF

49.9Ω 56nH*

5V 3V

1216

0.1µF

40.2k

BASEBAND

GAIN CONTROL

IOUT

QOUT

LTC5575

VCC

IOUT+

IOUT–

QOUT+

QOUT–

GND GND GNDRF

GND LO VCC

GND

10pF

10pF 100pF

10pF

56nH*

*COILCRAFT 0603HP

10pF 100pF

56nH*

RF IN

LO IN

1000pF0.1µF1µF

4321

9101112

1000pF

GAIN1 GAIN0

3.9pF

5.6pF