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Single-chip built-in FET type Switching Regulators
Output 2A or More High Efficiency
Step-down Switching Regulator
with Built-in Power MOSFET
BD9111NV
●Description
ROHM’s high efficiency step-down switching regulator BD9111NV is a power supply designed to produce a low voltage
including 3.3 volts from 5 volts power supply line. Offers high efficiency with our original pulse skip control technology and
synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load.
●Features
1) Offers fast transient response with current mode PWM control system.
2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET)
and SLLMTM (Simple Light Load Mode)
3) Incorporates soft-start function.
4) Incorporates thermal protection and ULVO functions.
5) Incorporates short-current protection circuit with time delay function.
6) Incorporates shutdown function
7) Employs small surface mount package : SON008V5060
●Applications
Power supply for LSI including DSP, Micro computer and ASIC
●Absolute Maximum Ratings (Ta=25℃)
Parameter Symbol Ratings Unit
VCC Voltage VCC -0.3～+7 *1 V
PVCC Voltage PVCC -0.3～+7 *1 V
EN Voltage VEN -0.3～+7 V
SW,ITH Voltage VSW,VITH -0.3～+7 V
Power Dissipation 1 Pd1 900*2 mW
Power Dissipation 2 Pd2 3900*3 mW
Operating temperature range Topr -25～+105 ℃
Storage temperature range Tstg -55～+150 ℃
Maximum junction temperature Tjmax +150 ℃
*1 Pd should not be exceeded.
*2 Derating in done 7.2mW/℃ for temperatures above Ta=25℃, Mounted on 70mm×70mm×1.6mm Glass Epoxy PCB (the density of copper:3%)
*3 Derating in done 31.2mW/℃ for temperatures above Ta=25℃, Mounted on JESD51-7.
●Operating Conditions (Ta=25℃)
Parameter Symbol Ratings Unit
Min. Typ. Max.
VCC Voltage VCC *4 4.5 5.0 5.5 V
PVCC Voltage PVCC *4 4.5 5.0 5.5 V
EN Voltage VEN 0 - VCC V
SW average output current Isw *4 - - 2.0 A
*4 Pd should not be exceeded.
No.10027EBT32
Technical Note
BD9111NV
2/13
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© 2010 ROHM Co., Ltd. All rights reserved.
●Electrical Characteristics (Ta=25℃, VCC=PVCC=3.3V, EN=VCC.)
Parameter Symbol Limits Unit Conditions
Min. Typ. Max.
Standby current ISTB - 0 10 μA EN=GND
Bias current ICC - 250 450 μA
EN Low voltage VENL - GND 0.8 V Standby mode
EN High voltage VENH 2.0 VCC - V Active mode
EN input current IEN - 1 10 μA VEN=5V
Oscillation frequency FOSC 0.8 1 1.2 MHz
Pch FET ON resistance RONP - 200 320 mΩ PVCC=5V
Nch FET ON resistance RONN - 150 270 mΩ PVCC=5V
Output voltage VOUT 3.250 3.300 3.350 V
ITH SInk current ITHSI 10 20 - μA VOUT=3.6V
ITH Source Current ITHSO 10 20 - μA VOUT=3.0V
UVLO threshold voltage VUVLO1 3.6 3.8 4.0 V VCC=5→0V
UVLO release voltage VUVLO2 3.65 3.90 4.2 V VCC=0→5V
Soft start time TSS 0.5 1 2 ms
Timer latch time TLATCH 1 2 3 ms SCP/TSD operated
Output Short circuit Threshold Voltage VSCP - 1.65 2.31 VOUT V
OUT=3.3→0V
●Block Diagram, Application Circuit
Fig.1 BD9111NV TOP View Fig.2 BD9111NV Block Diagram
●Pin number and function
Pin No. Pin name PIN function
1 VOUT Output voltage pin
2 VCC VCC power supply input pin
3 ITH GmAmp output pin/Connected phase compensation capacitor
4 GND Ground
5 PGND Nch FET source pin
6 SW Pch/Nch FET drain output pin
7 PVCC Pch FET source pin
8 EN Enable pin(Active High)
VOUT1
VCC 2
ITH 3
GND 4
8 EN
7 PVCC
6 SW
5 PGND
TOP View
Output
5V
Input
PVCC
PGND
SW
GND
Gm Amp. 2.2µH
VCC
R
S
Q
OSC
UVLO
TSD
22µF
VCC
VCC
CLK
SLOPE
EN
Current
Comp 22µF
8
7
2
6
5
4
Soft
Start
Current
Sense/
Protect
+
Driver
Logic
VREF
ITH
RITH CITH
3
SCP
VOUT
1
Technical Note
BD9111NV
3/13
www.rohm.com 2010.04 - Rev.B
© 2010 ROHM Co., Ltd. All rights reserved.
0.0
1.0
2.0
3.0
4.0
5.0
012345
OUTPUT CURRENT:IOUT[A]
OUTPUT VOLTAGE:VOUT[V]
0.0
0.5
1.0
1.5
2.0
012345
EN VOLTAGE:VEN[V]
OUTPUT VOLTAGE:VOUT[V]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
012345
INPUT VOLTAGE:VCC[V]
OUTPUT VOLTAGE:VOUT[V]
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
Io=2A
Ta=25℃
●Characteristics data
Fig.3 Vcc-Vout Fig.4 Ven-Vout Fig.5 Iout-Vout
Fig. 6 Ta-VOUT Fig.7 Efficiency Fig.8 Ta-FOSC
Fig.9 Ta-RONN, RONP Fig.10 Ta-VEN Fig.11 Ta-ICC
Io=0A
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000 10000
OUTPUT CURRENT:IOUT[mA]
EFFICIENCY:
η[%]
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
-25 0 25 50 75 100
TEMPERATURE:Ta[℃]
OUTPUT VOLTAGE:VOUT[V]
VCC=5V
Io=0A
VCC=5V
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
-25 0 25 50 75 100
TEMPERATURE:Ta[℃]
FREQUENCY:FOSC[MHz]
Ta=25℃
VCC=5V
0
50
100
150
200
250
300
350
400
-25 0 25 50 75 100
TEMPERATURE:Ta[℃]
CIRCUIT CURRENT:ICC [μA]
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
-25 0 25 50 75 100
TEMPERATURE:Ta[℃]
ON RESISTANCE:R ON [Ω]
PMOS
NMOS
VCC=5V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-25 0 25 50 75 100
TEMPERATURE:Ta[℃]
EN VOLTAGE:VEN[V]
VCC=5V VCC=5V
Technical Note
BD9111NV
4/13
www.rohm.com 2010.04 - Rev.B
© 2010 ROHM Co., Ltd. All rights reserved.
0.8
0.9
1
1.1
1.2
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
INPUT VOLTAGE:VCC[V]
FREQUENCY:FOSC[MHz]
Fig.12 Vcc-Fosc Fig.13 Soft start waveform Fig.14 SW waveform Io=10mA
Fig.15 SW waveform Io=200mAs Fig. 16 Transient response
Io=1A→2A(10μs)
Fig.17 Transient response
Io=2A→1A(10μs)
VOUT
IOUT
VOUT
IOUT
【SLLM control】
VCC=5V
Ta=25℃
【PWM control】
VCC=5V
Ta=25℃
100mV
VCC=5V
Ta
=
25
℃
110mV
SW
VOUT
Ta=25℃
VCC=5
V
Ta=25℃
Io=0
A
1msec
VCC=5
V
Ta=25℃
VCC=PVCC
=EN
VOUT
Technical Note
BD9111NV
5/13
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© 2010 ROHM Co., Ltd. All rights reserved.
●Information on advantages
Advantage 1：Offers fast transient response with current mode control system.
Voltage drop due to sudden change in load was reduced by about 50%.
Fig.18 Comparison of transient response
Advantage 2： Offers high efficiency for all load range.
・For lighter load:
Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching
dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance
dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load.
・For heavier load:
Utilizes the synchronous rectifying mode and the low on-resistance
MOS FETs incorporated as power transistor.
ON resistance of P-channel MOS FET : 200mΩ(Typ.)
ON resistance of N-channel MOS FET : 160mΩ(Typ.)
Achieves efficiency improvement for heavier load.
Offers high efficiency for all load range with the improvements mentioned above.
Advantage 3：・Supplied in smaller package due to small-sized power MOS FET incorporated.
Reduces a mounting area required.
Fig.20 Example application
Fig.19 Efficiency
Conventional product (Load response IO=0.1A→0.6A) BD9111NV (Load response IO=1A→2A)
・Output capacitor Co required for current mode control: 22μF ceramic capacitor
・Inductance L required for the operating frequency of 1 MHz: 2.2μH inductor
(BD9111NV:Co=22μF, L=2.2μH)
0.001 0.01 0.1 1
0
50
100
①
②
PWM
SLLM
①inprovement by SLLM system
②improvement by synchronous rectifier
Efficiency η[%]
Output current Io[A]
VOUT
IOUT
VOUT
IOUT
160mV 100mV
RITH
L
Co
VOUT
CITH
VCC
Cin
10mm
15mm
RITH
CITH
CIN
CO
L
DC/DC
Convertor
Controller
Technical Note
BD9111NV
6/13
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© 2010 ROHM Co., Ltd. All rights reserved.
●Operation
BD9111NV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing
current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load,
while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency.
○Synchronous rectifier
It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC,
and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power
dissipation of the set is reduced.
○Current mode PWM control
Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.
・PWM (Pulse Width Modulation) control
The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P-channel MOS FET (while a
N-channel MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp)
receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback
control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the
P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control
repeat this operation.
・SLLM (Simple Light Load Mode) control
When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse
is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without
voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa.
Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current
Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is
tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the
switching dissipation and improves the efficiency.
Fig.21 Diagram of current mode PWM control
Fig.22 PWM switching timing chart Fig.23 SLLMTM switching timing chart
Curren
t
Comp
SET
RESET
SW
VOUT
PVCC
GND
GND
GND
IL(AVE)
VOUT(AVE)
SENSE
FB
Curren
t
Comp
SET
RESET
SW
VOUT
PVCC
GND
GND
GND
0A
VOUT(AVE)
SENSE
FB
IL
Not switching
IL
OSC
Level
Shift Driver
Logic
RQ
S
IL
SW
ITH
Current
Comp
Gm Amp.
SET
RESET
FB
Load
SENSE
VOUT
VOUT
Technical Note
BD9111NV
7/13
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© 2010 ROHM Co., Ltd. All rights reserved.
●Description of operations
・Soft-start function
EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during
startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.
・Shutdown function
With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference
voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0μF (Typ.).
・UVLO function
Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of
100mV (Typ.) is provided to prevent output chattering.
Fig.24 Soft start, Shutdown, UVLO timing chart
・Short-current protection circuit with time delay function
Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for
the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking
UVLO.
Fig.25 Short-current protection circuit with time delay timing chart
t2=TLATCH
Output OFF
latch
EN
VOUT
Output Short circuit
Threshold Voltage
IL
Standby
mode Operating mode Operating mode
EN Timer latch EN
Standby
mode
IL Limi
t
t1<TLATCH
Hysteresis 100mV
Ts s Ts s Ts s
Soft start
Standby mode Operating mode
Standby
mode Operating mode
Standby
mode Operating mode Standby mode
UVLO
EN UVLO
UVLO
VCC
EN
VOU
T
Technical Note
BD9111NV
8/13
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© 2010 ROHM Co., Ltd. All rights reserved.
●Switching regulator efficiency
Efficiency ŋ may be expressed by the equation shown below:
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:
Dissipation factors:
1) ON resistance dissipation of inductor and FET：PD(I2R)
2) Gate charge/discharge dissipation：PD(Gate)
3) Switching dissipation：PD(SW)
4) ESR dissipation of capacitor：PD(ESR)
5) Operating current dissipation of IC：PD(IC)
1)PD(I2R)=IOUT2×(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET,f[Hz]：Switching frequency,V[V]：Gate driving voltage of FET)
4)PD(ESR)=IRMS2×ESR (IRMS[A]：Ripple current of capacitor,ESR[Ω]：Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.)
●Consideration on permissible dissipation and heat generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input
voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation
must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
If VCC=5V, VOUT=3.3V, RONP=0.2Ω, RONN=0.16Ω
IOUT=2A, for example,
D=VOUT/VCC=3.3/5.0=0.66
RON=0.66×0.20+(1-0.66)×0.16
=0.132+0.0544
=0.1864[Ω]
P=22×0.1864＝0.7456W]
As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater.
With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
η= VOUT×IOUT
Vin×Iin
×100[%]= POUT
Pin
×100[%]= POUT
POUT+PDα
×100[%]
P=IOUT2×RON
RON=D×RONP+(1-D)RONN
D：ON duty (=VOUT/VCC)
RCOIL：DC resistance of coil
RONP：ON resistance of P-channel MOS FET
RONN：ON resistance of N-channel MOS FET
IOUT：Output current
0 25 50 75 100 125 150
0
2.0
3.0
4.0
②0.90W
①3.9W
105
1.0
③0.64W
Fig.26 Thermal derating curve
(SON008V5060)
Power dissipation:Pd [W]
Ambient temperature:Ta [℃]
①for SON008V5060
JEDEC 4 layer board 76.2×114.3×1.6mm
θj-a=32.1℃/W
②for SON008V5060
ROHM standard 1 layer board 70×70×1.6mm
θj-a=138.9℃/W
③ IC only
θj-a=195.3℃/W
Vin2×CRSS×IOUT×f
IDRIVE
3)PD(SW)= (CRSS[F]：Reverse transfer capacitance of FET,IDRIVE[A]：Peak current of gate.)
Technical Note
BD9111NV
9/13
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© 2010 ROHM Co., Ltd. All rights reserved.
●Selection of components externally connected
1. Selection of inductor (L)
* Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency.
The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating.
If VCC=5V, VOUT=3.3V, f=1MHz, ΔIL=0.3×2A=0.6A, for example,(BD9111NV)
* Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency.
2. Selection of output capacitor (CO)
3. Selection of input capacitor (Cin)
A low ESR 22μF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
The inductance significantly depends on output ripple current.
s seen in the equation (1), the ripple current decreases as the
inductor and/or switching frequency increases.
Δ
IL=
(VCC-VOUT)×VOUT
L×VCC×f [A]・・・
(
1
)
A
ppropriate ripple current at output should be 20% more or less of the
maximum out
p
ut current.
ΔIL=0.3×IOUTmax. [A]・・・(2)
L=
(VCC-VOUT)×VOUT
ΔIL×VCC×f [H]・・・
(
3
)
(ΔIL: Output ripple current, and f: Switching frequency)
Output capacitor should be selected with the consideration on the stability region
and the equivalent series resistance required to smooth ripple voltage.
Output ripple voltage is determined by the equation (4)：
ΔVOUT=ΔIL×ESR [V]・・・(4)
(ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor)
*Rating of the capacitor should be determined allowing sufficient margin
against output voltage. Less ESR allows reduction in output ripple voltage.
22μF to 100μF ceramic capacitor is recommended.
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage.
The ripple current IRMS is given by the equation (5):
Fig.28 Output capacitor
(
5.0-3.3
)
×3.3
0.6×5.0×1M
L= =1.87μ → 2.2[μH]
Fig.29 Input capacitor
ΔIL
VCC
IL
L
Co
VOUT
Fig.27 Output ripple current
IL
VCC
L
Co
VOUT
ESR
VCC
L Co
VOUT
Cin
IRMS=IOUT×
VOUT
(
VCC-VOUT
)
VCC
[
A
]
・・・
(
5
)
√
When Vcc is twice the VOUT, IRMS=
IOUT
2
< Worst case > IRMS(max.)
IRMS=2×
3.3
(
5.0-3.3
)
5.0 =0.947
[
ARMS
]
√
If VCC=5.0V, VOUT=3.3V, and IOUTmax.=2A, (BD9111NV)
Technical Note
BD9111NV
10/13
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© 2010 ROHM Co., Ltd. All rights reserved.
4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
Fig.30 Open loop gain characteristics
Fig.31 Error amp phase compensation characteristics
fp=
2π×RO×CO
1
fz(ESR)=2π×ESR×CO
1
Pole at power amplifie
r
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
fp(Min.)=2π×ROMax.×CO
1[Hz]←with lighter load
fp(Max.)=2π×ROMin.×CO
1[Hz] ←with heavier load
Zero at power amplifie
r
fz(Amp.)=2π×RITH×CITH
1
GND,PGND
SW
VCC,PVCC
EN
VOUT
ITH
VCC
VOUT
Cin
RITH
CITH
L
ESR
CO
RO
VOUT
Fig.32 Typical application
fz(Amp.)= fp(Min.)
2π×RITH×CITH
1 = 2π×ROMax.×CO
1
Gain
[dB]
Phase
[deg]
A
0
0
-90
A
0
0
-90
fz(Amp.)
fp(Min.)
fp(Max.)
fz(ESR)
IOUTMin. IOUTMax.
Gain
[dB]
Phase
[deg]
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change. (This
is because when the capacitance is doubled, the capacito
r
ESR reduces to half.)
Technical Note
BD9111NV
11/13
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© 2010 ROHM Co., Ltd. All rights reserved.
●BD9111NV Cautions on PC Board layout
Fig.33 Layout diagram
①For the sections drawn with heavy line, use thick conductor pattern as short as possible.
②Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to
the pin PGND.
③Lay out CITH and RITH between the pins ITH and GND as near as possible with least necessary wiring.
※SON008V5060 (BD9111NV) has thermal FIN on the reverse of the package.
The package thermal performance may be enhanced by bonding the FIN to GND plane which take a large area of PCB.
●Recommended components Lists on above application
Symbol Part Value Manufacturer Series
L Coil 2.2uH TDK LTF5022-2R2N3R2
CIN Ceramic capacitor 22uF Kyocera CM32X5R226M10A
CO Ceramic capacitor 22uF Kyocera CM316B226M06A
CITH Ceramic capacitor 680pF murata GRM18 Serise
RITH Resistance 12kΩ Rohm MCR03 Serise
* The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your
application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the
depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When
switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode
established between the SW and PGND pins.
●I/O equivalence circuit
Fig.34 I/O equivalence circuit
VOUT
VCC
ITH
GND
EN
PVCC
SW
PGND
VCC
RITH
GND
Co
CIN
VOUT
EN
L
CITH
③
①
②
1
2
3
4
8
7
6
5
EN
・EN pin ・SW pin PVCC
SW
PVCC PVCC
ITH
・ITH pin
VCC
VCC
VOUT
10kΩ
・VOUT pin
Technical Note
BD9111NV
12/13
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© 2010 ROHM Co., Ltd. All rights reserved.
●Notes for use
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute
maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken,
short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the
absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mismounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may
result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and
power supply or GND may also cause breakdown.
4.Operation in Strong electromagnetic field
Be noted that using the IC in the strong electromagnetic radiation can cause operation failures.
5. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to
protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be
used thereafter for any operation originally intended.
6. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the
capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper
grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the
inspection process, be sure to turn OFF the power supply before it is connected and removed.
7. Input to IC terminals
This is a monolithic IC with P+ isolation between P-substrate and each element as illustrated below.
This P-layer and the N-layer of each element form a P-N junction, and various parasitic element are formed.
If a resistor is joined to a transistor terminal as shown in Fig 35.
○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side),
or GND>Terminal B (at transistor side); and
○if GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,
and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such
manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in
activation of parasitic elements.
Fig.35 Simplified structure of monorisic IC
8. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
9 . Selection of inductor
It is recommended to use an inductor with a series resistance element (DCR) 0.1Ω or less. Note that use of a high DCR
inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a specified
period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched OFF.
When using an inductor over 0.1Ω, be careful to ensure adequate margins for variation between external devices and this
IC, including transient as well as static characteristics. Furthermore, in any case, it is recommended to start up the output
with EN after supply voltage is within operation range.
Resistor Transistor (NPN)
N
N N P+ P
+
P
P substrate
GND
Parasitic element
Pin A
N
N P+ P+
P
P substrate
GND
Parasitic element
Pin B C B
E
N
GND
Pin A
P
aras
iti
c
element
Pin B
Other adjacent elements
E
B C
GND
P
aras
iti
c
element
Technical Note
BD9111NV
13/13
www.rohm.com 2010.04 - Rev.B
© 2010 ROHM Co., Ltd. All rights reserved.
●Ordering part number
B D 9 1 1 1 N V - E 2
Part No. Part No.
9111
Package
NV : SON008V5060
Packaging and forming specification
E2: Embossed tape and reel
(SON008V5060)
(Unit : mm)
SON008V5060
0.08 S
S
765
4321
8
(0.22)
C0.25
1PIN MARK
+0.03
-
0.02
0.02
0.59 0.4+0.05
-
0.04
5.0±0.15
6.0±0.15
4.2±0.1
3.6±0.1
0.8±0.1 1.0MAX
1.27
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
2000pcs
E2
()
Direction of feed
Reel 1pin
R1010
A
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© 2010 ROHM Co., Ltd. All rights reserved.
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