FEDL610Q101-01 Issue Date: Jan. 23, 2013 ML610Q101/ML610Q102 8-bit Microcontroller GENERAL DESCRIPTION This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as timers, PWM, UART, voltage level supervisor (VLS) function, and 10-bit successive approximation type A/D converter, are incorporated around 8-bit CPU nX-U8/100. The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipe line architecture parallel processing. The on-chip debug function that is installed enables program debugging and programming. FEATURES * CPU - 8-bit RISC CPU (CPU name: nX-U8/100) - Instruction system: 16-bit instructions - Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on - On-Chip debug function - Minimum instruction execution time 30.5s (@32.768kHz system clock) 0.122s (@8.192MHz system clock) * Internal memory - ML610Q101 : Internal 4Kbyte Flash ROM (2Kx16 bits) (including unusable 32 byte test data area) - ML610Q102 : Internal 6Kbyte Flash ROM (3Kx16 bits) (including unusable 32 byte test data area) - Internal 256byte data RAM (256x8 bits) * Interrupt controller - 1 non-maskable interrupt source (Internal source: 1) - 21 maskable interrupt sources (Internal sources: 16, External sources: 5) * Time base counter (TBC) - Low-speed time base counter x1 channel - High-speed time base counter x1 channel * Watchdog timer (WDT) - Non-maskable interrupt and reset - Free running - Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) * Timer - 8 bits x 6 channels (16-bit configuration available) - Support Continuos timer mode/one shot timer mode - Timer start/stop function by software or external trigger input 1/21 FEDL610Q101 -01 ML610Q101/ML610Q102 * PWM - Resolution 16 bits x 1 channel - Support Continuos timer mode/one shot timer mode - PWM start/stop function by software or external trigger input * UART - Half-duplex - TXD/RXD x 1 channels - Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits - Positive logic/negative logic selectable - Built-in baud rate generator * Successive approximation type A/D converter (SA-ADC) - 10-bit A/D converter - Input x 6 channels * Analog Comparator - Operating voltage: VDD = 2.7V to 5.5V - Input voltage by common mode: VDD = 0.1V to VDD - 1.5V - Hysteresis (Comparator0 only): 20mV(Typ.) - Allows selection of interrupt disabled mode,falling-edge interrupt mode,rising-edge interrupt mode, or both-edge interrupt mode. * General-purpose ports (GPIO) - Input/output port x 11 channels (including secondary functions) * Reset - Reset by the RESET_N pin - Reset by power-on detection - Reset by the watchdog timer (WDT) overflow - Reset by voltage level supervisor(VLS) * Voltage level supervisor(VLS) - Judgment accuracy: 3.0% (Typ.) - It can be used for low level detection reset. * Clock - Low-speed clock: Built-in RC oscillation (32.768 kHz) - High-speed clock: Built-in PLL oscillation (16.384 MHz), external clock The clock of the CPU is 8.192MHz(Max) - Selection of high-speed clock mode by software: Built-in PLL oscillation, external clock * Power management - HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states). - STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.) - Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) - Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals. 2/21 FEDL610Q101 -01 ML610Q101/ML610Q102 * Shipment - 16-pin plastic SSOP ML610Q101-xxxMB (Blank product: ML610Q101-NNNMB) ML610Q102-xxxMB (Blank product: ML610Q102-NNNMB) * Guaranteed operating range - Operating temperature: -40C to 85C - Operating voltage: VDD = 2.7V to 5.5V 3/21 FEDL610Q101 -01 ML610Q101/ML610Q102 BLOCK DIAGRAM ML610Q101 Block Diagram Figure 1 show the block diagram of the ML610Q101. "*" indicates secondary function, tertiary function or quaternary function of each port. CPU (nX-U8/100) EPSW13 GREG 015 PSW Timing Controller On-Chip ICE ALU TEST Instruction Decoder DSR/CSR EA PC Instruction Register RESET & TEST INT 1 UART RXD0 TXD0* PWM PWMC* Interrupt Controller Power INT 1 10bit-ADC INT 4 INT 6 INT 2 Analog Comparator x2 Program Memory (Flash) 4kbyte BUS Controller RAM 256byte INT 1 CMP0P* CMP0M* 1 CMP0POUT* CMP0NOUT* LR Data-bus OSC AIN0* to AIN5* ECSR13 SP VDD VSS RESET_N ELR13 INT 1 WDT INT 1 TBC 8bit Timer x6 INT 5 GPIO PA0 to PA2 PB0 to PB7 VLS CMP1P* CMP1OUT* Figure 1 ML610Q101 Block Diagram 4/21 FEDL610Q101 -01 ML610Q101/ML610Q102 ML610Q102 Block Diagram Figure 2 show the block diagram of the ML610Q102. "*" indicates secondary function, tertiary function or quaternary function of each port. CPU (nX-U8/100) EPSW13 GREG 015 PSW Timing Controller On-Chip ICE ALU TEST Instruction Decoder DSR/CSR EA PC Instruction Register RESET & TEST INT 1 UART RXD0 TXD0* PWM PWMC* Interrupt Controller Power INT 1 INT 4 WDT INT 6 INT 2 INT 1 TBC 10bit-ADC Analog Comparator x2 Program Memory (Flash) 6kbyte BUS Controller RAM 256byte INT 1 CMP0P* CMP0M* CMP0OUT* CMP0POUT* CMP0NOUT* LR Data-bus OSC AIN0* to AIN5* ECSR13 SP VDD VSS RESET_N ELR13 8bit Timer x6 INT 5 GPIO PA0 to PA2 PB0 to PB7 INT 1 VLS CMP1P* CMP1OUT* Figure 2 ML610Q102 Block Diagram 5/21 FEDL610Q101 -01 ML610Q101/ML610Q102 PIN CONFIGURATION ML610Q101/ML610Q102 SSOP16 Pin Layout Figure 3 show the SSOP16 pin layout of the ML610Q101/ML610Q102. RESET_N TEST PB0 / PWMC / OUTCLK / CMP1OUT PB1 / TXD0 PB2 / CMP0POUT PB3 / CMP0MOUT PA2 / CLKIN / CMP0OUT VPP Figure 3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PA0 / PWMC / OUTCLK / TM9OUT PB7 / LSCLK / PWMC VDD VSS PB6 / CLKIN PB5 / PB4 / TXD0 PA1 / LSCLK / TMFOUT ML610Q101/ML610Q102 SSOP16 Pin Configuration 6/21 FEDL610Q101 -01 ML610Q101/ML610Q102 LIST OF PINS PIN No. 1 Primary function Pin I/O Function name RESET_N I Reset input pin Input/output pin for testing Secondary function Pin I/O Function name Tertiary function Pin I/O Function name Quaternary function Pin I/O Function name PWMC O PWMC output OUTCLK O High-speed clock output CMP1O UT O CMP1 output TXD0 O UART output 2 TEST 3 PB0/ EXI4/ AIN2/ RXD0 I/O 4 PB1/ EXI5/ AIN3 I/O 5 PB2 I/O Input/output port, CMP0P OUT O CMP0N output 6 PB3 I/O Input/output port CMP0N OUT O CMP0N output 7 PA2/EXI2 I/O CLKIN I clock input CMP0O UT O CMP0 output 8 VPP 9 PA1/ EXI1/ AIN1/ CMP1P I/O LSCLK O Low speed clock output TMF OUT O timer F output 10 PB4/ CMP0P I/O TXD0 O UART data output 11 PB5/ RXD0/ CMP0M I/O 12 PB6/ AIN4 I/O CLKIN I 13 Vss 14 VDD 15 PB7/ AIN5 I/O LSCLK O Low-speed clock output PWMC O PWMC output 16 PA0/ EXI0/ AIN0 I/O PWMC O PWMC output OUTCLK O High-speed clock output TM9OU T O timer 9 output I/O Input/output port, External interrupt 4, ADC input 2, UART receive Input/output port, External interrupt 5,ADC input 3 Input/output port, External interrupt Power supply pin for Flash ROM Input port, External interrupt 1, ADC input 1, Comparator1 non-inverting input Input/output port, Comparator0 non-inverting input Input/output port, UART data receive, Comparator1 inverting input Input/output port, ADC input 4 Negative power supply pin Positive power supply pin Input/output port, ADC input 5 Input port, External interrupt 0, ADC input 0 clock input data 7/21 FEDL610Q101 -01 ML610Q101/ML610Q102 PIN DESCRIPTION Pin name I/O Description Primary/ Secondary/ Tertiary/ Quaternary Logic -- Negative System RESET_N I CLKIN I Reset input pin. When this pin is set to a "L" level, system reset mode is set and the internal section is initialized. When this pin is set to a "H" level subsequently, program execution starts. A pull-up resistor is internally connected. High-speed clock output pin. This pin is used as the tertiary function of the PA2 or the secondary function of PB6 pin. LSCLK O Low-speed clock output pin. This pin is used as the tertiary function of the PA1 or the secondary function of the PB7 pin. High-speed clock output pin. This pin is used as the tertiary function of the PA0 or PB0 pin. General-purpose input/output port General-purpose input/output port. PA0 to PA2 Since these pins have secondary functions and tertiary functions and quaternary I/O functions, the pins cannot be used as a port when the secondary functions and PB0 to PB7 tertiary functions and quaternary functions are used. UART UART0 data output pin. This pin is used as the tertiary function of the PB1 or O TXD0 PB4 pin. UART0 data input pin. This pin is used as the primary function of the PB0 or PB5 I RXD0 or the quaternary function of the PB7 pin. PWM PWMC output pin. This pin is used as the secondary function of the PB0 or PA0 O PWMC or the quaternary function of the PB7 pin. External interrupt External maskable interrupt input pins. Interrupt enable and edge selection can I be performed for each bit by software. These pins are used as the primary EXI0 to 2 functions of the PA0 - PA2 pins. External maskable interrupt input pins. Interrupt enable and edge selection can I be performed for each bit by software. These pins are used as the primary EXI4,5 functions of the PB0, PB1 pins. Timer External clock input pin used for both Timer E and Timer F.These pins are used I TnTG as the primary function of the PA0-PA2, PB0-PB7 pins. O Timer 9 output pin. This pin is used as the quaternary function of the PA0 pin. TM9OUT O Timer F output pin. This pin is used as the quaternary function of the PA1 pin. TMFOUT OUTCLK O Secondary/ Tertiary Secondary/ Tertiary -- -- Tertiary -- Primary Positive Tertiary Positive Primary Positive Secondary Quaternary Positive Primary Positive/ negative Primary Positive/ negative Primary -- Quaternary Quaternary Positive Positive 8/21 FEDL610Q101 -01 ML610Q101/ML610Q102 Pin name I/O Description Successive approximation type A/D converter Channel 0 analog input for successive approximation type A/D converter. This AIN0 I pin is used as the primary function of the PA0 pin. Channel 1 analog input for successive approximation type A/D converter. This AIN1 I pin is used as the primary function of the PA1 pin. Channel 2 analog input for successive approximation type A/D converter. This AIN2 I pin is used as the primary function of the PB0 pin. Channel 3 analog input for successive approximation type A/D converter. This AIN3 I pin is used as the primary function of the PB1 pin. Channel 4 analog input for successive approximation type A/D converter. This AIN4 I pin is used as the primary function of the PB6 pin. Channel 5 analog input for successive approximation type A/D converter. This AIN5 I pin is used as the primary function of the PB7 pin. Conparator Non-inverting input for comparator0. This pin is used as the primary function of CMP0P I the PB4 pin. Inverting input for comparator0. This pin is used as the primary function of the CMP0M I PB5 pin. Output for comparator0. This pin is used as the quaternary function of the PA2 CMP0OUT O pin. Output for comparator0. This pin is used as the quaternary function of the PB2 CMP0OUT O pin. Output for comparator0. This pin is used as the quaternary function of the PB3 CMP0OUT O pin. Non-inverting input for comparator1. This pin is used as the primary function of CMP1P I the PA1 pin. Output for comparator1. This pin is used as the quaternary function of the PB0 CMP1OUT O pin. For testing TEST I/O Input/output pin for testing. A pull-down resistor is internally connected. Power supply VSS -- Negative power supply pin. VDD -- Positive power supply pin. VPP -- Power supply pin for Flash ROM Primary/ Secondary/ Tertiary/ Quaternary Logic Primary -- Primary -- Primary -- Primary -- Primary -- Primary -- Primary -- Primary -- Quaternary -- Quaternary -- Quaternary -- Primary -- Quaternary -- -- Positive -- -- -- -- -- -- 9/21 FEDL610Q101 -01 ML610Q101/ML610Q102 ML610Q101/ML610Q102 TERMINATION OF UNUSED PINS Table 3 shows methods of terminating the unused pins for ML610Q101/ML610Q102. Table 3 Pin RESET_N TEST PA0 to PA2 PB0 to PB7 VPP Termination of Unused Pins Recommended pin termination Open Open Open Open Open Note: It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. 10/21 FEDL610Q101 -01 ML610Q101/ML610Q102 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (VSS = 0V) Parameter Symbol Condition Rating Unit Power supply voltage 1 VDD Ta = 25C -0.3 to +7.0 V Power supply voltage 2 VPP Ta = 25C -0.3 to +9.5 V Input voltage VIN Ta = 25C -0.3 to VDD+0.3 V Output voltage VOUT Ta = 25C -0.3 to VDD+0.3 V Output current 1 IOUT1 Ta = 25C -12 to +11 mA Power dissipation PD Ta = 25C 0.5 mW Storage temperature TSTG -55 to +150 C RECOMMENDED OPERATING CONDITIONS (VSS = 0V) Parameter Symbol Condition Range Unit Operating temperature TOP -40 to +85 C Operating voltage VDD 2.7 to 5.5 V Operating frequency (CPU) fOP VDD = 2.7V to 5.5V 30k to 8.4M Hz OPERATING CONDITIONS OF FLASH MEMORY (VSS=0V) Parameter Operating temperature Operating voltage Rewrite counts 1 Data retention* Symbol Condition TOP VDD VPP CEP YDR At write/erase At write/erase At write/erase Min. 0 4.5 7.7 10 Rating Typ. Max. +40 5.5 8.3 80 Unit C V cycles years *1 : However, please keep active time of the flash memory from exceeding ten years. Vpp pin has internal pull-down resistor. 11/21 FEDL610Q101 -01 ML610Q101/ML610Q102 DC CHARACTERISTICS (1/4) Parameter (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +85C, unless otherwise specified) Measuring Rating Condition Unit circuit Min. Typ. Max. Symbol Low-speed RC oscillation frequency fRCL Ta = 25C 31 Ta = 25C 1 PLL oscillation frequency* Ta = -10 to +85C fPLL 16.384 16.384 34 Typ. +1% Typ. +2% Typ. +2.5% 0.4 10 TRST Typ. -2.5% 100 TNRST TPOR Ta = -40 to +85C Reset pulse width Reset noise elimination pulse width Power-on reset activation power rise time Typ. -1% Typ. -2% 32.768 16.384 kHz MHz 1 s ms *1 : 1024 clock average. CPU clk is fPLL /2 max. RESET VDD 0.9*VDD 0.3*VDD RESET_N 0.3*VDD PRST 0.3*VDD PRST RESET_N pin reset 0.9*VDD VDD 0.1*VDD TPOR Power on reset 12/21 FEDL610Q101 -01 ML610Q101/ML610Q102 DC CHARACTERISTICS (2/4) Parameter (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +85C, unless otherwise specified) Measuring Rating Condition Unit circuit Min. Typ. Max. Symbol Typ -3.0 % Typ. -5.0 % Typ. -3.0 % Typ. -5.0 % Typ -3.0 % Typ -5.0 % 3.625 0.1 VDD -1.5 Ta=25C , VDD = 5.0V 10 20 30 VDD = 5.0V 5 20 35 Ta=25C , VDD = 5.0V 7 Ta=25C -25 25 -50 50 1 30 Ta=25C , VDD=fall VVLS0F VDD=fall Ta=25C , VDD=rise VLS Judgment voltage VVLS0R VDD=rise VLS0=0 Ta=25C VLS0=1 VVLS1 VLS0=0 Comparator0 In-phase input voltage range VCMR Comparator0 hysteresis VHYSP Comparator0 Input offset voltage Comparator Referencevoltage error*3 Supply current 1 Supply current 2 VCMOF VCMREF VLS0=1 IDD1 CPU: In STOP state. Low-speed/high-speed oscillation: stopped. IDD2 CPU: In 32.768kHz operating 1 state.* High-speed oscillation: Stopped. Ta=-40 to +85C 2.85 2.85 2.92 Typ +3.0 % Typ. +5.0 % Typ. +3.0 % Typ. 2.92 3.295 3.625 3.295 V 1 +5.0 % Typ +3.0 % Typ +5.0 % V 4 mV A 1 Ta=-40 to +85C 3.7 6 mA *1 : LTBC and WDT are operating ,and significant bits of BLKCON0 to BLKCON4 registers are all "1". *2 : When the CPU operating rate is 100%. Minimum instruction execution time: Approx 0.122 s (at 8.192MHz system clock) *3 :Comparator input offset voltage is included. 13/21 FEDL610Q101 -01 ML610Q101/ML610Q102 DC CHARACTERISTICS (3/4) Parameter Symbol (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +85C, unless otherwise specified) Rating Measuring Condition Unit circuit Min. Typ. Max. VDD -0.7 IOL1 = +8.5mA, VDD = 4.5V * 0.6 IOOH VOH = VDD (in high-impedance state) +1 IOOL VOL = VSS (in high-impedance state) -1 IIH1 IIL1 IIH1 IIL1 VIH1 = VDD VIL1 = VSS, VDD = 5.0V VIH1 = VDD = 5.0V VIL1 = VSS VIH2 = VDD = 5.0V (when pulled-down) VIL2 = VSS, VDD=5.0V (when pulled-up) -650 20 -1 -500 115 1 -350 200 20 115 200 -200 -100 -20 VOH IOH1 = -3.0mA, VDD = 4.5V *1 VOL Output voltage Output leakage Input current 1 (RESET_N) Input current 1 (TEST) Input current 2 (PA0-PA2) (PB0-PB7) 1 IIH2 IIL2 V 2 A 3 A 4 1 * : When the one terminal output state. DC CHARACTERISTICS (4/4) Parameter Input voltage 1 (RESET_N) (TEST) (PA0 to PA2) (PB0,to PB7) Input pin capacitance (PA0 to PA2) (PB0 to PB7) Symbol VIH1 (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +85C, unless otherwise specified) Rating Measuring Condition Unit circuit Min. Typ. Max. 0.7 xVDD VDD VIL1 0 0.3 xVDD CIN f = 10kHz Ta = 25C 20 V 2 pF 14/21 FEDL610Q101 -01 ML610Q101/ML610Q102 MEASURING CIRCUITS MEASURING CIRCUIT 1 VSS VDD A CV1F CV MEASURING CIRCUIT 2 (*2) VIL Input pins (*1) Output pins VIH VDD V Current load VSS *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. 15/21 FEDL610Q101 -01 ML610Q101/ML610Q102 MEASURING CIRCUIT 3 (*2) VIL Input pins (*1) Output pins VIH VDD A VSS *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. MEASURING CIRCUIT 4 Input pins A Output pins (*3) VDD VSS *3: Measured at the specified output pins. 16/21 FEDL610Q101 -01 ML610Q101/ML610Q102 AC CHARACTERISTICS (External Interrupt) Parameter Symbol External interrupt disable period TNUL (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +85C, unless otherwise specified) Rating Condition Unit Min. Typ. Max. Interrupt: Enabled (MIE = 1), 3.5 x 2.5 x s CPU: NOP operation sysclk sysclk System clock: 32.768kHz PA0 to PA2, PB0 to PB1 (Rising-edge interrupt) tNUL PA0 to PA2, PB0 to PB1 (Falling-edge interrupt) tNUL PA0 to PA2, PB0 to PB1 P00 ,P01,PB0 - PB2 (Both-edge interrupt) tNUL 17/21 FEDL610Q101 -01 ML610Q101/ML610Q102 Electrical Characteristics of Successive Approximation Type A/D Converter Parameter Resolution Integral non-linearity error Differential non-linearity error Zero-scale error Full-scale error Conversion time Symbol n INL DNL VOFF FSE tCONV (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +85C, unless otherwise specified) Rating Condition Unit Min. Typ. Max. 10 bit RI5k, HSCLK=8.192MHz -4 +4 RI5k, HSCLK=8.192MHz -3 +3 LSB RI5k, HSCLK=8.192MHz -4 +4 RI5k, HSCLK=8.192MHz -4 +4 102 /CH : fPLL/4 VDD A - 10F Analog input RI5k + 0.1F AIN0 to AIN7 VSS 18/21 FEDL610Q101 -01 ML610Q101/ML610Q102 PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 19/21 FEDL610Q101 -01 ML610Q101/ML610Q102 REVISION HISTORY Document No. Date FEDL610Q101-1 Jan,23,2013 Page Previous Current Edition Edition - - Description Final edition 1 20/21 FEDL610Q101 -01 ML610Q101/ML610Q102 NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LAPIS Semiconductor upon request. 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Copyright 2013 LAPIS Semiconductor Co., Ltd. 21/21 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ROHM Semiconductor: ML610Q101-NNNMBZ0ATL ML610Q102-NNNMBZ0ATL ML610Q101-NNNGDZ0ANL ML610Q102-NNNGDZ0ANL ML610Q102 reference board