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Low Noise/Low Power/SPI Bus/256 Taps
X9250
Quad Digitally Controlled Potentiometers (XDCP
™
)
FEATURES
• Four potentiometers in one package
• 256 resistor taps/pot–0.4% resolution
• SPI serial interface
• Wiper resistance, 40
Ω
typical @ V
CC
= 5V
• Four nonvolatile data registers for each pot
• Nonvolatile storage of wiper position
• Standby current < 5µA max (total package)
• Power supplies
—V
CC
= 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• 100K
Ω
, 50K
Ω
total pot resistance
• High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention – 100 years
• 24-lead SOIC, 24-lead TSSOP, 24-lead CSP (Chip
Scale Package)
• Dual supply version of X9251
DESCRIPTION
The X9250 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to
the wiper terminal through switches. The position of
the wiper on the arra y is controlled b y the user through
the SPI bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and 4 nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power
up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments , and signal processing.
BLOCK DIAGRAM
R0R1
R2R3
Wiper
Counter
Register
(WCR)
Resistor
Array
VH1/RH1
VL1/RL1
R0R1
R2R3
Wiper
Counter
Register
(WCR)
Interface
and
Control
Circuitry
CS
SCK
A0
A1
VH0/RH0
VL0/RL0
Data
8
VW0/RW0
VW1/RW1
SO
SI
R0R1
R2R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW2/RW2
R0R1
R2R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 3
VH3/RH3
VL3/RH3
VW3/RW3
Pot1
HOLD
WP
Pot 0
VCC
VSS
V+
V-
A
PPLICATION
N
OTE
A V A I L A B L E
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
X9250
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PIN DESCRIPTIONS
Serial Output (SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the f alling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial cloc k.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9250.
Chip Select (CS)
When CS is HIGH, the X9250 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9250, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Device Address (A
0
–
A
1
)
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9250. A maximum of 4 devices may occupy the
SPI serial bus.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
–V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
–V
L3
/R
L3
)
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer .
V
W
/R
W
(V
W0
/R
W0
–V
W3
/R
W3
)
The wiper pins are equivalent to the wiper ter minal of
a mechanical potentiometer .
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
S0
A0
VW3/RW3
V+
VCC
VL0/RL0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
HOLD
SCK
VL2/RL2
VH2/RL2
VW2/RW2
V–
VSS
VW1/RW1
VH1/RH1
VL1/RL1
SOIC/TSSOP
X9250
VH3/RH3
14
13
11
12
VL3/RL3
VH0/RH0
VW0/RW0
CS A1
SI
WP
2 3 4
A
B
C
D
E
F
Top View–Bumps Down
RW0
RL0
V+
A0
HOLD
RL1
VCC
RL3
RW3
SO
SI RW1
SCK RL2
WP
V-
RH0 RH1
RH3 RH2
VSS
RW2
CS A1
1 CSP
X9250
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PIN NAMES
DEVICE DESCRIPTION
Serial Interface
The X9250 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9250 is comprised of four resistor arrays. Each
arra y contains 255 discrete resistiv e segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within each individual array only one
s witch ma y be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8 bits of the WCR are decoded
to select, and enable , one of 256 s witches.
Wiper Counter Register (WCR)
The X9250 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of 256 switches
along its resistor array. The contents of the WCR can
be altered in f our w ays: it ma y be written directly by the
host via the write Wiper Counter Register instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated Data Registers
via the XFR Data Register or Global XFR Data
Register instructions (parallel load); it can be modified
one step at a time by the increment/decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon po wer-up .
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9250 is powered-
down. Although the register is automatically loaded
with the value in R0 upon power-up, this may be
diff erent from the v alue present at power-do wn.
Data Registers
Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms .
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user pref erence data.
Data Register Detail
Symbol Description
SCK Serial Clock
SI, SO Serial Data
A0-A1Device Address
VH0/RH0–VH3/RH3,
VL0/RL0–VL3/RL3 Potentiometer Pins
(terminal equivalent)
VW0/RW0–VW3/RW3 Potentiometer Pins
(wiper equivalent)
WP Hardware Write Protection
V+,V- Analog Supplies
VCC System Supply Voltage
VSS System Ground
NC No Connection
(MSB) (LSB)
D7 D6 D5 D4 D3 D2 D1 D0
NV NV NV NV NV NV NV NV
X9250
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Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9250 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9250 this is fix ed as 0101[B] (ref er to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0-A1 input pins.
The X9250 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9250 to successfully
continue the command sequence. The A0–A1 inputs
can be activ ely driven b y CMOS input signals or tied to
VCC or VSS.
The remaining two bits in the sla ve b yte must be set to 0.
Figure 2. Identification Byte Format
Instruction Byte
The next byte sent to the X9250 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
f ormat is shown below in Figure 3.
Figure 3. Instruction Byte Format
100
0 0 A1 A0
Device Type
Identifier
Device Address
1
I1I2I3 I0 R1 R0 P1 P0
Pot Select
Register
Select
Instructions
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
From Interface
Circuitry Register 0 Register 1
Register 2 Register 3
Serial
Bus
Input
Parallel
Input
Counter
Register
Inc/Dec
Logic
UP/DN
CLK
Modified SCK
UP/DN
VH/RH
VL/RL
VW/RW
88
C
o
u
n
t
e
r
D
e
c
o
d
e
If WCR = 00[H] then VW/RW = VL/RL
If WCR = FF[H] then VW/RW = VH/RH
Wiper
(One of Four Arrays)
(WCR)
Bus
X9250
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The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
(P1 and P0) selects which one of the four
potentiometers is to be aff ected by the instruction.
Four of the ten instr uctions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
– Global XFR Data Register to Wiper Counter Register—
This transfers the contents of all specified Data Reg-
isters to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data Register —
This transfers the contents of all Wiper Counter Reg-
isters to the specified associated Data Registers.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by tWRL. A transfer from
the WCR (current wiper position), to a Data Register is
a write to nonvolatile memor y and takes a minimum of
tWR to complete. The tr ansf er can occur betw een one of
the four potentiometers and one of its associated
registers; or it may occur globally, where the transfer
occurs between all potentiometers and one associated
register.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9250; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register . These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
–Write Wiper Counter Register—change current wiper
position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
–Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move
one resistor segment towards the VH/RH terminal.
Similarly, for each SCK clock pulse while SI is LOW, the
selected wiper will move one resistor segment towards
the VL/RL terminal. A detailed illustration of the sequence
and timing for this operation are shown in Figure 7 and
Figure 8.
X9250
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Figure 4. Two-Byte Instruction Sequence
Figure 5. Three-Byte Instruction Sequence (Write)
Figure 6. Three-Byte Instruction Sequence (Read)
Figure 7. Increment/Decrement Instruction Sequence
010100A1A0 I3 I2 I1 I0 R1 R0 P1 P0
SCK
SI
CS
0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0
SCL
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0
SCL
SI
CS
00
S0
D7 D6 D5 D4 D3 D2 D1 D0
Don’t Care
010100A1A0 I3 I2 I1 I0 0 P1 P0
SCK
SI
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
CS
X9250
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Figure 8. Increment/Decrement Timing Limits
Table 1. Instruction Set
Instruction Instruction Set OperationI3I2I1I0R1R0P1P0
Read Wiper Counter
Register 100100P
1P0Read the contents of the Wiper Counter
Register pointed to by P1-P0
Write Wiper Counter
Register 101000P
1P0Write new value to the Wiper Counter
Register pointed to by P1-P0
Read Data Register 1 0 1 1 R1R0P1P0Read the contents of the Data Register
pointed to by P1-P0 and R1–R0
Write Data Register 1 1 0 0 R1R0P1P0Write new value to the Data Register pointed
to by P1-P0 and R1–R0
XFR Data Register to
Wiper Counter Register 1101R
1R0P1P0Transfer the contents of the Data Register
pointed to by R1–R0 to the Wiper Counter
Register pointed to b y P1-P0
XFR Wiper Counter
Register to Data Register 1110R
1R0P1P0Transfer the contents of the Wiper Counter
Register pointed to by P 1-P0 to the Register
pointed to by R1–R0
Global XFR Data Register
to Wiper Counter Register 0001R
1R00 0 Transfer the contents of the Data Registers
pointed to by R1–R0 of all four pots to their
respective Wiper Counter Register
Global XFR Wiper Counter
Register to Data Register 1000R
1R00 0 Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R1–R0 of all four pots
Increment/Decrement
Wiper Counter Register 001000P
1P0Enable Increment/decrement of the Wiper
Counter Register pointed to by P1-P0
Read Status (WIP bit) 0 1 0 1 0 0 0 1 Read the status of the internal write cycle,
by checking the WIP bit.
SCK
SI
VW/RW
INC/DEC CMD Issued
tWRID
Voltage Out
X9250
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Instruction Format
Notes: (1) “A1 ~ A0”: stands f or the de vice addresses sent b y the master.
(2) WPx ref ers to wiper position data in the Counter Register
(2) “I”: stands f or the increment oper ation, SI held HIGH during active SCK phase (high).
(3) “D”: stands f or the decrement oper ation, SI held LO W during active SCK phase (high).
Read Wiper Counter Register(WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode WCR
addresses wiper position
(sent by X9250 on SO) CS
Rising
Edge
010100A
1A
0100100P
1P
0W
P
7
W
P
6
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode WCR
addresses Data Byte
(sent by Host on SI) CS
Rising
Edge
010100A
1A
0101000P
1P
0W
P
7
W
P
6
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode DR and WCR
addresses Data Byte
(sent by X9250 on SO) CS
Rising
Edge
010100A
1A
01011R
1R
0P
1P
0W
P
7
W
P
6
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode DR and WCR
addresses Data Byte
(sent by host on SI) CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A
1A
01100R
1R
0P
1P
0W
P
7
W
P
6
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode DR and WCR
addresses CS
Rising
Edge
010100A
1A
01101R
1R
0P
1P
0
X9250
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Transfer Wiper Counter Register (WCR) to Data Register (DR)
Increment/Decrement Wiper Counter Register (WCR)
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Read Status
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode DR and WCR
addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A
1A
01110R
1R
0P
1P
0
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode WCR
addresses increment/decrement
(sent by master on SI) CS
Rising
Edge
010100A
1A
00010XXP
1P
0I/DI/D....I/DI/D
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode DR
addresses CS
Rising
Edge
010100A
1A
00001R
1R
000
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode DR
addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A
1A
01000R
1R
000
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode Data Byte
(sent by X9250 on SO) CS
Rising
Edge
010100A
1A
0010100010000000W
I
P
X9250
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ABSOLUTE MAXIMUM RATINGS
Temperature under bias........................–65 to +135°C
Storage temperature.............................–65 to +150°C
Voltage on SCK, SCL or any address input
with respect to V SS................................. –1V to +7V
Voltage on V+ (ref erenced to VSS).........................10V
Voltage on V- (ref erenced to VSS)........................ -10V
(V+) – (V-)..............................................................12V
Any VH/RH...............................................................V+
Any VL/RL.................................................................V-
Lead temperature (soldering, 10 seconds)........300°C
IW (10 seconds)................................................±15mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Device Supply Voltage (VCC) Limits
X9250 5V ±10%
X9250-2.7 2.7V to 5.5V
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer .
(2) Relative linearity is utilized to determine the actual change in voltage betw een two successiv e tap positions when used as a potenti-
ometer . It is a measure of the error in step size.
(3) MI = R T O T/255 or (VH/RH–VL/RL)/255, single pot
(4) Individual arra y resolutions.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Unit
End to end resistance tolerance ±20 %
Power rating 50 mW 25°C, each pot
IW Wiper current ±7.5 mA
RWWiper resistance 150 250 ΩWiper current = ± 1mA
Vv+ Voltage on V+ pin X9250 +4.5 +5.5 V
X9250-2.7 +2.7 +5.5
Vv- Voltage on V- pin X9250 -5.5 -4.5 V
X9250-2.7 -5.5 -2.7
VTERM Voltage on any VH/RH or VL/RL pin V- V+ V
Noise -120 dBV Ref: 1kHz
Resolution (4) 0.6 %
Absolute linearity (1) ±1 MI(3) Vw(n)(actual)–Vw(n)(expected)
Relative linearity (2) ±0.6 MI(3) Vw(n + 1)–[Vw(n) + MI]
Temperature coefficient of RTOTAL ±300 ppm/°C
Ratiometric Temperature
Coefficient ±20 ppm/°C
CH/CL/CWPotentiometer Capacitances 10/10/25 pF See Circuit #3
X9250
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER UP AND DOWN REQUIREMENT
The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach
their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than
V+ and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach
their final v alue. The VCC ramp rate spec is alwa ys in effect.
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can
be issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Unit
ICC1 VCC supply current
(active) 400 µA fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ICC2 VCC supply current
(nonvolatile write) 1mAf
SCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB VCC current (standby) 5 µA SCK = SI = VSS, Addr. = VSS
ILI Input leakage current 10 µA VIN = VSS to VCC
ILO Output leakage current 10 µA VOUT = VSS to VCC
VIH Input HIGH voltage VCC x 0.7 VCC + 0.1 V
VIL Input LOW voltage –0.5 VCC x 0.3 V
VOL Output LOW voltage 0.4 V IOL = 3mA
Parameter Min. Unit
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 Years
Symbol Test Max. Unit Test Conditions
COUT(5) Output capacitance (SO) 8 pF VOUT = 0V
CIN(5) Input capacitance (A0, A1, SI, and SCK, CS) 6 pF VIN = 0V
Symbol Parameter Min. Max. Unit
tPUR(6) Power-up to initiation of read operation 1 ms
tPUW(6) Power-up to initiation of write operation 5 ms
tR VCC(7) VCC power up ramp rate 0.2 50 V/msec
A.C. TEST CONDITIONS
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
X9250
Characteristics subject to change without notice. 12 of 21
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AC TIMING
Symbol Parameter Min. Max. Unit
fSCK SSI/SPI clock frequency 2.0 MHz
tCYC SSI/SPI clock cycle time 500 ns
tWH SSI/SPI clock high time 200 ns
tWL SSI/SPI clock low time 200 ns
tLEAD Lead time 250 ns
tLAG Lag time 250 ns
tSU SI, SCK, HOLD and CS input setup time 50 ns
tHSI, SCK, HOLD and CS input hold time 75 ns
tRI SI, SCK, HOLD and CS input rise time 2 µs
tFI SI, SCK, HOLD and CS input fall time 2 µs
tDIS SO output disable Time 0 500 ns
tVSO output valid time 100 ns
tHO SO output hold time 0 ns
tRO SO output rise time 50 ns
tFO SO output fall time 50 ns
tHOLD HOLD time 400 ns
tHSU HOLD setup time 100 ns
tHH HOLD hold time 100 ns
tHZ HOLD low to output in high Z 100 ns
tLZ HOLD high to output in low Z 100 ns
TINoise suppression time constant at SI, SCK, HOLD and CS inputs TBD ns
tCS CS deselect time 2 µs
tWPASU WP, A0 and A1 setup time 0 ns
tWPAH WP, A0 and A1 hold time 0 ns
Circuit #3 SPICE Macro Model EQUIVALENT A.C. LOAD CIRCUIT
10pF
RH
RTOTAL
CH
25pF
CW
CL
10pF
RW
RL
5V
1533Ω
100pF
SDA Output
2.7V
100pF
X9250
Characteristics subject to change without notice. 13 of 21
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HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
SYMBOL TABLE
TIMING DIAGRAMS
Input Timing
Symbol Parameter Typ. Max. Unit
tWR High-voltage write cycle time (store instructions) 5 10 ms
Symbol Parameter Min. Max. Unit
tWRPO Wiper response time after the third (last) power supply is stable 10 µs
tWRL Wiper response time after instruction issued (all load instructions) 10 µs
tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruc-
tion) 40 µs
WAVEFORM INPUTS OUTPUTS
Must be
steady Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
...
CS
SCK
SI
SO
MSB LSB
High Impedance
tLEAD
tH
tSU tFI
tCS
tLAG
tCYC
tWL ...
tRI
tWH
X9250
Characteristics subject to change without notice. 14 of 21
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Output Timing
Hold Timing
XDCP Timing (for all Load Instructions)
...
CS
SCK
SO
SI ADDR
MSB LSB
tDIS
tHO
tV...
...
CS
SCK
SO
SI
HOLD
tHSU tHH
tLZ
tHZ
tHOLD
tRO tFO
...
CS
SCK
SI MSB LSB
VWx
tWRL
...
SO High Impedance
X9250
Characteristics subject to change without notice. 15 of 21
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XDCP Timing (for Increment/Decrement Instruction)
Write Protect and Device Address Pins Timing
...
CS
SCK
SO
SI ADDR
tWRID
High Impedance
VWx
...
Inc/Dec Inc/Dec
...
CS
WP
A0
A1
tWPASU tWPAH
(Any Instruction)
X9250
Characteristics subject to change without notice. 16 of 21
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APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
VR
VW/RW
+VR
I
Three terminal Potentiometer;
Variable voltage divider Two terminal Variable Resistor;
Variable current
Noninverting Amplifier Voltage Regulator
Offset Voltage Adjustment Comparator with Hysterisis
+
–
VSVO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2) VO(max)
VLL = {R1/(R1+R2) VO(min)
100KΩ
10KΩ10KΩ
10KΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
X9250
Characteristics subject to change without notice. 17 of 21
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Application Circuits (continued)
Attenuator Filter
Inverting Amplifier Equivalent L-R Circuit
+
–
VSVO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1
fc = 1/(2πRC)
+
–
VS
VO
R2
R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
R2
R4R1 = R2 = R3 = R4 = 10kΩ
+
–
VS
R2
R1
R
C
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
VO
X9250
Characteristics subject to change without notice. 18 of 21
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PACKAGING INFORMATION
f
jb
ad
e
Top View (Sample Marking) Bottom View (Bumped Side)
Side View
e
A1A4
C2
A3
B4 B3 B1
C4 C1
D4 D2 D1
E4 E2 E1
F1
F4 F3 F2
E3
D3
C3
B2
A2
c
k
l
m
Side View
24-Bump Chip Scale Package (CSP B24)
Package Outline Drawing
9250UA
YWW I
Lot#
Package Dimensions
Symbol Millimeters
Min Nominal Max
Package Width a 2.771 2.801 2.831
Package Length b 4.549 4.579 4.609
Package Height c 0.644 0.677 0.710
Body Thickness d 0.444 0.457 0.470
Ball Height e 0.200 0.220 0.240
Ball Diameter f 0.300 0.320 0.340
Ball Pitch – Width j 0.5
Ball Pitch – Length k 0.5
Ball to Edge Spacing – Width l 0.626 0.651 0.676
Ball to Edge Spacing – Length m 1.015 1.040 1.065
Ball Matrix:
4321
ARL1 A1 CS RW0
BRW1 SI WP RL0
CVSS RH1 RH0 VCC
DV- RH2 RH3 V+
ERW2 HOLD SO RL3
FRL2 SCK A0 RW3
X9250
Characteristics subject to change without notice. 19 of 21
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PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
24-Lead Plastic, TSSOP, Package Code V24
.169 (4.3)
.177 (4.5).252 (6.4) BSC
.026 (.65) BSC
.303 (7.70)
.311 (7.90)
.002 (.06)
.005 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
See Detail “A”
.031 (.80)
.041 (1.05)
.010 (.25)
.020 (.50)
.030 (.75)
Gage Plane
Seating Plane
Detail A (20X)
(4.16)(7.72)
(1.78)
(0.42) (0.65)
ALL MEASUREMENTS ARE TYPICAL
0°–8°
X9250
Characteristics subject to change without notice. 20 of 21
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PACKAGING INFORMATION
0.290 (7.37)
0.299 (7.60) 0.393 (10.00)
0.420 (10.65)
0.014 (0.35)
0.020 (0.50)
Pin 1
Pin 1 Index
0.050 (1.27)
0.598 (15.20)
0.610 (15.49)
0.003 (0.10)
0.012 (0.30)
0.092 (2.35)
0.105 (2.65)
(4X) 7°
24-Lead Plastic, SOIC, Package Code S24
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.420"
0.050" Typical
0.050"
Typical
0.030" Typical
24 Places
FOOTPRINT
0.010 (0.25)
0.020 (0.50)
0.015 (0.40)
0.050 (1.27)
0.009 (0.22)
0.013 (0.33)
0° – 8°
X 45°
X9250
Characteristics subject to change without notice. 21 of 21
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LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutor y, implied, or by description regarding the infor mation set for th herein or regarding the freedom of the described devices from patent infringement.
Xicor , Inc. makes no warranty of merchantability or fitness for any purpose. Xicor , Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor , Inc. assumes no responsibility f or the use of any circuitry other than circuitry embodied in a Xicor , Inc. product. No other circuits , patents, or licenses are implied.
COPYRIGHTS AND TRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life , system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up f eatures to pre v ent such an occurrence .
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonab ly expected to result in a significant injury to the user .
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support de vice or system, or to aff ect its saf ety or eff ectiv eness.
©Xicor, Inc. 2003 Patents Pending
Ordering Information
Device VCC Limits
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial =0°C to +70°C
I = Industrial = –40°C to +85°C
Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
B24 = 24-Lead CSP
P otentiometer Or ganization
T = 100KΩ
U= 50KΩ
X9250 P T VY
S & V Package Marking
Line #1 (Blank)
Line #2 (Part Number)
Line #3 (Date Code) (*)
Line #4 (Blank) = F 2.7V 0 to 70°C
G 2.7V -40 to +85°C
I 5V -40 to +85°C
