CY7C1061GN30
16-Mbit (1 M words × 16 bit) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-93680 Rev. *A Revised September 11, 2015
16-Mbit (1 M words × 16 b it) Static RAM
Features
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 90 mA at 100 MHz
■Low CMOS standby current
❐ISB2 = 20 mA (typ)
■Operating voltages of 2.2 V to 3.6 V
■1.0 V data retention
■Automatic power down when deselected
■TTL compatible inputs and outputs
■Easy memory expansion with CE1 and CE2 features
■Available in Pb-free 54-pin TSOP II, and 48-ball VFBGA
packages
■Offered in dual Chip Enable options
Functional Description
The CY7C1061GN30 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A19). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 12
for a complete description of Read and Write modes.
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE1 HIGH/CE2
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH, and WE LOW).
15
16
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
1M x 16
ARRAY
A0
A12
A14
A13
A
A
A17
A18
A10
A11
I/O0 – I/O7
OE
I/O8 – I/O15
CE1
WE
BLE
BHE
A9
A19
CE2
Logic Block Diagram
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 2 of 18
Contents
Selection Guide ................................................................3
Pin Configurations ...........................................................3
Maximum Ratings .............................................................5
Operating Range ............................................................... 5
DC Electrical Characteristics ..........................................5
Capacitance ......................................................................6
Thermal Resistance ..........................................................6
AC Test Loads and Waveforms .......................................6
Data Retention Characteristics ....................................... 7
Over the Operating Range ...............................................7
Data Retention Waveform ................................................ 7
AC Switching Characteristics .........................................8
Switching Waveforms ...................................................... 9
Truth Table ...................................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 3 of 18
Selection Guide
Description -10 Unit
Maximum access time 10 ns
Maximum operating current 110 mA
Maximum CMOS standby current 30 mA
Pin Configurations
Figure 1. 48-ball VFBGA (8 × 9.5 × 1 mm) Dual Chip Enable pinout (Top View) [1]
WE
A
11
A
10
A
6
A
0
A
3
CE
1
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
A
7
I/O
0
BHE
CE
2
A
17
A
2
A
1
BLE
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
A
18
A
19
326
5
41
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
Note
1. NC pins are not connected internally to the die.
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 4 of 18
Figure 2. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) pinout (Top View) [2]
Pin Configurations (continued)
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
I/O
11
18
17
20
19
23
28
25
24
22
21
27
26
V
SS
I/O
10
I/O
12
V
CC
I/O
13
I/O
14
V
SS
A
16
A
17
A
11
A
12
A
13
A
14
I/O
0
A
15
I/O
7
I/O
9
V
CC
I/O
8
I/O
15
A
19
A
4
A
3
A
2
A
1
CE
1
V
CC
WE
CE
2
BLE
NC
V
SS
OE
A
8
A
7
A
6
A
5
A
0
NC
A
9
BHE
A
10
10
A
18
46
45
47
50
49
48
51
54
53
52
I/O
2
I/O
1
I/O
3
V
SS
V
CC
V
SS
I/O
6
I/O
5
V
CC
I/O
4
Note
2. NC pins are not connected internally to the die.
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 5 of 18
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature
with Power Applied .................................. –55 C to +125 C
Supply Voltage on
VCC relative to GND [3] ....................... –0.5 V to VCC + 0.5 V
DC Voltage Applied to Outputs
in High Z State [3] ................................ –0.5 V to VCC + 0.5 V
DC Input Voltage [3] ............................ –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................. >2001 V
Latch Up Current .................................................... >200 mA
Operating Range
Range Ambient Temperature VCC
Industrial –40 C to +85 C 2.2 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions -10 Unit
Min Typ [4] Max
VOH Output HIGH
voltage
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA 2.0 – – V
2.7 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.2 – –
VOL Output LOW
voltage
2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4 V
2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4
VIH Input HIGH
voltage [3] 2.2 V to 2.7 V – 2.0 – VCC + 0.3 V
2.7 V to 3.6 V – 2.0 – VCC + 0.3
VIL Input LOW
voltage [3] 2.2 V to 2.7 V – –0.3 – 0.6 V
2.7 V to 3.6 V – –0.3 – 0.8
IIX Input leakage current GND < VI < VCC –1 – +1 A
IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 – +1 A
ICC VCC operating supply current VCC = Max,
f = fMAX = 1/tRC,
IOUT = 0 mA,
CMOS levels
– 90110mA
ISB1 Automatic CE power down
current – TTL inputs
Max VCC,
CE1 > VIH, CE2 < VIL,
VIN > VIH or VIN < VIL,
f = fMAX
––40mA
ISB2 Automatic CE power down
current – CMOS inputs
Max VCC,
CE1 > VCC – 0.3 V, CE2 < 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V,
f = 0
–2030mA
Note
3. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 2 ns.
4. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 3 V (for a VCC range of 2.2 V–3.6 V), TA = 25 °C.
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 6 of 18
Capacitance
Parameter [5] Description Test Conditions 54-pin TSOP II 48-ball VFBGA Unit
CIN Input capacitance TA = 25 C, f = 1 MHz,
VCC = 3.3 V
10 10 pF
COUT I/O capacitance 10 10 pF
Thermal Resistance
Parameter [5] Description Test Conditions 54-pin TSOP II 48-ball VFBGA Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, four
layer printed circuit board
93.63 31.50 C/W
JC Thermal resistance
(junction to case)
21.58 15.75 C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [6]
90%
10%
3.0 V
GND
90%
10%
All Input Pulses
3.3 V
Output
5 pF*
Including
JIG and
Scope (b)
R1 317
R2
351
Rise Time: Fall Time:
> 1 V/ns
(c)
Output
50
Z
0
= 50
V
TH
= 1.5 V
30 pF*
* Capacitive Load Consists
of all Components of the
Test Environment
High-Z Characteristics:
(a)
> 1 V/ns
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating
VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 1.0 V) voltage.
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 7 of 18
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Max Unit
VDR VCC for data retention – 1 – V
ICCDR Data retention current VCC = 1.2 V,
CE1 > VCC – 0.2 V, CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
–30mA
tCDR [7] Chip deselect to data retention
time
–0–ns
tR[8] Operation recovery time – 10 – ns
Data Retention Waveform
Figure 4. Data Retention Waveform [9]
3.0 V3.0 V
tCDR
VDR > 1 V
Data Retention Mode
tR
CE
VCC
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.
9. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 8 of 18
AC Switching Characteristics
Over the Operating Range
Parameter [10] Description -10 Unit
Min Max
Read Cycle
tpower VCC(typical) to the first access [11] 100 – s
tRC Read cycle time 10 – ns
tAA Address to data valid – 10 ns
tOHA Data hold from address change 3 – ns
tACE CE1 LOW/CE2 HIGH to data valid – 10 ns
tDOE OE LOW to data valid – 5 ns
tLZOE OE LOW to low Z [12] 0–ns
tHZOE OE HIGH to high Z [12] –5ns
tLZCE CE1 LOW/CE2 HIGH to low Z [12] 3–ns
tHZCE CE1 HIGH/CE2 LOW to high Z [12] –5ns
tPU CE1 LOW/CE2 HIGH to power-up [13] 0–ns
tPD CE1 HIGH/CE2 LOW to power-down [13] –10ns
tDBE Byte enable to data valid – 5 ns
tLZBE Byte enable to low Z 0 – ns
tHZBE Byte disable to high Z – 6 ns
Write Cycle [14, 15]
tWC Write cycle time 10 – ns
tSCE CE1 LOW/CE2 HIGH to write end 7 – ns
tAW Address setup to write end 7 – ns
tHA Address hold from write end 0–ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 7–ns
tSD Data setup to write end 5 – ns
tHD Data hold from write end 0 – ns
tLZWE WE HIGH to low Z [12,13.] 3–ns
tHZWE WE LOW to high Z [12,13.] –5ns
tBW Byte Enable to End of Write 7–ns
Notes
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use
output loading shown in part (a) of Figure 3 on page 6, unless specified otherwise.
11. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
12. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 6. Transition is measured when output goes into
high impedance
13. These parameters are guaranteed by design and are not tested.
14. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. Chip enables must be active and WE and byte enables must be
LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal
that terminates the write.
15. The minimum write cycle time for Write Cycle No. 2 (WE Controlled, OE LOW) is the sum of tHZWE and tSD.
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 9 of 18
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) [16, 17]
Figure 6. Read Cycle No. 2 (OE Controlled) [17, 18, 19]
Previous Data Valid Data Valid
RC
tAA
tOHA
tRC
Address
Data Out
50%
50%
Data Valid
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
High Impedance
t
HZOE
t
HZBE
t
PD
High
OE
CE
ICC
ISB
Impedance
Address
Data Out
V
CC
Supply
t
DBE
t
LZBE
t
HZCE
BHE,BLE
Current
I
CC
I
SB
Notes
16. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL.
17. WE is HIGH for read cycle.
18. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
19. Address valid before or similar to CE transition LOW.
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 10 of 18
Figure 7. Write Cycle No. 1 (CE Controlled) [20, 21, 22]
Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [20, 21, 22]
Switching Waveforms (continued)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
t
Data I/O
Address
CE
WE
BHE, BLE
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
tSA
tLZWE
tHZWE
Data I/O
Address
CE
WE
BHE,BLE
Notes
20. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
21. Data I/O is high impedance if OE, BHE, and/or BLE = VIH.
22. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 11 of 18
Figure 9. Write Cycle No. 3 (BLE or BHE Controlled) [23]
Switching Waveforms (continued)
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
Data I/O
Address
BHE,BLE
CE
WE
Note
23. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 12 of 18
Truth Table
CE1CE2OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
H X X X X X High Z High Z Power down Standby (ISB)
X L X X X X High Z High Z Power down Standby (ISB)
L H L H L L Data out Data out Read all bits Active (ICC)
L H L H L H Data out High Z Read lower bits only Active (ICC)
L H L H H L High Z Data out Read upper bits only Active (ICC)
L H X L L L Data in Data in Write all bits Active (ICC)
L H X L L H Data in High Z Write lower bits only Active (ICC)
L H X L H L High Z Data in Write upper bits only Active (ICC)
L H H H X X High Z High Z Selected, outputs disabled Active (ICC)
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 13 of 18
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
10 CY7C1061GN30-10ZSXI 51-85160 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) (Pb-free) Industrial
CY7C1061GN30-10BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm) (Pb-free) (Dual Chip Enable)
Temperature Range:
I = Industrial
Pb-free
Package Type: XX = ZS or BV
ZS = 54-pin TSOP II
BV = 48-ball VFBGA (Dual Chip Enable)
Speed: 10 ns
Voltage Range: 30 = 2.2 V to 3.6 V
N = No ECC
Process Technology: G = 65 nm Technology
Data Width: 1 = × 16-bits
Density: 06 = 16-Mbit density
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1 - 10 X706 G I301XXN
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 14 of 18
Package Diagrams
Figure 10. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160
51-85160 *E
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 15 of 18
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
Package Diagrams (continued)
51-85150 *H
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 16 of 18
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE Byte High Enable
BLE Byte Low Enable
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE Output Enable
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
TTL Transistor-Transistor Logic
VFBGA Very Fine-Pitch Ball Grid Array
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
Amicroampere
smicrosecond
mA milliampere
mm millimeter
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 17 of 18
Document History Page
Document Title: CY7C1061GN30, 16-Mbit (1 M words × 16 bit) Static RAM
Document Number: 001-93680
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 4505531 VINI 01/02/2015 New data sheet.
*A 4900408 NILE 09/11/2015 Updated DC Electrical Characteristics:
Updated details in “Test Conditions” column of VOH and VOL parameters.
Updated Ordering Information:
No change in part numbers.
Replaced “51-85178” with “51-85150” in “Package Diagram” column.
Replaced “8 × 9.5 × 1 mm” with “6 × 8 × 1.0 mm” in “Package Type” column.
Updated Package Diagrams:
Removed spec 51-85178 *C.
Added spec 51-85150 *H.
Updated to new template.
Document Number: 001-93680 Rev. *A Revised September 11, 2015 Page 18 of 18
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1061GN30
© Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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