CY7C1061GN30 16-Mbit (1 M words x 16 bit) Static RAM 16-Mbit (1 M words x 16 bit) Static RAM Features Functional Description High speed tAA = 10 ns The CY7C1061GN30 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. Low active power ICC = 90 mA at 100 MHz Low CMOS standby current ISB2 = 20 mA (typ) Operating voltages of 2.2 V to 3.6 V To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). 1.0 V data retention Automatic power down when deselected TTL compatible inputs and outputs Easy memory expansion with CE1 and CE2 features Available in Pb-free 54-pin TSOP II, and 48-ball VFBGA packages Offered in dual Chip Enable options To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See Truth Table on page 12 for a complete description of Read and Write modes. The input or output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE1 HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). Logic Block Diagram SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER 1M x 16 ARRAY I/O0 - I/O7 I/O8 - I/O15 A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 COLUMN DECODER BHE WE OE BLE Cypress Semiconductor Corporation Document Number: 001-93680 Rev. *A * 198 Champion Court * CE2 CE1 San Jose, CA 95134-1709 * 408-943-2600 Revised September 11, 2015 CY7C1061GN30 Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 DC Electrical Characteristics .......................................... 5 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads and Waveforms ....................................... 6 Data Retention Characteristics ....................................... 7 Over the Operating Range ............................................... 7 Data Retention Waveform ................................................ 7 AC Switching Characteristics ......................................... 8 Switching Waveforms ...................................................... 9 Truth Table ...................................................................... 12 Document Number: 001-93680 Rev. *A Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Diagrams .......................................................... 14 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC(R) Solutions ...................................................... 18 Cypress Developer Community ................................. 18 Technical Support ..................................................... 18 Page 2 of 18 CY7C1061GN30 Selection Guide -10 Unit Maximum access time Description 10 ns Maximum operating current 110 mA Maximum CMOS standby current 30 mA Pin Configurations Figure 1. 48-ball VFBGA (8 x 9.5 x 1 mm) Dual Chip Enable pinout (Top View) [1] 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC D VCC I/O12 NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 A19 H Note 1. NC pins are not connected internally to the die. Document Number: 001-93680 Rev. *A Page 3 of 18 CY7C1061GN30 Pin Configurations (continued) Figure 2. 54-pin TSOP II (22.4 x 11.84 x 1.0 mm) pinout (Top View) [2] I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 45 44 I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC OE VSS NC BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 54 53 52 51 50 49 48 47 46 Note 2. NC pins are not connected internally to the die. Document Number: 001-93680 Rev. *A Page 4 of 18 CY7C1061GN30 DC Input Voltage [3] ............................ -0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... -65 C to +150 C Ambient Temperature with Power Applied .................................. -55 C to +125 C Supply Voltage on VCC relative to GND [3] ....................... -0.5 V to VCC + 0.5 V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, Method 3015) .................................. >2001 V Latch Up Current .................................................... >200 mA Operating Range DC Voltage Applied to Outputs in High Z State [3] ................................ -0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Industrial -40 C to +85 C 2.2 V to 3.6 V DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions -10 Min Typ [4] Max VCC = Min, IOH = -0.1 mA 2.0 - - VOH Output HIGH voltage 2.2 V to 2.7 V 2.7 V to 3.6 V VCC = Min, IOH = -4.0 mA 2.2 - - VOL Output LOW voltage 2.2 V to 2.7 V VCC = Min, IOL = 2 mA - - 0.4 2.7 V to 3.6 V VCC = Min, IOL = 8 mA - - 0.4 2.2 V to 2.7 V - 2.0 - VCC + 0.3 2.7 V to 3.6 V - 2.0 - VCC + 0.3 2.2 V to 2.7 V - -0.3 - 0.6 2.7 V to 3.6 V - -0.3 - 0.8 GND < VI < VCC -1 - +1 VIH Input HIGH voltage [3] VIL Input LOW voltage [3] Unit V V V V A IIX Input leakage current IOZ Output leakage current GND < VOUT < VCC, Output disabled -1 - +1 A ICC VCC operating supply current VCC = Max, - 90 110 mA - - 40 mA - 20 30 mA f = fMAX = 1/tRC, IOUT = 0 mA, CMOS levels ISB1 Automatic CE power down current - TTL inputs Max VCC, CE1 > VIH, CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE power down current - CMOS inputs Max VCC, CE1 > VCC - 0.3 V, CE2 < 0.3 V, VIN > VCC - 0.3 V or VIN < 0.3 V, f=0 Note 3. VIL(min) = -2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 2 ns. 4. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 3 V (for a VCC range of 2.2 V-3.6 V), TA = 25 C. Document Number: 001-93680 Rev. *A Page 5 of 18 CY7C1061GN30 Capacitance Parameter [5] Description CIN Input capacitance COUT I/O capacitance Test Conditions 54-pin TSOP II 48-ball VFBGA Unit TA = 25 C, f = 1 MHz, VCC = 3.3 V 10 10 pF 10 10 pF Thermal Resistance Parameter [5] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 54-pin TSOP II 48-ball VFBGA Unit Still air, soldered on a 3 x 4.5 inch, four layer printed circuit board 93.63 31.50 C/W 21.58 15.75 C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [6] High-Z Characteristics: 3.3 V 50 VTH = 1.5 V Output Z0 = 50 Output 30 pF* Including JIG and Scope (b) All Input Pulses 3.0 V GND R2 351 5 pF* (a) * Capacitive Load Consists of all Components of the Test Environment R1 317 90% 90% 10% Rise Time: > 1 V/ns 10% (c) Fall Time: > 1 V/ns Notes 5. Tested initially and after any design or process changes that may affect these parameters. 6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 1.0 V) voltage. Document Number: 001-93680 Rev. *A Page 6 of 18 CY7C1061GN30 Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Max Unit VDR VCC for data retention - 1 - V ICCDR Data retention current VCC = 1.2 V, - 30 mA CE1 > VCC - 0.2 V, CE2 < 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V tCDR [7] tR[8] Chip deselect to data retention time - 0 - ns Operation recovery time - 10 - ns Data Retention Waveform Figure 4. Data Retention Waveform [9] Data Retention Mode VCC 3.0 V VDR > 1 V tCDR 3.0 V tR CE Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. 9. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document Number: 001-93680 Rev. *A Page 7 of 18 CY7C1061GN30 AC Switching Characteristics Over the Operating Range Parameter [10] Description -10 Min Max Unit Read Cycle tpower VCC(typical) to the first access [11] 100 - s tRC Read cycle time 10 - ns tAA Address to data valid - 10 ns tOHA Data hold from address change 3 - ns tACE CE1 LOW/CE2 HIGH to data valid - 10 ns tDOE OE LOW to data valid - 5 ns 0 - ns - 5 ns 3 - ns - 5 ns 0 - ns tLZOE OE LOW to low Z [12] [12] tHZOE OE HIGH to high Z tLZCE CE1 LOW/CE2 HIGH to low Z [12] tHZCE tPU CE1 HIGH/CE2 LOW to high Z [12] CE1 LOW/CE2 HIGH to power-up [13] [13] tPD CE1 HIGH/CE2 LOW to power-down - 10 ns tDBE Byte enable to data valid - 5 ns tLZBE Byte enable to low Z 0 - ns Byte disable to high Z - 6 ns tHZBE Write Cycle [14, 15] tWC Write cycle time 10 - ns tSCE CE1 LOW/CE2 HIGH to write end 7 - ns tAW Address setup to write end 7 - ns tHA Address hold from write end 0 - ns tSA Address setup to write start 0 - ns tPWE WE pulse width 7 - ns tSD Data setup to write end 5 - ns tHD Data hold from write end 0 - ns tLZWE WE HIGH to low Z [12,13.] 3 - ns tHZWE WE LOW to high Z [12,13.] - 5 ns tBW Byte Enable to End of Write 7 - ns Notes 10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use output loading shown in part (a) of Figure 3 on page 6, unless specified otherwise. 11. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 12. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 6. Transition is measured when output goes into high impedance 13. These parameters are guaranteed by design and are not tested. 14. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. Chip enables must be active and WE and byte enables must be LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 15. The minimum write cycle time for Write Cycle No. 2 (WE Controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-93680 Rev. *A Page 8 of 18 CY7C1061GN30 Switching Waveforms Figure 5. Read Cycle No. 1 (Address Transition Controlled) [16, 17] tRC RC Address tAA tOHA Data Out Previous Data Valid Data Valid Figure 6. Read Cycle No. 2 (OE Controlled) [17, 18, 19] Address tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE Data Out High Impedance Data Valid tLZCE VCC Supply Current tHZBE High Impedance tPD tPU 50% 50% IICC CC IISB SB Notes 16. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL. 17. WE is HIGH for read cycle. 18. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 19. Address valid before or similar to CE transition LOW. Document Number: 001-93680 Rev. *A Page 9 of 18 CY7C1061GN30 Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (CE Controlled) [20, 21, 22] tWC Address tSA CE tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD Data I/O Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [20, 21, 22] tWC Address tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD Data I/O tLZWE Notes 20. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 21. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. 22. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 001-93680 Rev. *A Page 10 of 18 CY7C1061GN30 Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (BLE or BHE Controlled) [23] tWC Address tSA tBW BHE, BLE tAW tHA tPWE WE tSCE CE tSD tHD Data I/O Note 23. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document Number: 001-93680 Rev. *A Page 11 of 18 CY7C1061GN30 Truth Table CE1 CE2 OE WE BLE BHE I/O0-I/O7 I/O8-I/O15 Mode Power H X X X X X High Z High Z Power down Standby (ISB) X L X X X X High Z High Z Power down Standby (ISB) L H L H L L Data out Data out Read all bits Active (ICC) L H L H L H Data out High Z Read lower bits only Active (ICC) L H L H H L High Z Data out Read upper bits only Active (ICC) L H X L L L Data in Data in Write all bits Active (ICC) L H X L L H Data in High Z Write lower bits only Active (ICC) L H X L H L High Z Data in Write upper bits only Active (ICC) L H H H X X High Z High Z Selected, outputs disabled Active (ICC) Document Number: 001-93680 Rev. *A Page 12 of 18 CY7C1061GN30 Ordering Information Speed (ns) 10 Package Diagram Ordering Code Package Type CY7C1061GN30-10ZSXI 51-85160 54-pin TSOP II (22.4 x 11.84 x 1.0 mm) (Pb-free) CY7C1061GN30-10BVXI 51-85150 48-ball VFBGA (6 x 8 x 1.0 mm) (Pb-free) (Dual Chip Enable) Operating Range Industrial Ordering Code Definitions CY 7 C 1 06 1 G N 30 - 10 XX X I Temperature Range: I = Industrial Pb-free Package Type: XX = ZS or BV ZS = 54-pin TSOP II BV = 48-ball VFBGA (Dual Chip Enable) Speed: 10 ns Voltage Range: 30 = 2.2 V to 3.6 V N = No ECC Process Technology: G = 65 nm Technology Data Width: 1 = x 16-bits Density: 06 = 16-Mbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-93680 Rev. *A Page 13 of 18 CY7C1061GN30 Package Diagrams Figure 10. 54-pin TSOP II (22.4 x 11.84 x 1.0 mm) Z54-II Package Outline, 51-85160 51-85160 *E Document Number: 001-93680 Rev. *A Page 14 of 18 CY7C1061GN30 Package Diagrams (continued) Figure 11. 48-ball VFBGA (6 x 8 x 1.0 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 001-93680 Rev. *A Page 15 of 18 CY7C1061GN30 Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor A microampere I/O Input/Output s microsecond OE Output Enable mA milliampere SRAM Static Random Access Memory mm millimeter TSOP Thin Small Outline Package ns nanosecond TTL Transistor-Transistor Logic ohm VFBGA Very Fine-Pitch Ball Grid Array % percent WE Write Enable pF picofarad V volt W watt Document Number: 001-93680 Rev. *A Symbol Unit of Measure Page 16 of 18 CY7C1061GN30 Document History Page Document Title: CY7C1061GN30, 16-Mbit (1 M words x 16 bit) Static RAM Document Number: 001-93680 Rev. ECN No. Orig. of Change Submission Date ** 4505531 VINI 01/02/2015 New data sheet. *A 4900408 NILE 09/11/2015 Updated DC Electrical Characteristics: Updated details in "Test Conditions" column of VOH and VOL parameters. Updated Ordering Information: No change in part numbers. Replaced "51-85178" with "51-85150" in "Package Diagram" column. Replaced "8 x 9.5 x 1 mm" with "6 x 8 x 1.0 mm" in "Package Type" column. Updated Package Diagrams: Removed spec 51-85178 *C. Added spec 51-85150 *H. Updated to new template. Document Number: 001-93680 Rev. *A Description of Change Page 17 of 18 CY7C1061GN30 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC(R) Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless (c) Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-93680 Rev. *A Revised September 11, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 18 of 18