N-Channel JFET
Monolithic Dual
SST404 / SST405 / SST406
FEATURES
••Very Low No is e . . . . . . . . . . . . . en < 10 nV/ Hz @ 10Hz
••Lo w Input Bias. . . . . . . . . . . . . . . . . . . . . . . . . . . IG < 2pA
••High Breakdown Vol ta g e. . . . . . . . . . . . . . . . . . . BV > 50V
APPLICATIONS
••Preci si on I nst ru me nta tion
••I n p ut Amplif iers
••Im pedance C onverters
DESCRIPTION
The SST404 Series is a very Low Noise Monolithic
N-Channel JFET Pair in a surface mount SO-8 plastic
package. Designed utilizing Calogic’s proprietary JFET
processing techniques these devices are ideal for front end
ampli fica tion of low level signal s. The low noise, low leakage
and good frequency response are excellent features for
sensitiv e medica l, instrum entat ion an d infrared de signs .
ORDERING INFORMATION
Part Pac ka ge T em perature Range
SST404-6 Plastic SO-8 -55oC to +125oC
NOTE: For Sorted Chips in Carriers, See U401 Series
PIN CONFI G U RAT IONS
LLC
SO-8
TOP VIEW
(1) S1
(2) D1
(3) G1
(4) N/C
N/C (8)
G2 (7)
D2 (6)
S2 (5)
CJ2 PRODUCT MARKI NG
SST404 R04
SST405 R05
SST406 R06
CALOGIC LLC, 237 WHITNEY PLACE, FREMONT, CA 94539, 510-656-2900 PHONE, 510-651-1076 FAX DS068 REV A
SST404 / SST405 / SST406
LLC
ABSOLUTE M AXIMUM R ATING S (TA = 2 5oC unless ot he rwise no te d)
P ar amete r/ Test Con di tio n Symbol Lim it Unit
Gate-Drain V oltage VGD -50 V
Gate-Source V oltage VGS -50 V
Forward Gate Current IG10 mA
Power Dissipation (per side) PD300 mW
(total) 500 mW
Pow er Derat ing (per side) 2 .4 mW / oC
(total) 4 mW/ oC
Oper ating Junc tion Tem peratu re TJ-55 t o 150 oC
Storage Temperature Tstg -55 t o 200 oC
Lead Temper at ure (1/1 6" from case f or 10 sec onds ) TL300 oC
ELECTRICAL CHARA CT ERIST ICS (TA = 25 oC unless otherwise noted)
SYMBOL CHARACTERISTCS TYP1SST404 SST405 SST406 UNIT TEST CONDITIONS
MIN MAX MIN MAX MIN MAX
STATIC
V(BR)GSS Gate-Source Breakdown V oltage -58 -50 -50 -50
V
IG = -1µA, VDS = 0V
V(BR)G1 - G2 Gate-Gate Breakdown V o ltage -58 ±50 ±50 ±50 IG = ±1µA, VDS = 0V, VGS = 0V
VGS(OFF) Gate-Source Cut off Voltage -1.5 -0.5 -2.5 -0.5 -2.5 -0.5 -2.5 VDS = 15V, ID = 1nA
IDSS Saturation Drain Current 23.50.5100.5100.510 mA V
DS = 15V, VGS = 0V
IGSS Gate Reverse Current -2 -25 -25 -25 pA VGS = -30 V, VDS = 0V
-1 nA TA = 125oC
IGGate Operating Current -2 -15 -15 -15 pA VDG = 15V, ID = 200µA
-0.8 -10 -10 -10 nA TA = 125oC
rDS(ON) Drain-Source On-Resistance 250 ΩVGS = 0V, ID = 0.1mA
VGS Gate-Source Voltage -1 -2.3 -2.3 -2.3 VVDG = 15V, ID = 200µA
VGS(F) Gate-Source Forward V oltage 0.7 IG = 1mA, VDS = 0V
DYNAMIC
gfs Common-Source Forward Transconductance 1.5 121212 mS
VDG = 15V, ID = 200µA
f = 1kHz
gos Common-Source Output Conductance 1.3 2 2 2 µS
gfs Common-Source Forward Transconductance 1.5 272727 VDS = 10V, VGS = 0V
f = 1kHz
gos Common-Source Output Conductance 10 20 20 20
Ciss Common-Source Input Capacitance 8 8 8 pF VDG = 15V, ID = 200µA
f = 1MHz
Crss Common-Source Reverse Transf e r Capaci tance 1.5 3 3 3
enEquivalent Input Noise Voltage 10 20 20 20 nV/ Hz VDG = 15V, ID = 200µA
f = 10Hz
MATCHING
| VGS1 - VGS2 | Differenti al Gate-Source Voltage 15 20 40 mV VDG = 10V, ID = 200µA
∆ | VGS1 - VGS2 |
∆TGate-Source Voltage Differential Change with
Temperature 25 40 80 µV/ oCTA = -55 to 25oCVDG = 10V,
ID = 200µA
25 40 80 TA = 25 to 125oC
CMRR Common Mode Rejection Ratio 102 95 90 dB VDG = 10 to 20V, ID = 200µA
NOTES: 1. F or design aid only, not subject to production testing.
2. Pulse test; PW = 300µs, duty cycle ≤ 3% .
CALOGIC LLC, 237 WHITNEY PLACE, FREMONT, CA 94539, 510-656-2900 PHONE, 510-651-1076 FAX DS068 REV A
