IM6653/IMG6654 GENERAL DESCRIPTION The Harris IM6653 and IM6654 are fully decoded 4096 bit CMOS electrically programmable ROMs (EPROMs) fabri- cated with Harris advanced CMOS processing technology. In all static states these devices exhibit the microwatt power dissipation typical of CMOS. Inputs and three-state outputs are TTL compatible and allow for direct interface with com- mon system bus structures. On-chip address registers and chip select functions simplify system interfacing require- ments. The IM6653 and IM6654 are specifically designed for pro- gram development applications where rapid turn-around for program changes is required. The devices may be erased by exposing their transparent lids to ultra-violet light, and then re-programmed. ORDERING INFORMATION IM6653/IMG6654 4096-Bit CMOS UV EPROM FEATURES Organization IM6653: 10244 M6654: 5128 Low Power 770, W Maximum Standby High Speed 300ns t0V Access Time For IM6653/54 Al 450ns 5V Access Time For IM6653/54-11 Single + 5V Supply Operation UV Erasable Synchronous Operation For Low Power Dissipation Three-State Outputs and Chip Select for Easy System Expansion Part Temperature Number Range Package IM6653/41JG 40C to +85C | 24-Pin CERDIP IM6653/4-1NG 40C to + 85C | 24-Pin CERDIP IM6653/4A1JG 40C to + 85C | 24-Pin CERDIP IM6653/4MJG* 55C to + 125C | 24-Pin CERDIP IM6653/4AMJG* | --55C to +125C | 24-Pin CERDIP * Add /HR for HiRel processing Ag Ato or PROGRAM Arde, Ez oo , oO 4 gle iE z,-7->| APORESS Sis | ws 2 8 16[5 PROGRAM al: ie o4 OR 3 oe 5 L_ Zt 0375-2 0375-3 0375-1 Figure 1: Functional Diagram Figure 2: Pin Configurations HARRIS SEMIGONDUCTOR'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE. THE WARRANTY SHALL BE EXCLUSIVE AND SHALL 8 IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTAGILITY AND FITNESS FOR A PARTICULAR USE. WOTE: All typical valves have been charactenzed but are not tested. 16002IM6653/IM6654 ABSOLUTE MAXIMUM RATINGS (IM6653/54 |, -1I, M) Supply Voltages VDDVSS 0+ ee cece e tee etree ees +B.0V VOCHVGS - oe cece eee eect e renee eene +86.0V {nput or Output Voltage ..... (Vssg 0.3V) to (Vpp + 0.3V) Operating Range Range (Ta) Industrial ............0..0.0....0000. 40C to + 85C Military 2.00.00. 0.00.0 cece ee eee eee 58G to + 125C DC ELECTRICAL CHARACTERISTICS Storage Temperature Range . Lead Temperature (Soldering, 10sec) NOTE: Siresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended pari- ods may affact device reliability. (Voc= Vpp = 5V + 10% Vss = OV, Ta = Operating Temperature Range) 65C to + 150C 300C Symbol Parameter Conaitty ns IM6653/541, ~11, M Units Min Max Vin Logical 1 Input Voltage &,,S$ Vpp2.0 Vin Address Pins 2.7 Vv Vit Logical 0 Input Voltage 0.8 I Input Leakage GND<Vin<Vpp -1.9 4.0 pA Vou Logical 1 Output Voltage lon= 90.2mA 2.4 Vv VoL Logical 0 Output Voitage lol =2.0mA 0.45 lok Output Leakage GND<Vo<Voc 1.0 1.0 istpy Standby Supply Current Vin=Vpp 400 pA Icc Vin=Vop 40 Ipp Operating Supply Current (1) f=1MHz 6 mA Cc, Input Capacitance Note 1 7.0 pF Co Output Capacitance Note 1 10.0 Note: 1. For design reference only, not 100% tested. AC ELECTRICAL CHARACTERISTICS Woc=Vpp=5V + 10% Vgg=0V, C_ = 50pf, T, = Operating Temperature Range) Symbol Parameter IM6653/54-11 1M6653/54 I 1IM6653/54 M Units Min Max Min Max Min Max TE ,LQV Access Time From Ey 450 550 600 TSLQV Output Enable Time 110 140 150 TE,HQZ Output Disable Time 110 140 150 TE,HE;L | , Pulse Width (Positive) 130 150 150 TE,LE,H E, Pulse Width (Negative) 450 550 600 ns TAVE,L Address Setup Time 0 0 0 TE LAX Address Hold Time 80 100 100 TEaVEqL Chip Enable Setup Time (6654) 0 0 0 TE,LE2X | Chip Enable Hold Time (6654) 80 +06 100 NOTE: Al typical values have bean characterized but are not tested. 14-3 IM6653/IM6654IMG6653/IM6654 IM6653/IM6654 ABSOLUTE MAXIMUM RATINGS (IM6653/54Al, AM) Supply Voltages Storage Temperature Range .......... 65C to + 150C VDDVSS csc ceeeeece cere eee ee sete teneee ees +11.0V Lead Temperature (Soldering, 10sec) ............. 300C Vom VSS occ cee e eet ener e eet eee enes +11.0V NOTE: Stresses above those listed under Absolute Maximum Ratings Input or Output Voltage ..... (Vgg 0.3V) to (Vpp +0.3V) may cause permanent damage to the device. These are stress ratings only Operating Temperature Range and functional operation of the device at these or any other conditions Industrial .... 2.2.2... 40C to + 85C above those indicated in the operat ctions of the sp s not Military 55C to + 125C implied. Exposure to absolute maximum rating conditions for extended peri- erence ener eee e tere enee ods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Vcc = Vop = 4.5V to 10.5V Vgs = OV, Ta = Operational Temperature Range) Symbol! Parameter Test Conditions IMG653/54Al, AM Units Min Max Vin Logical 1 Input Voltage ES Vpp2.0 Vin Address Pins Vop - 2.9 Vv Vit Logical "0" Input Voltage 0.8 ly Input Leakage GND<Vin=Vpo -1.0 1.0 pA VOH Logical '1" Output Voltage lout =0 (Note 1) Voc 0.01 Vv VoL Logicai 0 Output Voltage louT=0 (Note 1) Vsg+ 0.01 lotk Output Leakage Vss<VosVec 1.0 1.0 Istay Standby Supply Current Vin= Vpp 100 pA loc Vin= Vpo 40 Ipp Operating Supply Current f= 1MHz 12 mA Cc input Capacitance Note 1 7.0 pF Co Output Capacitance Note 1 10.0 Note: 1. For design reference only, not 100% tested. AC ELECTRICAL CHARACTERISTICS (Vcc=Vpp= 10V +5% Vgg = OV, C_=50pf, Ta = Operating Temperature Range) Symbol Parameter 1M6653/54 Al 1M6653/54 AM Units Min Max Min Max TE,LQV Access Time From E, 300 350 TSLQV Output Enable Time 60 70 TE,HQZ Output Disable Time 60 70 TE HEL E, Pulse Width (Positive) 125 125 TE,LE,H E, Pulse Width (Negative) 300 350 ns TAVE,L Address Setup Time 0 0 TE,LAX Address Hold Time 60 60 FE2VEyL Chip Enable Setup Time (6654) 0 Oo TE,LEaX Chip Enable Hold Time (6654) 60 60 NOTE: All typical values have been characterized but are not tested. 14-4IN6653/IMG654 PIN ASSIGNMENTS Pin Symbol oe Description 1-8,23 Ag-A7,A8 - Address Lines 9-11, 13-17 Qo-Q7 - Data Gut lines, 6654 Qo-Q3 - Data Cut lines, 6653 12 Vss - Negative Supply 18 Program - Programming pulse input 19 Vpb - Chip positive supply, normally tied to Voc 20 E, L Strobe line, latches both address lines and, for 6654, Chip enable Eo 21 s L Chip select line, must be low for valid data out 22 Ag - Additional address line for 6653 _ Eo L Chip enable line, latched by Chip enable E, on 6654 24! Voc - Output buffer positive supply READ MODE OPERATION In a typical READ operation address lines and chip en- able Ep* are latched by the falling edge of chip enable E, (T=0). Valid data appears at the outputs one access time (TELQV) later, provided level-sensitive chip select line Sis low (T= 3). Data remains valid until either ; or S returns to a high jevel (T= 4). Outputs are then forced to a high-Z state. Address lines and E> must be valid one setup time before (TAVEL), and one hold time after (TELAX), the falling edge of E, starting the read cycle. Before becoming valid, Q out- put lines become active (T= 2). The Q output lines return to a high-Z state one output disable time (TE;HQZ) after any rising edge on E, or S. The program jine remains high throughout the READ cy- cle. Chip enable line E, must remain high one minimum posi- tive pulse width (TEHEL) before the next cycle can begin. FUNCTION TABLE he MOSES only, E, M6654 onty 0375-4 Figure 3: Read Cycle Timing biog _ _inputs _ Outputs Notes E1 E2 Ss A -1 H x x x z DEVICE INACTIVE 0 N L xX Vv zZ CYCLE BEGINS; ADDRESSES, Ep LATCHED* L X x Xx Z INTERNAL OPERATIONS ONLY 2 L X L X A QUTPUTS ACTIVE UNDER CONTROL OF E, 5 3 L x L Xx Vv OUTPUTS VALID AFTER ACCESS TIME 4 a x L x v READ COMPLETE 5 H x x x Zz CYCLE ENDS {SAME AS 1) NOTE: Ail typical values have been characterized but are nat tested. 14-5 IMG6653/IM6654IM6653/IM6654 IMG6653/IM6654 Figure 4: Read and Program Cycle Timing 0375-5 DC CHARACTERISTICS FOR PROGRAMMING OPERATION (Vcc=Vop= 5V +5% Vgg= OV, Ta= 25C) Symbol! Parameter conattons Min Typ Max Units IPROG Program Pin Load Current 80 100 mA VpROG Programming Puise Amplitude 38 40 42 v loc Voc Current 0.1 5 mA lop Vpp Current 40 100 VIHA Address Input High Voltage Vpp 2.0 VILA Address Input Low Voltage 0.8 Vv Vin Data Input High Voltage Vop- 2.0 VIL Data Input Low Voltage 0.8 AC CHARACTERISTICS FOR PROGRAMMING OPERATION (Vcc= Vop=5V +5% Vss= OV, Ta = 25) Symbol Parameter Test Min Typ Max Units Conditions TPLPH Program Pulse Width tise = tai= 5s 18 20 22 ms Program Pulse Duty Cycie 75% TDVPL Data Setup Time 9 us TPHDX Data Hold Time 9 TE,HEyL Strobe Pulse Width 150 TAVE,L Address Setup Time 0 ns TE,LEsX Address Hold Time 100 TE,LQV Access Time 1000 NOTE: Ail typical values have been characterized but are not tested. 14-6PROGRAM MODE OPERATION Initially, all 4096 bits of the EPROM are in the logic one (output high) state. Selective programming of proper bit lo- cations to 0s is performed electrically. In the PROGRAM mode for all EPROMs, Voc and Vop are tied together to a + 5V operating supply. High logic lev- els at all of the appropriate chip inputs and outputs must be set at Vpp 2V minimum. Low logic levels must be set at Vss +0.8V maximum. Addressing of the desired location in PROGRAM mode is done as in the READ mode. Address and data lines are set at the desired logic levels, and PRO- GRAM and chip select (S) pins are set high. The address is latched by the downward edge on the strobe line (E1). Dur- ing valid DATA IN time, the PROGRAM pin is pulsed from Vop to 40V. This pulse initiates the programming of the device to the levels set on the data outputs. Duty cycle iimi- tations are specified from chip heat dissipation considera- tions. PULSE RISE AND FALL TIMES MUST NOT BE FASTER THAN 5Suzs. Intelligent programmer equipment with successive READ/PROGRAM/VERIFY sequences is recommended. PROGRAMMING SYSTEM CHARACTERISTICS 1. During programming the power supply should be ca- pable of limiting peak instantaneous current to 100mA. 14-7 IM6653/IM6654 2. The programming pin is driven from Vpp to 40 volts (+2V) by pulses of 20 milliseconds duration. These pulses should be applied in the sequence shown in the flow chart. Pulse rise and fall times of 10 microseconds are recommended. Note that any individual location may be programmed at any time. 3. Addresses and data should be presented to the de- vice within the recommended setup/hold time and high/low logic level margins. Both A (10V) and non A EPROMs are programmed at Vcc, Vop of 5V +5%. 4. Programming is to be done at room temperature. ERASING PROCEDURE The IM6653/54 are erased by exposure to high intensity short-wave ultraviolet light at a wavelength of 2537A. The recommended integrated dose (i.e., UV intensity x exposure time) is 10W sec/cm2. The lamps should be used without short-wave filters, and the IM6653/54 to be erased should be placed about one inch away from the lamp tubes. For best results it is recommended that the device remain inac- tive for 5 minutes after erasure, before reprogramming. The erasing effect of UV light is cumulative. Care should be taken to protect EPROMs from exposure to direct sun- light or fluorescent lamps radiating UV light in the 2000A to 4Q00A range. IM6653/IM6654IM6653/IMG6654 IMG653/IM6654 Figure 5: Programming Flow Chart 0375-6 NOTE: All typical! values have been charactarized but are not tested. 14-8IM6653/IM6654 +s GND < 8 < 8 < 8 Oud wu EPSP 8 INPUT PRErZxPry Epop RF PIPPIPP IPT 0375-7 Figure 6: IM6653 CMOS EPROMS as External Program Memory with the IM80C35 0375~8 Figure 7: Using IM6654 CMOS EPROM To Extend Program Memory NOTE: Ail typical values have been charactarized but are not tested. IM6653/IM6654