ITE Caretta oe OORT Ly "0 1a RRO eA _ FEATURES" @ 262,144 words x 1-bit organization @ 100/120/150 ns access time from RE @ 50/60/75 ns access time from CE @ 385/360/330 mW active power, Page Mode, @ 256 refresh cycles 413/385/360 mW active power, Nibble Mode, at minimum cycle time -@ 25 mW standby power e@ Multiplexed address inputs @ +10% power supply tolerance DESCRIPTION The M41256xx-10B, -12B, & -15B integrated circuits are high-speed, low-power 262,144 words by 1-bit dynamic random access memory (DRAM) devices. These devices are available with various mode, speed, and package options. @ Read-Modify-Write capabilities e RE Only Refresh/Hidden Refresh @ Latched or high impedance output during refresh @ Nibble Mode/Page Mode options e CE before RE refresh with Nibble Mode Option e Available in 2 plastic or hermetic ceramic DIP, plastic leaded chip carrier (PLCC), and hermetic ceramic leadless chip carrier (LCC) Multiplexed Address Buffers (9) 256 Sense Amps| 256 Sense Amps 256 Ref Cells 256 Ref Cells 9 a . > = 4/0 6 Buses - [| Upper 2 of 512 Column Selector ; on Data gel Lower 2 of 512 Column Selector SEL Buffer Sia no Sat Ss 410 ata 5 r AMP aut (U2) 256 Ref Cells 256 Ref Cells . 256 Sense Amps 256 Sense Amps| [Ge}-= Timing Generator , Figure 1. Page Mode Block Diagram ATST reserves the right to make changes to the product(s) or circuit(s) described herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product or circuit. 1986 AT&T. All Rights Reserved. July 1986AT a T MELEC (I ) a2 DM O0S0026 0000313 5 mi 1-46-23-15 M41256xx-10B, -12B, & -15B Dynamic RAM : RA8 CAS - [256 Sense Amps] 256 Sense Amps 256 Ref Celts _ 256 Ref Cells 40 Buses Multiplexed Address Buffers (9) lumn Selector 1-of-4 Data . HO Out olumn Selector SEL Buffer Upper 2 of 51 Lower 2 of 51 sd 1 of 256 6 |Row SEL pe Data in Buffer 41/0 AMP 1 of 256 Row SEL 256 Ref Cells 256 Ref Cells 256 Sense Amps} 256 Sense Amps | [Ge-> Generator , ' [we USER INFORMATION Pin Descriptions A2 AN NC RE W Oiriri frm 4 3 b At Ai[]s 2[]5 AB vec vec []9 1, ] a8 i Ves a7 A7[]10 18[]Vss } _ As |it 171 | CE : CE 16 15 14 13 12 AS C 1213 14 #15 16 _ . CITILICI LI G a6 NC AS A4 Ad AS NC AG Q 18 1/O Ceramic LCC 18 I/O PLCC Pin Description Key Symbol Name a7 AB 10 J 16 Vss Vcc +5 V Supply o 26 1s CE D Data In WwW 3c cr) 14 Q - RE 4 13 AG Q Data Out AO 5c 12 A3 A(O8) Address Input (0-8) A2 6q nh 14 Aa Ww Write Enable Al - 7 Ch7I 10) AS RE Row Enable Veo 8 & 9 Ar CE Column Enable 16-Pin DIP Vss Ground NC No Connect ~ Figure 3. Pin Function Diagramos APD nnata in i T=4 23-15 I A T & T MELEC (I C) 42 D M@ 0050026 0000314 7 mm i NI41256Xx-10B, -12B, & -15B Dynamic RAM , CHARACTERISTICS Operating Conditions (TA = 0 to 70C) . Parameter Symbol Min Nom Max Unit i Supply Voltages Vcc 4,5 5.0 5.5 V i Vss 0 0 0 Vv Input Voltages* : High Level All Inputs (Logic 1) VIH 2.4 - 6.5 Vv : Low Level All Inputs (Logic 0) VIL ~1.0 - 0.8 Vv : Refresh Cycle Time** , tREF - _ 4.0 ms * Application of invalid levels may destroy stored information during that cycle as well as the first cycle using valid levels. Data out is indeterminate. ** Addresses AOA7 are used for refresh. A8 must be a valid one or zero. Electrical Characteristics (Vcc = 5 V 410%, Vss = 0 V, TA = 0 to 70C) M41256xx-10B | M41256xx-12B | M41256xx-15B Parameter Symbol Min Max Min Max Min Max | Unit Output Voltages Low Level (OL = 4.2 mA) VOL 0.4 0.4 - 0.4 Vv High Level (IOH = 5.0 mA) Vou 2.4 - 2.4 _ 2.4 - Vv Power Supply Currents Operating Current _ (Average Operating Current RE & CE Cycling, tRELREL = minimum) Page Mode Option Icc1 - 70T - 65T - 60T mA Nibble Mode Option Icct - 75t - 70f - 65+ mA Standby Current (RE = VIH, Q = High Impedance) Icc2 4.5 _ 4.5 - 4.5 mA Refresh Current (Average Operating Current, Refresh Mode Operation) | RE Cycling, CE = VIH, tRELREL = min. Page Mode Option Icc3 - 557 50f - 45+ mA Nibble Mode Option Icc3 - 60T- _ 55T - 50f mA CE before RE Nibble Mode Option Icc3 - 95 - 90T - gst | mA Page Mode Current (Average Operating Current, Page Mode Operation, RE = VIL, CE Cycling, tCELCEL = minimum) Icc4 507 - 45 - 40t mA Nibble Mode Current (Average Operating Current, Nibble Mode Operation, RE = ViL, CE Cycling, . tNCELCEL = minimum) Iccs _ 55t - 50T _ 45+ mA { Maximum occurs at TA = 0C. Icci, Icc3, Icc4, and Iccs are specified with output open-circuited.AT&T NELEC (I ) a2 )D m 0050024 o000315 5 ma 1-46-23-15 M41256xx-10B, -12B, & -15B Dynamic RAM & aa M41256xx-10B | M41256xx-12B | M41256xx-15B Parameter - Symbol Min Max Min Max Min Max | Unit Input Leakage Current (Vcc = 5.5 V, Vi = 0to 6.5 V, i i i ! All other ieads at 0 V) i -10 | 10 | -10 | 10 | -10 | 10 Output Leakage Current . . (Q = High Impedance, VQ = 0 to Vcc) Io 10 10 10 10 -10 10 Input Capacitance (AOA8)jf Ci _ 5 - 5 - 5 pF Input Capacitance (D, W Leads)tt cp -_ 5 _ 5 | - 5 pF Input Capacitance (RE, CE Leads){t CB = 10 ~_ 10 _ 10 pF Output Capacitance (Q Lead)tt Co - 7 _ 7 _ 7 pF +t Parameter periodically sampled and not 100% tested. Hm ARIK Eg Maximum Ratings* | Rating Symbol Value Unit Voltage Range on VCC Relative to Vss Vcc -1.0 to +7.0 Vv Power Dissipation PD 1.0 .W Case Operating Temperature Range Tc 0 to 85. C Ambient Operating Temperature Range TA 0 to 70 C Ambient Storage Temperature Range** Tstg Ceramic Package -65 to +160 C Plastic Package 55 to +120 C Short Circuit Output Current . Ios 50 mA * Maximum Ratings are defined as the limiting conditions that the user can apply to the device under all variations of circuit and environmental conditions. If any rating is exceeded, permanent damage to the device may result. Ex- tended operation at any of these conditions may result in reduced reliability. ** Bonding or soldering of the external pins of these devices can be performed safely at temperatures up to 300C.A T & T MELEC (I C) 62 D MM 0050026 0000316 Oo my 1746-23-15 M41256xx-10B, -12B, & -15B Dynamic RAM STP tet ye TTS Timing Characteristics (Vcc = 5 V +10%, Vss = 0 V, TA = 0 to 70C) (Notes 1, 2, and 3) ee i JEDEC M41256xx-10B | M41256xx-12B |. M41256xx-15B : Description Symbol Symbol Min | Max | Min | Max | Min | Max | Unit i Random Read/Write Cycle Time tRC tRELREL 200 - 220 - 260 - ns 3 Access Time from RE - 4 (Notes 4 & 5) tRAC tRELQV _ 100 120 - 150 ns i Access Time from CE : (Notes 5 & 6) tCAC tCELQV - 50 _ 60 - 75 ns i Output Buffer Turn Off Delay ; (Note 7) tOFF | tCEHQZ 0 20 0 30 0 30 ns : Transition Time wT 7 2 50 2 50 2 50 ns : RE Precharge Time tRP tREHREL 90 - 90 - 100 - ns RE Pulse Width tRAS tRELREH 100 10000 120 10000 150 10000 ns RE Hold Time tRSH tCELREH 50 - 60 - 75 - ns CE Pulse Width (Note 8) tCAS tCELCEH 50 10000 60 10000 75 10000 ns ; CE Hold Time .. tCSH | tRELCEH | 100 ~ 120 - 150 | ns i RE to CE Delay (Note 4) tRCD tRELCEL 25 50 25 60 25 75 ns : CE to RE Precharge Time tCRP | tCEHREL 0 - 0 - 0 | ns : Row Address Setup Time tASR tRAVREL 0 ~ 0 - 0 | ns Row Address Hold Time tRAH tRELRAX 15 - 15 ~ 15 - ns Column Address Setup Time tASC tCAVCEL 0 0 - 0 - ns Column Address Hold Time tCAH tCELCAX 15 - 20 - 25 - ns Column Address Hold Time Ref. to RE tAR tRELCAX 75 _ 90 _ 105 - ns Read Command Hold Time Ref. to RE tRRH tREHWX 10 _ 10 _ 10 | ns Read Command Setup Time tRCS tWHCEL 0 - 0 - 0 - ns Read Command Hold Time Ref. to CE tRCH tCEHWX 0 - 0 - 0 _ ns Write Command Hold Time tWCH tCELWX 15 - 20 - 25 ns Write Command Hold Time Ref. to RE tWCR tRELWX 85 - 100 - 120 _ ns Write Command Pulse Width tWwP tWLWH 15 - 20 - 25 _ ns Write Command to RE Lead Time tRWL tWLREH 30 _ 35 - 45 | ns Write Command to CE Lead Time tCWL tWLCEH 20 _ 30 - 40 | ns Data In Setup Time tDS tDVCEL 0 - 0 - 0 - ns Data In Hold Time tDH tCELDX 15 - 20 - 25 - ns Data In Hold Time Ref. to RE tDHR tRELDX 85 - 100 | 120 _ ns WriteCommand Setup Time (Note 9) tWCs tWLCEL 0 - 0 _ 0 - ns CE to W Delay (Read-Modify-Write) tCWD tCELWL 25 ~ 30 _ 35 - ns RE to W Delay (Read-Modify-Write) (Note 6) tRWD tRELWL 75 _ 100 _ 125 | ns Data In Hold Time (Read-Modify-Write) (Note 6) tDH tWLDX 20 = 20 20 - ns Data In Setup Time ; (Read-Modify-Write) tDS tDVWL 0 _ 0 - 0 _ ns Refresh Period 7 tREF tR _ 4.0 _ 4.0 - 4.0 | ms Cycle Time (Read-Modify-Write) tRMW | tWRELREL 245 ~ 260 _ 310 - nsSoi rime. syne erat gn ecg ee era aie at a ot. ne mics * A T & T MELEC (I C) 82 D M@@ OOSO02b 0000317 2 me 7-46-23-15 M41256xx-10B, -12B, & -15B Dynamic RAM JEDEC M41256xx-10B | M41256xx-12B | M41256xx-15B Description Symbol Symbol Min | Max | Min | Max | Min | Max | Unit PAGE MODE OPTION Page Mode Cycle Time tPC tCELCEL 120 _ 130 - 145 _ ns CE Precharge Time tCP tCEHCEL. 45 _ 50 - 60 os ns NIBBLE MODE OPTION CE Cycle Time tNC | tNCELCEL 50 - 60 - 70 | 10000 | ns Access Time from CE . . _ Notes 5 & 6) tNCAC tNCELQV - 20 - 25 - 30 ns RE Hold Time tNRRSH | tNCELREH 20 10000 25 10000 30 10000 ns CE Pulse Width ; tCAS | tNCELCEH 20 10000 25 10000 30 10000 ns Write Command Hold Time tWCH tNCELWX 10 - 10 - 10 _ ns Write Command to RE Lead Time | tNRWL | tNWLREH 20 _ 25 - 30 - ns Write Command to CE Lead Time | tNCWL | tNWLCEH 20 - 25 - 30 - ns Write Command Pulse Width tNWP tNWLWH 10 - 10 - 10 _ ns Data In Hold Time tDH tNCELDX 10 - - 10 - 10 _ ns CE Precharge Time tNCP | tNCEHCEL 20 _ 25 _ 30 ns CE to W Delay ; (Read-Modify-Write) tNCWD tNCELWL 10 _ 15 15 _ ns Data In Hoid Time (Read-Modify-Write) (Note 6) tDH tNWLDX 10 - 10 - 10 - ns CE Before RE Refresh CE to RE Delay tFCS tCELREL 10 - 10 - 10 _ ns CE Hold Time tFCH tRELCEX 20 - 25 _ 30 _ ns RE Precharge to CE Active tRPC tREHCEL 0 _ 0 ~ 0 = ns Notes: 1. 2. pan nw Timing specifications given assume ff = 5. ns. Vin (min.), VIL (max.) are reference levels for timing specifications or input signals. Transition times are to be measured between these reference levels. An initial pause of 100 ps followed by a minimum of 8 refresh cycles is necessary after Vcc is applied, to achieve proper device operation. Addresses AOA7 are used for refresh. A8 must be a valid one or zero. For tRELCEL > tRELCEL (max.), tRELQV will increase by the amount that tRELCEL (max.) is exceeded. Q load assumed to be equivalent to 2 TTL loads and 100 pF. Assumes tRELCEL = tRELCEL (max.). tCEHQZ (max.) defines the time at which Q achieves the open circuit condition. CE can be held at Logic 0 for an indefinite time for latched output during refresh, However, tRELRAX must be increased to 100 ns. Non-restrictive operating parameter. If {WLCEL = tWLCEL (min), the cycle is an early write cycle and the data out (Q) will re- main an open circuit (high impedance) for the entire cycle. If tCELWL = tCELWL (min.) and tRELWL = tRELWL (min.), the cycle is a read-write cycle and the data out (Q) will validly reproduce the data contained in the selected cell. If neither of the above sets or conditions is satisfied, data out will be indeterminate.AT @ T MELEC (I C) a2 D mi 0050024 o000318 4 ma 1-46-23-15 i | M41256xx-10B, -12B, & -15B Dynamic RAM Fee nant Timing Diagrams tRELREL wig tRELREH j$_$ ______. tREL CEH RE Vin _ tRELCAX ~ VIL . i tCELREH @ tRELCEL tCELCEH & i : k Viqo = i CE Ve i tRELRAX > <_ : ; : ~ tCELCAX tCEHCEL tRAVREL tCAVCEL tREHREL SUR wOR een ne RE pant aL 0 tCEHREL : Vu = ROW COLUMN AXXKKKK ROKR EKER ERR) ADtoAS =, XNYyt ADDRESS | ADDRESS PRX K KKK RNY { tCEHWX | 'WHCEL tREHWX l ae I XK We RRR _?______- tRELQV VoH Q Vol Figure 4. Read Cycleee A T&T MELEC (I C) 62 D M@ 0050026 0000319 b MM T-46-23-15 M41256xx-10B, -12B, & -15B Dynamic RAM FOE We Sa BRINE Ee AO to A8 =| Vin Vin VIH Vit Vin VIL Vin VIL Vin VIL tRELREL ett tRELREH ___ am et tRELCEH __> =_ 3 _ N jgt tRELCAX tREHREL M tRELCEL tCELREH m | tCELCEH o~ tCEHREL tRELRAX m | | tCEHCEL tRAVREL -ggee pent tCAVCEL - ROW COLUMN KARR RK AORN ADDRESS ADDRESS LYYYY Ny xX RAR YY 1 ' | | | {WLCEH a | tWLCEL NN Xx RA ROM XRX RRR RR BER QW WON % Oe ROR BD | DATA , tRELDX RY xX XX v YOY Gis XXX) RW RY KX VoH Vo. OPEN Figure 5. Write Cycle (Early Write)TNS mrp 1 RTT mene! Dee me sete ee PSL ae aaa eRe We beep SY WALL NPE TYRONE EE RENEE ORR EE AT & T MELEC (I C) 62 D M@i 0050026 0000320 2 mm 71-46-23-15 M41256xx-10B, -12B, & -15B Dynamic RAM aes tWRELREL at a tREL RE <a gg EL EH __ va a= tRELCAX > RE _ N Vit |. . : tREHREL a tRELCEL . tCELREH _____ gis tCELCEH _-gam= Va | CE Vu = \ . + tRELRAX . ICELCAX tCEHCEL tRAVREL pamt tCAVCEL ViH COLUMN LOOOOIOOO OOK RIDIN) 1) A010 AB vn ADDRESS _ PX KRREX RK RANK RKXRRAAN ER NORY i i tRELWL =| S [~~ tceLWL tCEL Vin 2 - Vi Wy | Qv in VoH | | 7 VALID *. y OUTPUT Q Vo. : | LL tRELQV _______ _| tWLDX tDVWL Vix pan IIIA RAO VI OYA F PAPAS YVVYY \AAKA OOOO OOOO 000 00 OOOO OOK OOK KKK YX) VALID KLOQQOOOKKOOXX A Dvn REINA RARR RRO, _ DATA PRS RXR Figure 6. Read-Modify-Write Cycle tRELREL . | tRELREH VH = RE Vit - tRELRAX tRAVREL laas Vn = XKKKKK KEKE? AKL KKKKEKK XXXKK CHK KKKKKK KKK 0 Q ) AO tO AT vi RKO ADDRESS PRX SRR RRC RR Q Vou OPEN Vo. NOTE: Input CE = Vik, Input W = Don't Care Figure 7. RE Only Refresh Cycle (Note 3)| tregpeeny' an pare AR TOE pent ETP A RI MLR PM _ AT&T MELEC (IC) 62 D M OO50026 oO00321 4 mm 1~46-23-15 M41256xx-10B, -12B, & -15B Dynamic RAM tRELREL tRELREH - Vin RE VIL t*CELREL rE Vin CE Vit | { VoH Qa Vo. = OPEN NOTE: Inputs AOA8, W, D = Dont Care Figure 8. CE Before RE Refresh Cycle (Available with Nibble Mode Option Only) tRELREL _>| Vin RE Vi tRELCEX | CE Vi = i a a lag I felB>1 tRELRAX tRAVREL lag * i TCAVCEL RAVREL a <_ | AO to A8 ve CX now ADD MW COL ADD ROW ADD* | OK XKKK KKK | tCELCAX | tWHCELgel al Wrenn EKO tCELQV tCEHOZ < le tRELQV 3 . Vou 7 Q va = { VALID OUTPUT _}- l. READ mi REFRESH * This row address not necessary when using a device with CE. before RE refresh (as available with the nibble mode part). | Figure 9,-Hidden Refresh Cycle (Notes 3 & 8) 10woe mele STITT oy ROA eR RR NONE aOR oe ro Ue ogRAN eri OS Lome AT & T MELEC (IC) a2 D MM OOSOO@ O000322 & mm 1-46-23-15 M41256xx-10B, -12B, & -15B Dynamic RAM AO to A8 =| tRELREH < tRELCEH g-@I- tRELCAX Vin _ x Vit - a -}} ! [+ toekcet tCELCEH ' tRELCEL tCEHCEL {CELCEH tCELCEH Vu = : Vit _ tRELRAX4 tCELCAX M tCELCAX tRAVREL le tCAVCEL | tCAVCEL Vin COL KLKIKKKKKKKKKR AK KOOOOORK XA KICIIOX AIK Vit ADD PRRRRRKEXNY KK KKK RRR ROR ER I {CELQV > je tczLav| + _w-tceLav tRELQV (cEHozo < | tCEHOZ 3 e| tCEHQZ VoH t 7 * * Vo. = OPEN { { Re { Va == Vt Os x ae tWHCEL *WHCEL tCEHWX tCEHWX ORY x 9.9.4 RRR ~ (AX? KRY) RN Figure 10. Page Mode Read Cycle 11ene Mg array ce eee A eT TRH We gree cme A T & T MELEC (I C) 4e p mi O0S0026 0000323 M41256xx-10B, -12B, & -15B Dynamic RAM & ME 1T-46-23-15 ae tRELREH jg_ tRELCEH > tRELCAX RE Vino Vu tCELCEL tRELCEL | he tCEHCEL _tCELCEH aE Vin CE Vit - tRELRAX tCAVCEL tRAVREL le => We tCELCAX | ;tcavceL | Vin = AKKRRA KY KKXKK KX RRR OL WOOO ONY AO to A8 OL COL RAYMAN) OOD 7: ORY) vi 00 NYBXMRXRRRIY RR RRRIA_AD9_ ZARA RRR RR i tCELWxLol e| hee tcELWX o| le tcELwx | tWLCEH -@ tWLCEH-@ | Vin VY KY MAKAK AD | w RN MLL vi DORR Vie | aL tWLWH i tWLWH ee tRELWX , | tWLREH ~ ja tCELDX etel tcELDX PELOX - ke tovcEL tDVCEL VOOR VALID ROK VALID OX BKK KKK KKK ARAM) KRY ) Mu OS OW DATA__ FRANK PRR RR KR Figure 11. Page Mode Write Cycle 12T-46-23-15 Mm 00500ceb ooo00324 T = D M41256xx-10B, -12B, & -15B Dynamic RAM Se AT & T MELEC (I C) Pee a SE, apPAD UM-AMPOW-peay Spoy| We_ ZL ans1y KITA ERK IK ee KR IERRY 4% Wy KH ay VOUOVEREOOVEEEVENEOES XK) A EESECCECETT EN KKK AR RRR TI A RRR RR RRR ERR ORY AR RRR K RR LE RRR RK EK RRR KRY nn >| Lesnar xa _ g ota} > LNdino LNdino K =A Oriva Qniva ar HOA ZOHO} A01301~- ZOH39} aww HAKIMT HACIMG , AO1301 . r x = iA yi bb / PTTL Lin M Hay IM | ht HOTU -Om ke 139M e-HaoTM T1__> 131 | ssgyuday IK KAO KYO A NINITIO ONSEN MMSE Yin BY OF OV xvO1a01 2 H39149: | - E , \ / y l 430739} - SHAD ; 30H39} dL 9 XVOT1I91 : 7397391 Pie 4 139739} > | vr x " WA ~HIA- gu JaHH39I 1397au)} - $$ #313391 --___ SyH3uI wTaS Xvol1aui) A a H3073ut 7 Hau Tau? 7 HG) em MACE fy MR NRTA ER AE Oe DO ICR, Ny een an ea BAN Whee ee te Bee ad ta A ces ABE Ane em Boc wanermrenr ag ORITIOT! T A T & T MELEC (I C) ] 2 D.. Z Dos002b 0000325 1 mm 1~46~23-15 M41256xx-10B, -12B, & -15B Dynamic RAM AO to A8 = 14 tRELREH -_ tRELCEH en Vu = Ve 22 ae tcevcer ! tNCELCEL tREHREL tRELCEL 4 | tNCELREH tNCEHCEL t= tNCEHCEL Viq 5 Vt tRELRAX t= jt teeHReLp tCELCE \- tNCELCEH tNCELCEH tRAVREL -p ag tCAVCEL | 2 op XXX KKK XXX KKK Lago J 5S te 2 1 Vin i FROW Vi ADD i | . tCELOV fat e : | el tnceLav + aa! tNCELQV I tRELQVpe| | *CEHOZwy pee | Tl eet tCEHQZ | {CEHOZ oe] me teraz > VoH Fv | } os VALID VALID RK, ouTPuTy x oureurp-e OUTPUT {otter Vv VoL y tWHCEL . a IWHCEL P| | tWHCEL CORR tCEHWX j VIH_ = Vit ROY | yt OO tCEHWX tCEHWX - tCEHWX Figure 13. Nibble Mode Read Cycle eee nee ye ee ee pe _AT 2 T MELEC (IO - a2 D mi 0050026 o00032b 3 ma 1~46-23-15 M41256xx-10B, -12B, & -15B Dynamic RAM | t{RELREH Me tRELCEH att-tRELCAX- : RE Vino K i Veoo- 22 i i be tCELCEL tNCELCEL tREHREL , tCELCEH tNCEHCEL = pul je metre tRELCEL tNCEHCEL | tNCEHCEL 1 =e VH = CE Vw = tRELRAX-3 je {NCELCEH tNCELCEH g= att tCELCAX tRAVREL 9>|}e _ | CAVCEL 1 . | KKK AO to A8& Vit 4 AOD. 4. ADD J OYA 1 toeLwx 7 ~~ lea of- nWicEH aaa [rey tNceLwx : , | tWLCEH 3>4 fi tNCELWX tNWLCEH : Wom % | | LXXXXEAL fd - a WwW Vit x hey fake | tWLWH a | : NWOWH {NWLWH tWLCEL ne INWLREH i tRELWX _ 2] tNCELDX tCELDX zt g tNCELDX {DVCEL3> . tDVCEL tOVCEL >| jet Va SS D Vu + DATA Le snetox VALID DATA tWLDX Figure 14. Nibble Mode Write Cycle 15mata, weep Ur et vere N nTe A T & T MELEC (I C) 42 dD mi 0050026 o000327 S Mm 1-46-23-15 M41256xx-10B, -12B, & -15B Dynamic RAM AO to A8& 16 =| at tRELREH > ea tRELCEH tCELCEH tREHREL tNCELCEH tNCEHCEL {RAVREL > lane tRELRAX tCELCAX Vin SOOO OOK OR RX OCC ROCIO KIN Vie RR IIR II RC RRC Vin XXXXYKKYKK A RXXYRRXKRKN (RXXXY) RXYKKY vic YOO RY HRY KKR RR), __ AR tRELQV Vou VoL WA? YVVAAVYY LA AASYVA/Y SERN RRA AAR KN | tWLDX bee sel - nox Vin XXXKKRKYXXKY Figure 15. Nibble Mode Read-Modify-Write Cycle Vit prewar ree eke ee i eens eee"A T & T MELEC (ZI ) 82 D W OOSO02b 0000326 7 mm T-46-23-15 ; . - _M41256xx-10B, -12B, & -15B Dynamic RAM OUTLINE DRAWINGS (Dimensions in Inches) 16-Pin Plastic DIP , oy) feo58 max 780 MAX Y f aa eee ES os mn FO wl .200 MAX __ INDEX. SY a tom 155 MAX 120 MAX INDEX AREA* Y os on, no DIA 1 ad 322 MAX 058 MAX i ue 140 -- -- Y t 1 Leora MAX jt .035 MAX l 029 MAX 100 REF Zs 17AT&T MELEC (I C) a2) M@ 005002) 0000329 9 MM T~46-23-15 M41256xx-10B, -12B, & -15B Dynamic RAM 16-Pin Hermetic Ceramic DIP a (~ @ | Ll ~ 1 CJ hed 2 8 - Leno NOS. FOR REFERENCE ONLY LEAD NO. 1 INDEX MARK -785 MAX ___ t- .325 MAX _ _| | ] a : .120 i ; MAX : SURFACE A ' __ __ j a | 7S v r q : ZONE X" Hil __ _ : 4 201 yl e040 .030 .035 7169 | ' ' APPROX | i i uJ | -- -- Us Uw 045 APPROX wel |eg-.019 + .003 .020 MAX + i . (BOTH ENDS i (EACH DIRECTION) Le nea vin ) .100 APPROX tl |e.013 MAX .700 + .008 340 MAX MEASURED WITHIN ZONE 'X (8 LEADS EACH SIDE) 18be eek Am ARRON S FNppatates a Dy yoemmaediine ie +130 (3.56) OMAK cost L 095 (2.41) . aN 1 YN Ll LY L L Ul J AT & T MELEC (I C) a2 D = Dos00a6 oo0o330 5 ma 1-46-23-15 M41256xx-10B, -12B, & -15B Dynamic RAM 18 I/O Plastic Leaded Chip Carrier CIF) 01 Pir 045 (1.14) ; x 45 onmnonm DILIus Ci Li q______.493 (12.52) MAX -__ > fr TYP ty I L.oso (1.27) TYP 457 (11.61) NOM a (13,59) MAX J i pen Pa 1 100 (2.54) AX .005 (.13) Enlarged Detail of Leads MAX .335 (8.51) MAX _ (7.44) "| ge +2) TYP 193 & & . > M41256xx-10B, -12B, & -15B Dynamic RAM A T&T MELEC (I C) 2 D Mm@ OOSOO24 0000331 7 | T 46-23-15 18 I/O Ceramic Leadless Chip Carrier (Hermetic) 4 i t ! i i : | ' 495 4.005 _______ ay A _ PIN MARK 1290 +.005 \ f =) CLO tL OO oasrer | ye i | : 1 L070 REF i : _ ,200 - 085 | 400 REF 3.4 [5 6 {7 t fo 4 Nt | a 4 x 9 ; Ul L L 1 cos TYP = (Gs | 075 REF ; i 7 wo Spay | eg 18D ] ' | ; q10 Wh} hy can \ fl s i i 012 R \ 16 15 14 ~=(/13 [12 4 PLACES PIN 1 INDEX 050 TYP 045 TYP 20 in te eeeA T & T MELEC (I C) 62 D MM 0050026 0000332 9 mm T-46-23-15 M41256xx-10B, -12B, & -15B Dynamic RAM aaa a i OTT ORDERING INFORMATION Package Mode Part Number COMCODE : M41256DP-10B* (104382395 * PLCC Page M41256DP-12B 104370358 . M41256DP-15B 104370366 M41256PP-10B* 104375159 Plastic DIP Page M41256PP-12B 104375167 M41256PP-15B 104375175 M41256CP-10B* 104382239 Ceramic LCC Page M41256CP-12B 104382247 : M41256CP-15B 104382254 f M41256HP-10B* 104382320 F Ceramic DIP Page M41256HP-12B 104375092 : M41256HP-I5SB 104375100 M41256CN-10B* 104382213 Ceramic LCC | Nibble M41256CN-12B 104387618 M41256CN-15B 104382221 ; , M41256HN-10B* 104382312 i Ceramic DIP | Nibble M41256HN-12B 104375076 M41256HN-15B 104375084 * Limited Quantities 21 -AT&T MELEC (I ) 6c D go50026 0000333 Oo m= T= 7o- 23 - /S~ For additional information, contact your AT&T Account Manager, or call: AT&YP Technologies, 555 Union Boulevard, Dept. 50AL203140, Allentown, PA 18103 1-800-372-2447 In Europe, contact: . 0) AT&T Microelectronics, Freischiitzstrasse 92, 8000 Mtinchen 81, West Germany 4- Tel. 89/95 97 0 Telex 5 216 884 Printed in United States of America 1930 E-07 mo DS86-135MMOS