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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS90LV027A

SNLS026D –MARCH 2000–REVISED JUNE 2016

DS90LV027A LVDS Dual High Speed Differential Driver

1 Features

1• >600-Mbps (300 MHz) Switching Rates

• 0.3-ns Typical Differential Skew

• 0.7-ns Maximum Differential Skew

• 1.5-ns Maximum Propagation Delay

• 3.3-V Power Supply Design

• ±360-mV Differential Signaling

• Low Power Dissipation (46 mW at 3.3-V Static)

• Flow-Through Design Simplifies PCB Layout

• Interoperable With Existing 5-V LVDS Devices

• Power-Off Protection (Outputs in High Impedance)

• Conforms to TIA/EIA-644 Standard

• 8-Pin SOIC Package Saves Space

• Industrial Temperature Operating Range: −40°C

to 85°C

2 Applications

• Multi-Function Printers

• LVCMOS-to-LVDS Translation

• Building and Factory Automation

• Grid Infrastructure

3 Description

The DS90LV027A is a dual LVDS driver device

optimized for high data rate and low-power

applications. The device is designed to support data

rates in excess of 600 Mbps (300 MHz) using Low

Voltage Differential Signaling (LVDS) technology. The

DS90LV027A is a current mode driver allowing power

dissipation to remain low even at high frequency. In

addition, the short circuit fault current is also

minimized.

The device is in a 8-pin SOIC package. The

DS90LV027A has a flow-through design for easy

printed-circuit board (PCB) layout. The differential

driver outputs provides low EMI with its typical low

output swing of 360 mV. It is perfect for high-speed

transfer of clock and data. The DS90LV027A can be

paired with its companion dual line receiver, the

DS90LV028A, or with any of TI's LVDS receivers, to

provide a high-speed point-to-point LVDS interface.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

DS90LV027A SOIC (8) 4.90 mm × 3.91 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

space

Functional Diagrams

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions ...................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics .......................................... 5

6.6 Switching Characteristics.......................................... 5

6.7 Typical Characteristics.............................................. 6

7 Parameter Measurement Information .................. 9

8 Detailed Description............................................ 10

8.1 Overview................................................................. 10

8.2 Functional Block Diagrams ..................................... 10

8.3 Feature Description................................................. 11

8.4 Device Functional Modes........................................ 11

9 Application and Implementation ........................ 12

9.1 Application Information............................................ 12

9.2 Typical Application.................................................. 12

10 Power Supply Recommendations ..................... 13

11 Layout................................................................... 14

11.1 Layout Guidelines ................................................. 14

11.2 Layout Example .................................................... 14

12 Device and Documentation Support................. 15

12.1 Documentation Support ........................................ 15

12.2 Receiving Notification of Documentation Updates 15

12.3 Community Resources.......................................... 15

12.4 Trademarks........................................................... 15

12.5 Electrostatic Discharge Caution............................ 15

12.6 Glossary................................................................ 15

13 Mechanical, Packaging, and Orderable

Information........................................................... 15

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (April 2013) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

Changes from Revision B (April 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format ............................................................................................................. 1

VCC

DI 1

DI 2

GND D0- 2

D0+ 2

D0+ 1

D0- 11

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5 Pin Configuration and Functions

D Package

8-Pin SOIC

Top View

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

DI 2, 3 I TTL/CMOS driver input pins

DO+ 6, 7 O Noninverting LVDS driver output pin

DO– 5, 8 O Inverting LVDS driver output pin

GND 4 — Ground pin

VCC 1 — Positive power supply pin, 3.3 V ± 0.3 V

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Supply voltage, VCC –0.3 4 V

Input voltage, DI –0.3 3.6 V

Output voltage, DO± –0.3 3.9 V

Maximum package power dissipation at 25°C D package 1190 mW

Derate D package 9.5 mW/°C

above 25°C °C

Lead temperature range, soldering (4 s) 260 °C

Storage temperature, Tstg –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±8000

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

EIAJ, 0 Ω, 200 pF ±1000

IEC direct, 330 Ω, 150 pF ±4000

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

VCC Supply voltage 3 3.3 3.6 V

TAOperating free-air temperature –40 25 85 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages.

6.4 Thermal Information

THERMAL METRIC(1) DS90LV027A

UNITD (SOIC)

8 PINS

RθJA Junction-to-ambient thermal resistance Low-K thermal resistance(2) 212 °C/W

High-K thermal resistance(2) 112

RθJC(top) Junction-to-case (top) thermal resistance 69.1 °C/W

RθJB Junction-to-board thermal resistance 47.7 °C/W

ψJT Junction-to-top characterization parameter 15.2 °C/W

ψJB Junction-to-board characterization parameter 47.2 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W

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(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground

except VOD.

(2) The DS90LV027A is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers

outputs.

(3) All typicals are given for: VCC = 3.3 V and TA= 25°C.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)(1)(2)

PARAMETER TEST CONDITIONS MIN TYP(3) MAX UNIT

VOD Output differential voltage RL= 100 Ω(see Figure 15), DO+, DO−pins 250 360 450 mV

ΔVOD VOD magnitude change RL= 100 Ω(see Figure 15), DO+, DO−pins 1 35 mV

VOH Output high voltage RL= 100 Ω(see Figure 15), DO+, DO−pins 1.4 1.6 V

VOL Output low voltage RL= 100 Ω(see Figure 15), DO+, DO−pins 0.9 1.1 V

VOS Offset voltage RL= 100 Ω(see Figure 15), DO+, DO−pins 1.125 1.2 1.375 V

ΔVOS Offset magnitude change RL= 100 Ω(see Figure 15), DO+, DO−pins 0 3 25 mV

IOXD Power-off leakage VOUT = VCC or GND, VCC = 0 V, DO+, DO−pins ±1 ±10 μA

IOSD Output short-circuit current DO+, DO−pins –5.7 –8 mA

VIH Input high voltage DI pin 2 VCC V

VIL Input low voltage DI pin GND 0.8 V

IIH Input high current VIN = 3.3 V or 2.4 V, DI pin ±2 ±10 μA

IIL Input low current VIN = GND or 0.5 V, DI pin ±1 ±10 μA

VCL Input clamp voltage ICL =−18 mA, DI pin –1.5 –0.6 V

ICC Power supply current VIN = VCC or GND, VCC pin No load 8 14 mA

RL= 100 Ω14 20

(1) These parameters are ensured by design. The limits are based on statistical analysis of the device over PVT (process, voltage,

temperature) ranges.

(2) CLincludes probe and fixture capacitance.

(3) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO= 50 Ω, tr≤1 ns, tf≤1 ns (10%-90%).

(4) All typicals are given for: VCC = 3.3 V and TA= 25°C.

(5) tSKD1, |tPHLD −tPLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative

going edge of the same channel.

(6) tSKD2 is the Differential Channel to Channel Skew of any event on the same device.

(7) tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation

delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.

(8) tSKD4, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices

over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max −Min|

differential propagation delay.

(9) fMAX generator input conditions: tr= tf< 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% / 55%,

VOD > 250 mV, all channels switching.

6.6 Switching Characteristics

RL= 100 Ωand CL= 15 pF, see Figure 16 and Figure 17 (unless otherwise noted)(1)(2)(3)

PARAMETER TEST CONDITIONS MIN TYP(4) MAX UNIT

tPHLD Differential propagation delay high to low 0.3 0.8 1.5 ns

tPLHD Differential propagation delay low to high 0.3 1.1 1.5 ns

tSKD1 Differential pulse skew |tPHLD −tPLHD|(5) 0 0.3 0.7 ns

tSKD2 Channel to channel skew(6) 0 0.4 0.8 ns

tSKD3 Differential part to part skew(7) 0 1 ns

tSKD4 Differential part to part skew(8) 0 1.2 ns

tTLH Transition low to high time 0.2 0.5 1 ns

tTHL Transition high to low time 0.2 0.5 1 ns

fMAX Maximum operating frequency(9) 350 MHz

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6.7 Typical Characteristics

Figure 1. Output High Voltage

vs Power Supply Voltage Figure 2. Output Low Voltage

vs Power Supply Voltage

Figure 3. Output Short-Circuit Current

vs Power Supply Voltage

Figure 4. Differential Output Voltage

vs Power Supply Voltage

Figure 5. Differential Output Voltage

vs Load Resistor Figure 6. Offset Voltage

vs Power Supply Voltage

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Typical Characteristics (continued)

Figure 7. Power Supply Current

vs Power Supply Voltage Figure 8. Power Supply Current

vs Ambient Temperature

Figure 9. Differential Propagation Delay

vs Power Supply Voltage Figure 10. Differential Propagation Delay

vs Ambient Temperature

Figure 11. Differential Skew

vs Power Supply Voltage Figure 12. Differential Skew

vs Ambient Temperature

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Typical Characteristics (continued)

Figure 13. Transition Time

vs Power Supply Voltage Figure 14. Transition Time

vs Ambient Temperature

DO-

DO+

VDIFF

20 % 20 %

tTHL

80 % 80 %

0 V

VDIFF = (DO+) ± (DO-)

0 V

tPHLD

VOL

VOH

0 V

3 V

1.5 V

tPLH

0 V (Differential)

Generator D

50 Ÿ

DO-

DO+

VOD

VOS

RL / 2

DO-

DO+

DI D

2 V

0.8 V

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7 Parameter Measurement Information

Figure 15. Differential Driver DC Test Circuit

Figure 16. Differential Driver Propagation Delay and Transition Time Test Circuit

Figure 17. Differential Driver Propagation Delay and Transition Time Waveforms

DO 2-

DO+ 2

DI 2 D

DO 1-

DO+ 1

DI 1 D

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8 Detailed Description

8.1 Overview

LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as

is shown in Figure 19. This configuration provides a clean signaling environment for the fast edge rates of the

drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair

cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media

is in the range of 100 Ω. A termination resistor of 100 Ω(selected to match the media), and is placed as close to

the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into

a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver

configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as

well as ground shifting, noise margin limits, and total termination loading must be considered. The DS90LV027A

differential line driver is a balanced current source design. A current mode driver, generally speaking has a high

output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand

supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce

a logic state and in the other direction to produce the other logic state. The output current is typically 3.1 mA, a

minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode driver requires (as discussed above) that a

resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 19. AC or

unterminated configurations are not allowed. The 3.1-mA loop current develops a differential voltage of 310 mV

across the 100-Ωtermination resistor which the receiver detects with a 250-mV minimum differential noise

margin, (driven signal minus receiver threshold (250 mV – 100 mV = 150 mV). The signal is centered around 1.2

V (Driver Offset, VOS) with respect to ground as shown in Figure 18.

NOTE

The steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD)

and is typically 620 mV.

The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its

quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver

increases exponentially in most case from 20 MHz to 50 MHz. This is due to the overlap current that flows

between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed

current between its output without any substantial overlap current. This is similar to some ECL and PECL

devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires >80% less

current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing

RS-422 drivers.

8.2 Functional Block Diagrams

DIN

DOUT-

SINGLE-ENDED

DOUT+

DOUT+ ± DOUT-

DIFFERENTIAL OUTPUT

V0H

V0S (1.2V typical)

V0L

0V (DIFF.) 0V VSS

+V0D

-V0D

V0D

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8.3 Feature Description

8.3.1 LVDS Fail-Safe

This section addresses the common concerns of fail-safe biasing of LVDS interconnects, specifically looking at

the DS90LV027A driver outputs and the DS90LV028A receiver inputs.

The LVDS receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mV) to CMOS

logic levels. Due to the high gain and tight threshold of the receiver, take care to prevent noise from appearing as

a valid signal.

The internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing

fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated, or shorted receiver

inputs.

1. Open Input Pins: The DS90LV028A is a dual receiver device, and if an application requires only 1 receiver,

the unused channel inputs must be left OPEN. Do not tie unused receiver inputs to ground or any other

voltages. The input is biased by internal high value pullup and pulldown resistors to set the output to a HIGH

state. This internal circuitry ensures a HIGH, stable output state for open inputs.

2. Terminated Input: If the DS90LV027A driver is disconnected (cable unplugged), or if the DS90LV027A driver

is in a TRI-STATE or power-off condition, the receiver output is in a HIGH state again, even with the end of

cable 100-Ωtermination resistor across the input pins. The unplugged cable can become a floating antenna

which can pick up noise. If the cable picks up more than 10 mV of differential noise, the receiver may see the

noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a

balanced interconnect must be used. Twisted pair cable offers better balance than flat ribbon cable.

3. Shorted Inputs: If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0-V

differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported

across the common-mode range of the device (GND to 2.4 V). It is only supported with inputs shorted and no

external common-mode voltage applied.

External lower value pullup and pulldown resistors (for a stronger bias) may be used to boost fail-safe in the

presence of higher noise levels. The pullup and pulldown resistors must be in the 5-kΩto 15-kΩrange to

minimize loading and waveform distortion to the driver. The common-mode bias point must be set to

approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry.

Figure 18. Driver Output Levels

8.4 Device Functional Modes

Table 1 lists the functional modes of the DS90LV027A.

Table 1. Truth Table

INPUT OUTPUTS

DI DO+ DO–

L L H

H H L

DATA

INPUT RT

100:

DATA

OUTPUT

Any LVDS

Receiver

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DS90LV027A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of

the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and

the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise

isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.

General application guidelines and hints for LVDS drivers and receivers may be found in the following application

notes:

•LVDS Owner's Manual

•AN-808 Long Transmission Lines and Data Signal Quality

•AN-977 LVDS Signal Quality: Jitter Measurements Using Eye Patterns Test Report

•AN-971 An Overview of LVDS Technology

•AN-916 A Practical Guide To Cable Selection

•AN-805 Calculating Power Dissipation for Differential Line Drivers

•AN-903 A Comparison of Differential Termination Techniques

9.2 Typical Application

Figure 19. LVDS Application Schematic

9.2.1 Design Requirements

When using LVDS devices, it is important to remember to specify controlled impedance PCB traces, cable

assemblies, and connectors. All components of the transmission media must have a matched differential

impedance of about 100 Ω. They must not introduce major impedance discontinuities. Balanced cables (for

example, twisted pair) are usually better than unbalanced cables (ribbon cable) for noise reduction and signal

quality.

Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up

electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the LVDS receiver.

For cable distances < 0.5 M, most cables can be made to work effectively. For distances 0.5 M ≤d≤10 M,

CAT5 (Category 5) twisted pair cable works well, is readily available, and relatively inexpensive.

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Typical Application (continued)

9.2.2 Detailed Design Procedure

9.2.2.1 Probing LVDS Transmission Lines

Always use high impedance (>100 kΩ), low capacitance (<2 pF) scope probes with a wide bandwidth (1 GHz)

scope. Improper probing gives deceiving results.

A pseudo-random bit sequence (PRBS) of 29−1 bits was programmed into a function generator (Tektronix

HFS9009) and connected to the driver inputs through 50-Ωcables and SMB connectors. An oscilloscope

(Tektronix 11801B) was used to probe the resulting eye pattern, measured differentially at the input to the

receiver. A 100-Ωresistor was used to terminate the pair at the far end of the cable. The measurements were

taken at the far end of the cable, at the input of the receiver, and used for the jitter analysis for Figure 21. The

frequency of the input signal was increased until the measured jitter (ttcs) equaled 20% with respect to the unit

interval (ttui) for the particular cable length under test. Twenty percent jitter is a reasonable place to start with

many system designs. The data used was NRZ. Jitter was measured at the 0-V differential voltage of the

differential eye pattern.

The DS90LV027A and DS90LV028A can be evaluated using the new DS90LV047-048AEVM.

9.2.3 Application Curves

Figure 20. Power Supply Current

vs Frequency Figure 21. Data Rate

vs Cable Length

10 Power Supply Recommendations

Although the DS90LV027A draws very little power while at rest, at higher switching frequencies there is a

dynamic current component which increases the overall power consumption. The DS90LV027A power supply

connection must take this additional current consumption into consideration for maximum power requirements.

Decoupling Cap

(Bottom Layer)

DI 2

DI 1

VCC

GND DO- 2

DO+ 2

DO+ 1

DO- 1

DS90LV027A

ROUT2

ROUT1

GND

DS90LV028A

RIN2-

RIN2+

RIN1+

RIN1-

LVCMOS

Inputs

VCC

Decoupling Cap

(Bottom Layer)

Series Termination (optional)

LVCMOS

Outputs

Input Termination

(Required)

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11 Layout

11.1 Layout Guidelines

• Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, and TTL signals.

• Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. Best practice is to

place TTL and LVDS signals on different layers which are isolated by power or ground plane(s).

• Keep drivers and receivers as close to the (LVDS port side) connectors as possible.

11.2 Layout Example

Figure 22. Simplified DS90LV027A and DS90LV028A Layout

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•LVDS Owner's Manual

•AN-808 Long Transmission Lines and Data Signal Quality

•AN-977 LVDS Signal Quality: Jitter Measurements Using Eye Patterns Test Report

•AN-971 An Overview of LVDS Technology

•AN-916 A Practical Guide To Cable Selection

•AN-805 Calculating Power Dissipation for Differential Line Drivers

•AN-903 A Comparison of Differential Termination Techniques

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 16-Feb-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

DS90LV027ATM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LV27A

DS90LV027ATM/NOPB ACTIVE SOIC D 8 95 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LV27A

DS90LV027ATMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LV27A

DS90LV027ATMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LV27A

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

PACKAGE OPTION ADDENDUM

www.ti.com 16-Feb-2016

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DS90LV027ATMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

DS90LV027ATMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Feb-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DS90LV027ATMX SOIC D 8 2500 367.0 367.0 35.0

DS90LV027ATMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Feb-2016

Pack Materials-Page 2

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