1 of 6
19-6412; Rev 8/12
FEATURES
All-Silicon Timing Circuit
Three Independent Buffered Delays
Stable and Precise Over Temperature and
Voltage
Leading and Trailing Edge Precision
Preserves the Input Symmetry
Vapor Phase and IR Reflow Solderable
Available in Tape and Reel
Delays Specified Over Both Commercial
and Industrial Temperature Ranges
3V Operation
Recommended Replacement for DS1033
PIN ASSIGNMENT
PIN DESCRIPTION
IN1-IN3 - Input Signals
OUT1-OUT3 - Output Signals
VCC - +3V Supply
GND - Ground
DESCRIPTION
The DS1135L series is a low-power, 3V high-speed version of the popular DS1013, DS1033, and
DS1035 series.
The DS1135L series of delay lines have three independent logic buffered delays in a single package. The
device is our fastest 3-in-1 delay line. It is available in a 150-mil 8-pin SO.
The device features precise leading and trailing edge accuracy. It has the inherent reliability of an all-
silicon delay line solution.
Standard delay values are indicated in Table 1.
DS1135L
3V 3-in-1 High-Speed
Silicon
Delay Line
DS1135LZ 8-Pin SO (150 mils)
1
2
3
4
7
8
6
5
IN2
GND
IN1
VCC
OUT1
OUT2
OUT3
DS1135L
2 of 7
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (tPLH, tPHL) Table 1
PART NUMBER
DELAY PER
OUTPUT
(ns)
INITIAL
TOLERANCE
(Note 1)
TOLERANCE OVER
TEMP AND VOLTAGE
(Note 2)
0°C to +70°C
-40°C to +85°C
DS1135LZ-10+
10/10/10
±1.0ns
±2.0ns
±3.0ns
DS1135LZ-12+
12/12/12
±1.0ns
±2.0ns
±3.0ns
DS1135LZ-15+
15/15/15
±1.0ns
±2.5ns
±4.0ns
DS1135LZ-20+
20/20/20
±1.0ns
±2.5ns
±4.0ns
DS1135LZ-25+
25/25/25
±1.5ns
±3.0ns
±5.0ns
DS1135LZ-30+
30/30/30
±1.5ns
±3.0ns
±5.0ns
+Denotes a lead(Pb)-free/RoHS-compliant package.
NOTES:
1. Nominal conditions are +25°C and VCC = +3.3V.
2. Voltage range of 2.7V to 3.6V.
3. Delay accuracies are for both leading and trailing edges.
TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1135L.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected to the output. The DS1135L output taps
are selected and connected to the interval counter by a VHF switch control unit. All measurements are
fully automated with each instrument controlled by the computer over an IEEE 488 bus.
TIME DELAY
OUT
IN
ONE OF THREE
DS1135L
3 of 7
DS1135L TEST CIRCUIT Figure 2
PULSE
GENERATOR
UNIT UNDER
TEST
TAPS 1-3
START
50Ω
STOP
50Ω
OUT
3
IN
VHF
SWITCH
CONTROL
UNIT
TIME INTERVAL
COUNTER
DS1135L
4 of 7
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground -1.0V to +6.0 V
Short-Circuit Output Current 50mA for 1 second
Operating Temperature Range -40°C to +85°C
Storage Temperature Range -55°C to +125°C
Lead Temperature (soldering, 10 seconds) +300°C
Soldering Temperature (reflow) +260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V to 3.6V, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage
VCC
2.7
3.3
3.6
V
Active Current ICC
V
CC
= 3.6V,
period = 1µs
10 mA
High Level Input Voltage
VIH
2.0
VCC
+ 0.5
V
Low Level Input Voltage
VIL
-0.5
0.8
V
Input Leakage
IL
0V ≤ VI
≤ VCC
-1.0
+1.0
µA
High Level Output
Current
ICC
V
CC
= 2.7V,
VOH = 2V
-1.0 mA
Low Level Output
Current
ICC
V
CC
= 2.7V,
VOL = 0.4V
8 mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V to 3.6V, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Period
tPERIOD
2 (tWI
)
ns
Input Pulse Width tWI
100% of
Delay Value
ns
Input-to-Output Delay
tPLH
,
tPHL
See Table 1
ns
Output Rise or Fall Time
tOF, tOR
2.0
2.5
ns
Power-up Time
tPU
1
ms
2
CAPACITANCE
(TA = +25°C, unless otherwise noted.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance
CIN
10
pF
DS1135L
5 of 7
TEST CONDITIONS
Ambient Temperature: 25°C ± 3°C
Supply Voltage (VCC ): 3.3V ± 0.1V
Input Pulse:
High: 3.0V ± 0.1V
Low: 0.0V ± 0.1V
Source Impedance: 50Ω Max.
Rise and Fall Time: 3.0ns Max. — Measured between 0.6V and 2.4V.
Pulse Width: 500ns
Pulse Period: 1µs
Output Load Capacitance: 15pF
Output: Each output is loaded with the equivalent of one 74F04 input gate.
Data is measured at the 1.5V level on the rising and falling edges.
Note: The above conditions are for test only and do not restrict the devices under other data sheet
conditions.
NOTES:
1. All voltages are referenced to ground.
2. Power-up time is the time from the application of power to the time stable delays are being produced
at the output.
TIMING DIAGRAM
t
FALL
80%
t
RISE
20%
IN
OUT
1.5V
1.5V
t
WI
t
WI
PERIOD
1.5V
1.5V
1.5V
t
PLH
t
PHL
t
OF
t
OR
DS1135L
6 of 7
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge on the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the falling edge of the input
pulse and the 1.5V point on the falling edge of the output pulse.
ORDERING INFORMATION
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to
www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of
RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
8 SO S8+2 21-0041 90-0096
DS1135L
PACKAGE TYPE:
Z = SO (150MIL)
Dash Delay (NS)
Number
Time
10
10
12
12
15
15
20
20
25
25
30
30
DS1135L
7 of 7
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim
reserves the right to change the circuitry and specifications without notice at any time.The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
8/12
Removed the µSOP package; updated the Absolute Maximum
Ratings section; added the Package Information section
1, 2, 4, 6