EN6360QI 8A Synchronous Highly Integrated DC-DC Power SoC Description Features The EN6360QI is a Power System on a Chip (PowerSoC) DC to DC converter in a 68 pin QFN module. It offers highly efficient performance along with a rich and proven feature set that facilitate ease of use in systems that are sensitive to beat tones. The switching frequency can be synchronized to an external clock or other EN6360QIs. Other features include precision Enable threshold, pre-bias monotonic start-up, and parallel operation. * * * * The EN6360QI is specifically designed to meet the precise voltage and fast transient requirements of present and future highperformance, low-power processor, DSP, FPGA, memory boards and system level applications in distributed power architecture. The device's advanced circuit techniques, ultra high switching frequency, and proprietary integrated inductor technology deliver high-quality, ultra compact, non-isolated DC-DC conversion. * The Enpirion integrated inductor solution significantly helps to reduce noise. The complete power converter solution enhances productivity by offering greatly simplified board design, layout and manufacturing requirements. All Enpirion products are RoHS compliant and lead-free manufacturing environment compatible. * * * * * * * * Application * * * * Figure 1: BOM layout of EN6360QI solution for maximum 2 performance. Total Area 190 mm High efficiency, up to 96%. Excellent ripple and EMI performance. Up to 8A continuous operating current. 1.2 MHz operating frequency with ability to synchronize to an external clock source or serve as the primary source. External programmable Frequency between 0.9MHz and 1.5MHz for application tuning. 2% Output Voltage Accuracy over line, load, temp EN6360QI is a member of a family of devices between 1A to 12A load capacity with small total PCB footprints from 156mm2 and 227mm2. Precision Enable threshold for sequencing. Monotonic start-up with pre-bias. Programmable soft-start time. Soft Shutdown. Master/slave configuration for parallel operation. Thermal shutdown, over current, short circuit, and under-voltage protection. RoHS compliant, MSL level 3, 260C reflow. * * * Point of load regulation for low-power processors, multi-core processors, communication processor, DSPs, FPGAs, and ASICs Low voltage, distributed power architectures with 0.8, 1.0, 1.2, 2.5V, 3.3V, 5V or 6V rails Blade servers, RAID storage cards, LAN/SAN adapter cards, wireless base stations, industrial automation, test and measurement, embedded computing, communications, and printers High efficiency 12V intermediate bus architectures Beat frequency sensitive applications Ripple/Noise Sensitive Applications Beat frequency sensitive applications www.enpirion.com December 2010, Rev A EN6360QI Datasheet Schematic Ordering Information Part Number EN6360QI EN6360QI-E Temp Rating (C) Package -40 to +85 68-pin QFN T&R QFN Evaluation Board NC 6 NC 7 NC 8 NC 9 NC VSENSE SS EAOUT VFB M/S AGND AVIN ENABLE POK S_OUT 57 56 55 54 53 52 51 50 49 NC(SW) NC(XREF) NC(SW) 62 58 NC 63 FQADJ NC 64 59 NC 65 EN_PB NC 66 60 NC 45 NC 44 NC 43 PVIN 42 PVIN 41 PVIN 40 PVIN 10 39 PVIN NC 11 38 PVIN NC 12 37 PVIN NC 13 36 PVIN NC 14 35 PVIN 69 PGND 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VOUT VOUT VOUT NC NC(SW) NC(SW) PGND PGND PGND PGND PGND PGND PGND EN6360QI VOUT Figure 2: Simple Application Schematic for maximum performance. Unless otherwise specified, all passive components can be 0402 or smaller. 5 20 RB 4 NC VDDB VOUT FQADJ NC BGND 46 19 AGND 3 S_IN 47 VOUT PGND NC 48 Thermal Pad 18 PGND 2 VOUT 15nF R1 1 NC 17 VFB SS NC VOUT AVIN CA 16 2x22 F 1206 2x 47 F 1206 15 RA ENA 67 VOUT VOUT NC BGND PVIN VOUT VDDB VIN 68 0.1F 61 Pin Assignments (Top View) Figure 3: Pin Out Diagram (Top View) NOTE: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. Pin Description PIN 1-15, 25, 44-45, 64-68 16-24 NAME NC VOUT NC(SW) 26-27, 62-63 28-34 PGND 35-43 PVIN 46 VDDB 47 BGND FUNCTION NO CONNECT: These pins must be soldered to PCB but not be electrically connected to each other or to any external signal, voltage, or ground. These pins may be connected internally. Failure to follow this guideline may result in device damage. Regulated converter output. Connect to the load, and place output filter capacitor(s) between these pins and PGND pins 28-31. NO CONNECT: These pins are internally connected to the common switching node of the internal MOSFETs. They must be soldered to PCB but not be electrically connected to any external signal, ground, or voltage. Failure to follow this guideline may result in device damage. Input/Output power ground. Connect these pins to the ground electrode of the input and output filter capacitors. See VOUT and PVIN descriptions for more details. Input power supply. Connect to input power supply, place input filter capacitor(s) between these pins and PGND pins 32-34. Internal regulated voltage used for the internal control circuitry. Decouple with a 0.1uF capacitor to BGND for improved efficiency. See pin 46 description. Enpirion 2010 all rights reserved, E&OE Enpirion Confidential www.enpirion.com, Page 2 December 2010, Rev A PIN 48 NAME S_IN 49 S_OUT 50 POK 51 ENABLE 52 AVIN 53 54 AGND M/S 55 VFB 56 57 EAOUT SS 58 VSENSE 59 NC (XREF) 60 FQADJ 61 EN_PB 69 PGND EN6360QI Datasheet FUNCTION Digital Input. Depending on the M/S pin, this pin accepts either an input clock to phase lock the internal switching frequency or a S_OUT signal from another EN6360QI. Leave this pin floating if it is not used. Digital Output. Depending on the M/S pin, either a clock signal synchronous with the internal switching frequency or the PWM signal is output on this pin. Leave this pin floating if it is not used. POK is a logic high when VOUT is within -10% to +20% of the programmed output voltage. This pin has an internal pull-up resistor to AVIN with a nominal value of 94K ohms. This pin can sink a maximum 4mA. This is the Device Enable pin. Floating this pin or a high level enables the device while a low level disables the device. A voltage ramp from another power converter may be applied for precision Enable. Analog input voltage for the control circuits. Connect this pin to the input power supply (PVIN) at a quiet point. Can also be connected to an auxiliary supply within a voltage range that is sequencing. This is the quiet ground for the control circuits. This is a Ternary Input put. Floating the pin disables parallel operation. A low level configures the device as Master and a High level configures the device as a slave. This is the External Feedback input pin. A resistor divider connects from the output to AGND. The mid-point of the resistor divider is connected to VFB. (A feed-forward capacitor is required across the upper resistor.) The output voltage regulates so as to make the VFB node voltage = 0.600volt. Optional Error Amplifier output. Allows for customization of the control loop. A soft-start capacitor is connected between this pin and AGND. The value of the capacitor controls the soft-start interval. This pin senses the output voltage when the device is in the Back-feed (or Pre-bias) mode. NO CONNECT: Precision External voltage reference input. Feature is available in a separate part number. Application of external reference overrides the device's internal reference. Contact Enpirion for more information. This pin must have a resistor to AGND, which sets the free running frequency of the internal oscillator. This is the Enable Pre-Bias Input. When this pin is pulled high, the Device will support monotonic start-up under a pre-biased load. This pin is pulled high internally. Device thermal pad to be connected to the system GND plane for heatsinking purposes. See Layout Recommendations section. Enpirion 2010 all rights reserved, E&OE Enpirion Confidential www.enpirion.com, Page 3 December 2010, Rev A EN6360QI Datasheet Absolute Maximum Ratings PARAMETER SYMBOL MIN MAX UNITS Voltages on: PVIN, AVIN, VOUT -0.3 7.0 V Voltages on: EN, POK, M/S -0.3 VIN+0.3 V Voltages on: VFB, EXTREF, EAOUT, SS, S_IN, S_OUT, FQADJ -0.3 2.5 V -65 150 C 150 C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 C ESD Rating (based on Human Body Model) 2000 V ESD Rating (based on CDM) 500 V MAX UNITS Storage Temperature Range TSTG Maximum Operating Junction Temperature TJ-ABS Max Recommended Operating Conditions PARAMETER Input Voltage Range Output Voltage Range SYMBOL MIN VIN 2.5 6.6 V 0.60 VIN 0.05*ILOAD V VOUT Output Current 2 IOUT Operating Ambient Temperature TA - 40 8 A +85 C Thermal Characteristics PARAMETER SYMBOL TYP UNITS Thermal Resistance: Junction to Ambient (0 LFM) (Note 1) JA 16 C/W Thermal Resistance: Junction to Case (0 LFM) JC 1.0 C/W Thermal Shutdown TSD 150 C Thermal Shutdown Hysteresis TSDH 20 C Note 1: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high thermal conductivity boards. Note 2: See Table in "Resistor Programmable Frequency" section for allowable Vin, Vout, Switching Frequency. Enpirion 2010 all rights reserved, E&OE Enpirion Confidential www.enpirion.com, Page 4 December 2010, Rev A EN6360QI Datasheet Electrical Characteristics NOTE: VIN=6.6V over operating temperature range unless otherwise noted. Typical values are at TA = 25C. PARAMETER SYMBOL TEST CONDITIONS Operating Input Voltage VIN See Note 5. VFB Pin Voltage VVFB Internal voltage reference at: VIN = 5V, TA = 25C, ILOAD = 0 MIN TYP 2.5 MAX UNITS 6.6 V 0.594 0.600 0.606 V 0.588 0.600 0.612 V 0.2 A VFB Pin Voltage VVFB 2.5V VIN 6.6V 0A ILOAD 10A, TA = -40 to 85C VFB Pin Input Leakage Current IVFB VFB pin input leakage current Shut-Down Supply Current IS Power Supply current with Enable=0 1.5 mA Under Voltage Lock-out - VIN Rising VUVLOR Voltage above which UVLO is not asserted 2.2 V Under Voltage Lock-out - tVIN Falling VUVLOF Voltage below which UVLO is asserted 2.1 V Output Drop Out Voltage Resistance (Note 1) VDO RDO VINMIN - VOUT at Full load Input to Output Resistance 300 50 mV m Maximum Continuous Output Current IOUT_Max_SRC Maximum load current. See Note 1 and Note 5. 8 A Maximum Continuous Output Sinking Current IOUT_Max_SNK Maximum load current. See Note 1. 8 A Over Current Trip Level IOCP Sourcing current Switching Frequency FSW Operating frequency with FQADJ resistor = 4.42 k at 5Vin External SYNC Clock Frequency Lock Range FPLL_LOCK SYNC clock input frequency range S_IN Clock Amplitude - Low VS_IN_LO SYNC Clock Logic Level S_IN Clock Amplitude - High VS_IN_HI SYNC Clock Logic Level S_IN Clock Duty Cycle (PLL) DCS_INPLL S_IN Clock Duty Cycle (PWM) -0.2 16 A 0.9 1.2 1.5 MHz 0.9*Fsw Fsw 1.1*Fsw MHz 0.8 V 1.8 2.5 V M/S Pin Float or Low 20 80 % DCS_INPWM M/S Pin High 10 90 % Pre-Bias Level VPB Allowable pre-bias as a fraction of programmed output voltage for monotonic start up. Minimum prebias voltage = 300mV. 20 75 % Non-Monotonicity VPB_NM Allowable non-monotonicity under pre-bias start up VOUT Range for POK = High Enpirion 2010 all rights reserved, E&OE Range of output voltage as a fraction of programmed value when POK is asserted Enpirion Confidential 100 90 mV 120 % www.enpirion.com, Page 5 December 2010, Rev A PARAMETER EN6360QI Datasheet SYMBOL TEST CONDITIONS POK Deglitch Delay Falling edge deglitch delay after output crossing 90% level. FSW =1.0 MHz VPOK Logic Low level With 4mA current sink into POK pin MIN TYP MAX 62 UNITS us 0.4 V VPOK Logic high level VIN V POK Internal pull-up resistor 94 k +/-10 % Current Balance IOUT With 2-4 converters in parallel, the difference between nominal and actual current levels. VIN<50mV; RTRACE< 10 m, Iload= # converter * IMAX VOUT Rise Time Accuracy TRISE TRISE = CSS*65K; 10nF CSS 30nF; (See Notes 3, 4) -25 Enable Threshold VENABLE 2.375V VIN 6.6V 1.3 Disable Threshold VDISABLE Max voltage to ensure the converter is disabled Enable Pin Current IEN VIN = 6.6V M/S Ternary Pin Logic Low VT-LOW Tie pin to GND M/S Ternary Pin Logic Hi VT-HIGH Pull up to VIN through an external resistor REXT Ternary Pin Input Current ITERN VIN = 5.0V, REXT = 24.9k Binary Pin Logic Low Threshold VB-LOW ENABLE, S_IN Binary Pin Logic High Threshold VB-HIGH ENABLE, S_IN S_OUT Low Level VS_OUT_LOW S_OUT High Level VS_OUT_HIGH +25 V 0.8 TBD V 50 A 0 see Input Current below 100 V V A 0.8 1.8 V V 0.4 2.0 % V V Note 1: Maximum output current may need to be de-rated, based on operating condition, to meet TJ and headroom requirements. Note 2: POK threshold when VOUT is rising is nominally 92%. This threshold is 90% when VOUT is falling. After crossing the 90% level, there is a 256 clock cycle (~62us at 1 MHz) delay before POK is de-asserted. The 90% and 92% levels are nominal values. Expect these thresholds to vary by 3%. Note 3: Parameter not production tested but is guaranteed by design. Note 4: Rise time begins when AVIN > VUVLO and Enable=HIGH. Note 5: See Table in "Resistor Programmable Frequency" section for allowable Vin, Vout. Enpirion 2010 all rights reserved, E&OE Enpirion Confidential www.enpirion.com, Page 6 December 2010, Rev A EN6360QI Datasheet 100 100 95 95 90 90 85 85 Efficiency (%) Efficiency (%) Typical Performance Characteristics 80 75 70 80 75 70 65 65 60 60 55 55 50 50 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 Efficiency VIN = 3.3V, Vout = 2.5, 1.8, 1.2, 1.0 at Frequency = 1.00MHz Enpirion 2010 all rights reserved, E&OE 7 8 9 500 MHz BW Output Ripple: VIN = 5.0V, VOUT = 1.0V, Iout = 8A F/1206, COUT = 2x47 F/1206 CIN = 2 x47 20 MHz BW limit Output Ripple: VIN = 5.0V, VOUT = 2.4V, Iout = 8A F/1206, COUT = 2x47 F/1206 CIN = 2 x 47 6 Efficiency VIN = 5.0V,Vout=3.3, 2.5, 1.8, 1.2, 1.0 at Frequency = 1.00MHz 20 MHz BW limit Output Ripple: VIN = 5.0V, VOUT = 1.0V, Iout = 8A F/1206, COUT = 2x47 F/1206 CIN = 2 x 47 5 Load (Amps) Load (Amps) 500 MHz BW Output Ripple: VIN = 5.0V, VOUT = 2.4V, Iout = 8A CIN = 2 x 47 F/1206, COUT = 2x47 F/1206 Enpirion Confidential www.enpirion.com, Page 7 EN6360QI Power Up/Down at 8A (0.08 ) Load: VIN/VOUT = 5.0V/1.0V, 15nF soft-start capacitor, Ch.3: ENABLE, Ch.1: VOUT Power Up/Down into 8A (0.194 ) load: VIN/VOUT = 5.0V/2.4V, 15nF soft-start capacitor, Ch.3: ENABLE, Ch.1: VOUT Load Transient: VIN = 6.2V, VOUT = 1.5V Ch.1: VOUT, Ch.2: ILOAD 0 8A (slew rate 10A/S) F, COUT 2x47 F CIN 2x47 www.enpirion.com December 2010, Rev A EN6360QI Datasheet Functional Block Diagram Figure 4: Functional Block Diagram Functional DescriptionSynchronous Buck Converter The EN6360QI is a synchronous, programmable Buck power supply with integrated power MOSFET switches and integrated inductor. The switching supply uses voltage mode control and a low noise PWM topology. This provides superior impedance matching to ICs processed in sub 90nm process technologies. The nominal input voltage range is 2.50 - 6.6 volts. The output voltage is programmed using an external resistor divider network. The feedback control loop is a type IV design. Voltage-mode control and a low-noise PWM topology offers superior performance. The device is optimized for 6A Enpirion 2010 all rights reserved, E&OE with up to 8A continuous output current operation. Operating between 0.9MHz and 1.5MHz switching frequency enables the use of small-size input and output capacitors. The power supply has the following protection features: * Over-current protection with hiccup mode. * Short Circuit protection. * Thermal shutdown with hysteresis. * Under-voltage lockout circuit to disable the converter output when the input voltage is less than approximately 2.2V Enpirion Confidential www.enpirion.com, Page 9 December 2010, Rev A EN6360QI Datasheet The power supply further supports the following features: * Precision enable threshold * Soft-start and Soft-shutdown * Pre-Bias Start-up * Resistor Programmable Switching Frequency * Optional external Voltage Reference * Switching frequency phase lockable to an external oscillator/another PoL device. * Parallel operation * Power OK Precision Enable The Enable threshold is a precision Analog voltage rather than a digital logic threshold. A precision voltage reference and a comparator circuit are kept powered up even when Enable is de-asserted. Precision threshold along with a proper choice of soft-start capacitor helps to accurately sequence multiple power supplies in a system as desired. Soft-Start and Soft-Shutdown The SS pin in conjunction with a small external capacitor between this pin and AGND provides a soft-start function to limit in-rush current during device power-up. When the part is initially powered up, the output voltage is gradually ramped to its final value. The gradual output ramp is achieved by increasing the reference voltage to the error amplifier. A constant current flowing into the soft-start capacitor provides the reference voltage ramp. When the voltage on the soft-start capacitor reaches 0.60V, the output has reached its programmed voltage. The current source will continue, however, to charge the SS capacitor beyond 0.60V to about 1.5V in normal operation. The output ramp rate can be controlled by the choice of soft-start capacitor value. The Enable signal, internal to the device, is extended to allow soft-shutdown. In shutdown, the SS capacitor is discharged in a controlled manner. The output ramps down correspondingly and when the output voltage is essentially zero, the controller is turned off. Pre-Bias Start-up The EN6360QI supports the device start up into a pre-biased load. A proprietary circuit ensures the output voltage ramps up from the pre-bias value to the programmed output voltage. Start-up is guaranteed for pre-bias voltages in the range of 20% to 75% of the programmed output voltage with a minimum pre-bias voltage of 300mV. The Pre-Bias feature is engaged by use of the EN_PB pin. Please see Electrical Characteristics table for more details. Resistor Programmable Frequency The free running frequency of the oscillator may be altered by connecting a suitable value resistor from the pin FQADJ to AGND. Frequency can be tuned to optimize dynamic performance and efficiency. The table below shows the recommended RFQADJ values for optimum efficiency for a specific Vin/Vout combination and 8A load. Contact Enpirion Applications for more information. Recommended RFQADJ (K ) as a Function of VIN & VOUT VOUT VIN 3.3V 10% 5.0V 10% 6.0V 10% 0.8V 1.2V 1.5V 1.8V 2.5V 3.3V 3.57 3.57 3.57 3.57 3.57 3.57 4.99 4.99 4.99 5.49 5.49 5.49 5.49 5.49 5.49 NA 4.99 5.49 When the device is disabled, the soft-start capacitor is discharged before the controller is powered down. The EN6360, however, relies on the output load current as the primary path to discharge the output Enpirion 2010 all rights reserved, E&OE Enpirion Confidential www.enpirion.com, Page 10 December 2010, Rev A EN6360QI Datasheet External Voltage Reference (Optional) This feature is available in a separate part number. Contact Enpirion for more information. When a voltage greater than 0.6V is present at the EXTREF pin the device will detect the presence of the voltage and automatically switch to this voltage as the reference for voltage regulation. Bypassing the internal reference can be used to further improve overall DC set point accuracy and temperature drift associated with the internal reference. EN6360QI accepts a wide range of input references between 1.15 and 1.5V directly. Please contact Enpirion to ensure the appropriate EN6360QI device is selected for the specific band gap reference being applied. Phase-Lock Operation: With M/S pin floating or at a logical `0,' the internal switching clock of the DC/DC converter can be phase-locked to a clock signal applied to S_IN. When a clock signal is present at S_IN, an activity detector recognizes the presence of the clock signal and the internal oscillator phase locks to the external clock. The external clock could be the system clock or the output of another EN6360QI. A delayed version of the phase locked clock is output at S_OUT. The clock frequency should be within 20% of the free running frequency for guaranteed phase-lock. Multiple EN6360QI devices on a system board may be daisy chained to avoid beat frequency components. The device switching frequency can be adjusted with the resistor to FQADJ as well as by the external clock source for phase-lock. Master / Slave (Parallel) Operation: Two EN6360QI devices may be connected in a Master/Slave configuration to handle larger load currents. The Master device's switching clock may be phase-locked to an external clock source or another EN6360QI. The device is placed in Master mode by pulling the M/S pin low or in Slave mode by pulling M/S pin high. When this pin is in Float state, parallel operation is not possible. In master mode, the internal PWM signal is output on the S_OUT pin. This PWM signal from the Master Enpirion 2010 all rights reserved, E&OE is fed to the slave device at its S_IN input. The Slave device acts like an extension of the power FETs in the Master. The inductor in the slave prevents crow-bar currents from Master to slave due to timing delays. POK Operation The POK signals the output voltage is within the specified range. The POK signal is asserted high when the rising output voltage crosses 92% (nominal) of the programmed output voltage. POK is de-asserted low for 256 clock cycles (62us at 1MHz) after the falling output voltage crosses 90% (nominal) of the programmed voltage. POK remains asserted if the output voltage falls outside the range of 90% to 120% for a period of time less than the de-glitch time. POK is also de-asserted if the output voltage exceeds 120% of the programmed output. If the feedback loop is broken, POK will remain de-asserted (sensed output < 92% of programmed value!) but the actual output voltage will equal the input voltage. If however, there is a short across the PFET, and the feedback is in place, POK will be de-asserted as an over voltage condition. In this case, the power NFET is turned on resulting in a large input supply current. This in turn is expected to trip the upstream power supply powering the EN6360QI. The POK pin can sink up to 4mA. No pull-up resistor required; when POK is asserted high the output will be pulled up to PVIN. Over Voltage Protection If the output voltage exceeds 120% of the programmed value (as sensed at VFB pin), the low-side power FET is turned on. If the overvoltage condition is due to an input-to-output or a high-side power FET short, the turn-on of the low-side power FET will cause a large current draw from the input supply. This will likely cause the input voltage to drop, thus protecting the load. Over Current Protection The current limit function is achieved by sensing the current flowing through a sense PFET. When the sensed current exceeds the current limit, both power FETs are turned off Enpirion Confidential www.enpirion.com, Page 11 December 2010, Rev A EN6360QI Datasheet for the rest of the switching cycle. If the overcurrent condition is removed, the over-current protection circuit will re-enable PWM operation. If the over-current condition persists, the circuit will continue to protect the load. The OCP trip point is nominally set as specified in the Electrical Characteristics table. In the event the OCP circuit trips consistently in normal operation, the device enters a hiccup mode. The device is disabled for a short while and restarted with a normal soft-start. This cycle can continue indefinitely as long as the over current condition persists. temperature exceeds approximately 150C. Once the junction temperature drops by approx 20C, the converter will re-start with a normal soft-start. Input Under-Voltage Lock-Out When the input voltage is below a required voltage level (VUVHI) for normal operation, the converter switching is inhibited. The lock-out threshold has hysteresis to prevent chatter. Thus when the device is operating normally, the input voltage has to fall below the lower threshold (VUVLO) for the device to stop switching. Thermal Overload Protection Temperature sensing circuits in the controller will disable operation when the Junction Application Information / Layout Recommendation Soft-start Capacitor Selection The output voltage ramp time is controlled by the choice of the soft-start capacitor value. The ramp time is defined as the time from when the Enable signal crosses the threshold and the input voltage crosses the upper UVLO threshold to the time when the output voltage reaches 95% of the programmed value. This time is given by the following equation: TSS = Css* 65k (seconds) Output Voltage Programming and loop Compensation The EN6360QI output voltage is programmed using a simple resistor divider network. A phase lead capacitor plus a resistor are required for stabilizing the loop. Figure 5 shows the required components and the equations to calculate their values. The EN6360QI output voltage is determined by the voltage presented at the VFB pin. This voltage is set by way of a resistor divider between VOUT and AGND with the midpoint going to VFB. are required in parallel with upper resistor of the external feedback network (see Figure 5). Total compensation is optimized for use with 2X47F output capacitance and will result in a wide loop bandwidth and excellent load transient performance for most applications. Additional capacitance may be placed beyond the voltage sensing point outside the control loop. Voltage mode operation provides high noise immunity at light load. Further, Voltage mode control provides superior impedance matching to ICs processed in sub 90nm technologies. In some cases modifications to the compensation or output capacitance may be required to optimize device performance such as transient response, ripple, or hold-up time. The EN6360QI provides the capability to modify the control loop response to allow for customization for such applications. For more information, contact Enpirion Applications Engineering support. The EN6360QI uses a type IV compensation network. Most of this network is integrated. However a phase lead capacitor and a resistor Enpirion 2010 all rights reserved, E&OE Enpirion Confidential www.enpirion.com, Page 12 December 2010, Rev A EN6360QI Datasheet R A = 48,400 x V IN (R A /VIN in / V) 3.83 x10 - 6 RA CA = (C A /R A in F/) Round C A down to closest available value lower than the calculated value. RB = V FB x R A (VOUT - V FB ) V FB is 0.6V nominal Additional capacitance may be placed beyond the voltage sensing point outside the control loop. Low ESR, X5R or X7R ceramic capacitors are required. Y5V or equivalent dielectric formulations must not be used as these lose capacitance with frequency, temperature and bias voltage. Recommended Output Capacitors Description R1 = 15 k Figure 5: External feedback and compensation network Enable Operation With the device input power applied, the device automatically starts to operate with a normal soft-start, provided the input supply voltage is above the UVLO high threshold of ~2.2 volts. To start device operation under ENABLE control, the ENABLE pin has to be initially pulled low and subsequently pulled high when so desired. 1 In some applications, lower value ceramic capacitors maybe needed in parallel with the larger capacitors in order to provide high frequency decoupling. P/N Taiyo Yuden LMK316BJ476ML-T Murata GRM31CR60J476ME19L Taiyo Yuden JMK316BJ476ML-T Murata GRM21BR70J106KE76L Taiyo Yuden JMK212B7106KG-T Output ripple voltage is primarily determined by the aggregate output capacitor impedance. Placing multiple capacitors in parallel reduces the impedance and hence will result in lower ripple voltage. Input Capacitor Selection The EN6360QI requires between 40-50F of input capacitance. Low ESR ceramic capacitors are required with X5R or X7R dielectric formulation. Y5V or equivalent dielectric formulations must not be used as these lose capacitance with frequency, temperature and bias voltage. MFG 47uF, 10V, 20% X5R, 1206 (2 capacitors needed) 47uF, 6.3V, 20% X5R, 1206 (2 capacitors needed) 10uF, 6.3V, 10% X7R, 0805 (Optional 1 capacitor in parallel with 2x47uF) Z Total = 1 1 1 + + ... + Z1 Z 2 Zn Typical Ripple Voltages Output Capacitor Configuration Typical Output Ripple (mVp-p) (as measured on device evaluation board) 2 x 47 uF 20 MHz bandwidth limit <10mV Recommended Input Capacitors Description 22uF, 10V, 20% X5R, 1206 (2 capacitors needed) MFG P/N Murata GRM31CR61A226ME19L Taiyo Yuden LMK316BJ226ML-T Output Capacitor Selection The EN6360QI has been optimized for use with about 100F of output filter capacitance. Enpirion 2010 all rights reserved, E&OE Enpirion Confidential www.enpirion.com, Page 13 December 2010, Rev A EN6360QI Datasheet M/S (Master/Slave) Pin States Ternary Pin M/S is a Ternary pin. This pin can assume 3 states - A low state, a high state and a float state. Device operation is controlled by the state of the pin. The pins may be pulled to ground or left floating without any special care. However when pulling high, we recommend tying this pin to VIN with a series resistor. The resistor value may be optimized to reduce the current drawn by the pin by following the equations in 6. The resistance should not be too high as in that case the pin may not recognize the high state. M/S Pin Function Low This is the Master mode. Switching phase locked to S_IN external clock. S_OUT outputs a delayed version of internal PWM signal Float Parallel operation is not feasible. Switching phase locked to S_IN external clock. S_OUT outputs a delayed version of switching clock High This is the Slave mode. The S_IN signal drives directly the power FETs. S_OUT outputs a delayed version of S_IN Contact Enpirion Application support for parallel operation of multiple EN6360QIs for higher output currents. 2.5V R1 100k PIN To VIN REXT To Gates D1 Vf ~ 2V R3 7k R2 100k Maximum value of REXT= (VIN-2)*67k AGND Input pin current = (VIN -2)/REXT EV6360QI Figure 6: Selection of REXT to connect ternary pins to VIN Enpirion 2010 all rights reserved, E&OE Enpirion Confidential www.enpirion.com, Page 14 December 2010, Rev A EN6360QI Datasheet Layout Recommendation Figure 7: Critical Components and Layer 1 Copper for Minimum Footprint and Layer 2 Ground Plane Figure 7 above shows critical components and layer 1 traces of the recommended EN6360 layout for minimum footprint with ENABLE tied to VIN. Alternate ENABLE configurations, and other small signal pins need to be connected and routed according to specific customer application. Please see the Gerber files on the Enpirion website www.enpirion.com for exact dimensions and other layers. Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EN6360QI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EN6360QI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 2: The system ground plane referred to in recommendations 2 and 3 should be the first layer immediately below the surface layer. This ground plane should be continuous and uninterrupted below the converter and the input/output capacitors. Recommendation 3: The thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the path for heat dissipation from the converter. Recommendation 4: Multiple small vias (the same size as the thermal vias discussed in recommendation 3) should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. It is preferred to put these vias along the edge of the GND copper closest to the +V copper. These vias connect the input/output filter capacitors to the GND plane, and help reduce parasitic inductances in the input and output current loops. Recommendation 5: AVIN is the power supply for the small-signal control circuits. It should be connected to the input voltage at a quiet point. In Figure 7 this connection is made at the input capacitor. Enpirion 2010 all rights reserved, E&OE Enpirion Confidential www.enpirion.com, Page 15 December 2010, Rev A EN6360QI Datasheet Recommendation 6: The layer 1 metal under the device must not be more than shown in Figure 7. See the section regarding exposed metal on bottom of package. As with any switch-mode DC/DC converter, try not to run sensitive signal or control lines underneath the converter package on other layers. Recommendation 7: The VOUT sense point should be just after the last output filter capacitor. Keep the sense trace short in order to avoid noise coupling into the node. Recommendation 8: Keep RA, CA, RB, and R1 close to the VFB pin (see Figures 5 and 7). The VFB pin is a high-impedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect RB directly to the AGND pin instead of going through the GND plane. Design Considerations for Lead-Frame Based Modules Exposed Metal on Bottom of Package Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. However, they do require some special considerations. In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several small pads being exposed on the bottom of the package, as shown in Figure 8. Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board. The PCB top layer under the EN6360QI should be clear of any metal (copper pours, traces, or vias) except for the two thermal pads. The "grayed-out" area in Figure 8 represents the area that should be clear of any metal on the top layer of the PCB. Any layer 1 metal under the grayed-out area runs the risk of undesirable shorted connections even if it is covered by soldermask. Figure 9 shows the package dimensions. Figure 8: Lead-Frame exposed metal. Grey area highlights exposed metal that is not to be mechanically or electrically connected to the PCB. Enpirion 2010 all rights reserved, E&OE Enpirion Confidential www.enpirion.com, Page 16 December 2010, Rev A EN6360QI Datasheet Package and Mechanical Figure 9: EN6360QI Package Dimensions Contact Information Enpirion, Inc. 53 Frontage Road - Suite 210 Hampton, NJ 08827 USA Phone: 1.908.894.6000 Fax: 1.908.894.6090 Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment used in hazardous environment without the express written authority from Enpirion Enpirion 2010 all rights reserved, E&OE Enpirion Confidential www.enpirion.com, Page 17 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Altera: EN6360QI