Data Sheet Dual HDMI Receiver, Multiformat SDTV/HDTV Video Decoder, and RGB Graphics Digitizer ADV7441A FEATURES GENERAL DESCRIPTION Dual HDMI(R) 1.3 receiver HDMI support Deep color support xvYCC Enhanced colorimetry Gamut metadata 225 MHz HDMI receiver Repeater support High-bandwidth digital content protection (HDCP 1.3) S/PDIF (IEC60958-compatible) digital audio output Multichannel I2S audio output (up to 8 channels) Adaptive equalizer for cable lengths up to 30 meters Internal EDID RAM DVI 1.0 Multiformat decoder Four 10-bit analog-to-digital converters (ADCs) ADC sampling rates up to 170 MHz Mux with 12 analog input channels SCART fast blank sampling support NTSC/PAL/SECAM color standards support 525p-/625p-component progressive scan formats support 720p-/1080i-/1080p-component HD formats support Digitizes RGB graphics from VGA to UXGA rates (up to 1600 x 1200 at 60 Hz) VBI data slicer (including teletext) Analog-to-HDMI fast switching mode General Highly flexible output interface STDI function support standard identification 2 any-to-any, 3 x 3 color-space conversion matrices Programmable interrupt request output pins The ADV7441A is a high quality multiformat video decoder and graphics digitizer with an integrated 2:1 multiplexed HDMI receiver. APPLICATIONS Advanced TVs PDP HDTVs LCD TVs (HDTV ready) LCD/DLP(R) rear projection HDTVs CRT HDTVs LCoS(R) HDTVs Audio/video receivers (AVR) LCD/DLP front projectors HDTV STBs with PVR DVD recorders with progressive scan input support The ADV7441A contains two main processing sections. The first section is the standard definition processor (SDP), which processes all types of PAL, NTSC, and SECAM signals. The second section is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics. The CP also processes the video signals from the HDMI receiver. The ADV7441A can keep the HDCP link between a HDMI source and the selected HDMI port active in analog mode operation. This allows for fast switching between the analog and HDMI modes. As a decoder, the ADV7441A can convert PAL, NTSC, and SECAM composite or S-Video signals into a digital ITU-R BT.656 format. It can also decode a component RGB or YPrPb video signal into a digital YCrCb or RGB pixel output stream. The ADV7441A supports the 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i component video standards, as well as many other HD and SMPTE standards. SCART and overlay functionality are enabled by the ability of the ADV7441A to process CVBS and standard definition RGB signals simultaneously. As a graphics digitizer, the ADV7441A can digitize RGB graphics signals from VGA to UXGA rates and convert them to a digital RGB or YCrCb pixel output stream. The ADV7441A incorporates a dual-input HDMI-compatible receiver that supports HDTV formats up to 1080p and display resolutions up to UXGA. The reception of encrypted video is possible with the inclusion of HDCP. The inclusion of adaptive equalization in the HDMI receiver ensures robust operation of the interface with cable lengths up to 30 meters. The HDMI receiver has advanced audio functionality, including a mute controller that prevents audible extraneous noise in the audio output. To facilitate professional applications, where HDCP processing and decryption is not required, a derivative part of the ADV7441A is available. This allows users who are not HDCP adopters to purchase the ADV7441A (see the Ordering Guide section for details). Fabricated using an advanced CMOS process, the ADV7441A is available in a space-saving, 144-lead, surface-mount, RoHScompliant, plastic LQFP and is specified over the -40C to +85C temperature range. Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007-2012 Analog Devices, Inc. All rights reserved. ADV7441A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Component Processor Pixel Data Output Modes.................. 14 Applications ....................................................................................... 1 Composite and S-Video Processing ......................................... 14 General Description ......................................................................... 1 Component Video Processing .................................................. 15 Revision History ............................................................................... 2 RGB Graphics Processing ......................................................... 15 Functional Block Diagram .............................................................. 3 General Features ......................................................................... 15 Specifications..................................................................................... 4 Theory of Operation ...................................................................... 16 Electrical Characteristics ............................................................. 4 Analog Front End ....................................................................... 16 Video Specifications ..................................................................... 6 HDMI Receiver........................................................................... 16 Analog and HDMI Specifications .............................................. 7 Standard Definition Processor ................................................. 16 Timing Characteristics ................................................................ 8 Component Processor (CP) ...................................................... 17 Absolute Maximum Ratings .......................................................... 10 VBI Data Processor .................................................................... 17 Thermal Resistance .................................................................... 10 Pixel Output Formatting................................................................ 18 Package Thermal Performance ................................................. 10 Register Map Architecture ........................................................ 21 ESD Caution ................................................................................ 10 Typical Connection Diagram........................................................ 22 Pin Configuration and Function Descriptions ........................... 11 Recommended External Loop Filter Components ................ 23 Functional Overview ...................................................................... 14 ADV7441A Evaluation Platform.................................................. 24 Analog Front End ....................................................................... 14 Outline Dimensions ....................................................................... 25 HDMI Receiver ........................................................................... 14 Ordering Guide .......................................................................... 25 Standard Definition Processor Pixel Data Output Modes .... 14 REVISION HISTORY 2/12--Rev. G to Rev. H Deleted EVAL-ADV7441AFEZ_2 .................................... Universal Changes to ADV7441A Evaluation Platform Section ............... 24 5/11--Rev. F to Rev. G Added Endnote 10 (Table 1) ........................................................... 4 11/10--Rev. E to Rev. F Changes to Product Title and Features Section ............................ 1 Changes to Analog Front End Section......................................... 14 Changes to Ordering Guide .......................................................... 25 7/09--Rev. D to Rev. E Change to Pin No. Order for AIN1 to AIN12 Pins (Table 7) .......... 12 1/09--Rev. B to Rev. C Change to Figure 1 ............................................................................3 Changes to Static Performance Parameter and Power Requirements Parameter, Table 1 ....................................................4 Changes to HDMI Specifications Parameter, Table 3...................7 Change to Maximum Junction Temperature (TJ_MAX), Table 5 ....... 10 Changes to Package Thermal Performance Section .................. 10 Changes to ADV7441A Evaluation Platform Section ............... 24 Changes to Table 13 ....................................................................... 24 Changes to Figure 11...................................................................... 24 Changes to Ordering Guide .......................................................... 25 7/08--Revision B: Initial Version 4/09--Rev. C to Rev. D Changes to Package Thermal Performance Section .................. 10 Changes to VBI Data Processor Section...................................... 17 Rev. H | Page 2 of 28 RXB_2 RXB_1 RXB_0 RXB_C RXA_C RXA_2 RXA_1 RXA_0 ALSB SCL SDA FB SAMPLER PLL SAMPLER CONTROL INTERFACE I2C SYNC PROCESSING AND CLOCK GENERATION LLC GENERATION ADC 3 CLAMP YC AND CVBS MUX SOG SOY HS_IN/CS_IN VS_IN ADC 2 CLAMP ADC 1 EDID/REPEATER CONTROLLER DATA RECOVERY ALIGNMENT YPrPb INPUT MATRIX CLAMP RGB EQUALIZER MUX EQUALIZER 10 10 10 MDA MCL HS VS DE CONTROL CONTROL AND DATA CONTROL CONTROL HS/CS, VS HDMI DECODE ADC 0 HDCP ENGINE CLAMP XOR HDCP EEPROM CVBS FILTER 4:2:2 TO 4:4:4 CONVERSION 10 EMBEDDED SYNC VBI DATA RECOVERY CHROMA DEMOD FSC RECOVERY SYNC EXTRACT LUMA DIGITAL FINE CLAMP Y AUDIO PROCESSING MACROVISION DETECTION CHROMA DIGITAL FINE CLAMP C DECIMATION AND DOWNSAMPLING FILTERS CHC COLOR-SPACE CONVERTER CHA CHD CHB CHC CHB DATA PROCESSOR CHA PACKET/ INFOFRAME MEMORY MUX I2S LRCLK SCLK MCLKOUT SPDIF FREE RUN OUTPUT CONTROL SYNTHESIZED LLC CONTROL CHROMA RESAMPLE RESAMPLE CONTROL LINE LENGTH PREDICTOR GAIN CONTROL LUMA RESAMPLE GAIN CONTROL STANDARD AUTODETECTION GLOBAL CONTROL CHROMA FILTER LUMA FILTER CHROMA 2D COMB (0x04 MAX) CTI C-DNR AV CODE INSERTION LUMA 2D COMB (0x04 MAX) G B R FB OFFSET ADDER AV CODE INSERTION ANCILLARY DATA ACTIVE PEAK AND HSYNC DEPTH GAIN CONTROL STANDARD DEFINITION PROCESSOR NOISE AND CALIBRATION DIGITIAL FINE CLAMP MACROVISION AND CGMS DETECTION STANDARD IDENTIFICATION SYNC EXTRACT COMPONENT PROCESSOR SYNC SOURCE AND POLARITY DETECT PROGRAM DELAY ANCILLARY DATA FORMATTER DIGITAL PROCESSING BLOCK VBI DECODER VBI DATA PROCESSOR FAST BLANK OVERLAY CONTROL ANALOG INTERFACE PACKET PROCESSOR Rev. H | Page 3 of 28 10 10 10 SFL/ SYNC_OUT/ INT2 LLC HS/CS VS/FIELD DE/FIELD INT1 P20 TO P29 P10 TO P19 P0 TO P9 PIXEL DATA 06914-001 Figure 1. DDCA_SCL DDCA_SDA DDCB_SDA DDCB_SCL Data Sheet ADV7441A FUNCTIONAL BLOCK DIAGRAM OUTPUT FORMATTER ADV7441A Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is -40C to +85C, unless otherwise noted. Table 1. Parameter 1 STATIC PERFORMANCE 2 Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage 3 Symbol N INL DNL Test Conditions BSL 27 MHz (@ a 10-bit level) BSL 54 MHz (@ a 10-bit level) BSL 74 MHz (@ a 10-bit level) BSL 110 MHz (@ a 10-bit level) BSL 170 MHz (@ an 8-bit level) At 27 MHz (@ a 10-bit level) At 54 MHz (@ a 10-bit level) At 74 MHz (@ a 10-bit level) At 110 MHz (@ a 10-bit level) At 170 MHz (@ an 8-bit level) VIH HS_IN/CS_IN, VS_IN low trigger mode Input Low Voltage3 Input Current Input Capacitance 4 DIGITAL OUTPUTS Output High Voltage 5 Output Low Voltage5 High Impedance Leakage Current Output Capacitance4 POWER REQUIREMENTS4 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Analog Power Supply Terminator Power Supply Comparator Power Supply Digital Core Supply Current Digital I/O Supply Current Min Typ IIN DVDD DVDDIO PVDD AVDD TVDD CVDD IDVDD IDVDDIO ISOURCE = 0.4 mA ISINK = 3.2 mA -60 -10 Rev. H | Page 4 of 28 Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB 0.8 0.3 +60 +10 10 V V V V A A pF 0.4 10 20 V V A pF 1.98 3.63 1.89 1.89 3.465 1.89 198 290 218 305 358 414 48 80 50 136 192 151 V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA 2.4 1.62 2.97 1.71 1.71 3.135 1.71 CVBS input sampling @ 54 MHz 6, 7 Graphics RGB sampling @ 108 MHz6, 7 SCART RGB fast blank sampling @ 54 MHz6, 7 YPrPb 1080p sampling @ 148.5 MHz6, 7 HDMI RGB sampling @ 165 MHz7, 8, 9 HDMI RGB sampling @ 225 MHz7, 8, 9 CVBS input sampling @ 54 MHz6, 7 Graphics RGB sampling @ 108 MHz6, 7 SCART RGB fast blank sampling @ 54 MHz6, 7 YPrPb 1080p sampling @ 148.5 MHz6, 7 HDMI RGB sampling @ 165 MHz7, 8, 9 HDMI RGB sampling @ 225 MHz7, 8, 9, 10 10 2 0.7 CIN VOH VOL ILEAK COUT Unit -0.5/+2 -0.5/+2 -0.5/+1.5 -0.7/+2 -0.25/+0.5 -0.5/+0.5 0.5 0.5 0.5 -0.25/+0.2 VIL HS_IN/CS_IN, VS_IN low trigger mode Pin 21 (RESET) All input pins other than Pin 21 Max 1.8 3.3 1.8 1.8 3.3 1.8 140 141 152 203 242 242 16 17 16 42 17 20 Data Sheet Parameter 1 HDMI Comparators TMDS PLL and Equalizer Supply Current ADV7441A Symbol ICVDD Analog Supply Current 11 IAVDD Terminator Supply Current ITVDD Audio and Video PLL Supply Current IPVDD Power-Down Current Power-Up Time IPWRDN tPWRUP Test Conditions CVBS input sampling @ 54 MHz6, 7 Graphics RGB sampling @ 108 MHz6, 7 SCART RGB fast blank sampling @ 54 MHz6, 7 YPrPb 1080p sampling @ 148.5 MHz6, 7 HDMI RGB sampling @ 165 MHz7, 8, 9 HDMI RGB sampling @ 225 MHz7, 8, 9 CVBS input sampling @ 54 MHz6, 7 Graphics RGB sampling @ 108 MHz6, 7 SCART RGB fast blank sampling @ 54 MHz6, 7 YPrPb 1080p sampling @ 148.5 MHz6, 7 HDMI RGB sampling @ 165 MHz7, 8, 9 HDMI RGB sampling @ 225 MHz7, 8, 9 CVBS input sampling @ 54 MHz6, 7 Graphics RGB sampling @ 108 MHz6, 7 SCART RGB fast blank sampling @ 54 MHz6, 7 YPrPb 1080p sampling @ 148.5 MHz6, 7 HDMI RGB sampling @ 165 MHz7, 8, 9, 12 HDMI RGB sampling @ 225 MHz7, 8, 9, 12 CVBS input sampling @ 54 MHz6, 7 Graphics RGB sampling @ 108 MHz6, 7 SCART RGB fast blank sampling @ 54 MHz6, 7 YPrPb 1080p sampling @ 148.5 MHz6, 7 HDMI RGB sampling @ 165 MHz7, 8, 9 HDMI RGB sampling @ 225 MHz7, 8, 9 Min Typ 56 56 56 56 86 95 63 174 225 180 0 0 12 12 12 12 42 63 18 14 17 19 10 15 11.6 25 Max 83 83 83 83 111 125 115 312 388 318 2 2 20 20 20 20 97 100 24 22 24 25 20 21 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA ms The minimum/maximum specifications are guaranteed over the -40C to +85C temperature range (TMIN to TMAX). All ADC linearity tests were performed at input range full scale - 12.5% and at zero scale + 12.5%. Pin 1, Pin 105, Pin 106, and Pin 144 are 5 V tolerant. 4 Guaranteed by characterization. 5 The VOH and VOL levels were obtained using the default drive strength value (0x15) in User Map Register 0xF4. 6 Current measurements for analog inputs were made with HDMI/analog simultaneous mode disabled (User Map Register 0xBA, Bit 7, programmed with Value 0) and with no HDMI sources connected to the part. 7 Typical current measurements were taken with nominal voltage supply levels and an SMPTE bar video pattern input. Maximum current measurements were taken with maximum rating voltage supply levels and a MoireX video pattern input. 8 Current measurements for HDMI inputs were made with a source connected to the active HDMI port and with no source connected to the inactive HDMI port. 9 Audio stream is an uncompressed stereo audio sampling frequency of fS = 48 kHz, and MCLKOUT = 256 fS. 10 The maximum IDVDDIO value for the HDMI RGB sampling @ 225 MHz appears lower than expected. This is due to the 1080p 12-bit deep color mode input used during evaluation. In this mode, the input HDMI TMDS clock has a frequency of 222.75 MHz; however, the output pixel clock is stepped down to 148.5 MHz to account for the extra bits of data. DVDDIO power is proportional to the output pixel clock, therefore the stepping down of the output pixel clock data in 1080p 12-bit deep color mode results in lower than expected IDVDDIO. 11 Analog current measurements for CVBS were made with only ADC0 powered up; for RGB, with only ADC0, ADC1, and ADC2 powered up; for SCART FB, with all ADCs powered up; and for HDMI mode, with all ADCs powered off. 12 The terminator supply current may vary with the HDMI source in use. 1 2 3 Rev. H | Page 5 of 28 ADV7441A Data Sheet VIDEO SPECIFICATIONS AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is -40C to +85C, unless otherwise noted. Table 2. Parameter 1, 2 NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Symbol Test Conditions Min DP DG LNL CVBS input, modulated in five steps CVBS input, modulated in five steps CVBS input, five steps 0.3 0.6 0.8 Degrees % % Luma ramp Luma flat field 61.8 63.1 60 dB dB dB Analog Front-End Crosstalk LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range FSC Subcarrier Lock Range Color Lock-In Time Synchronization Depth Range 3 Color Burst Range Vertical Lock Time Horizontal Lock Time CHROMA SPECIFICATIONS Hue Accuracy Color Saturation Accuracy Color AGC Range Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy 1 2 3 Typ -5 40 Max +5 70 1.3 60 20 5 200 200 2 100 HUE CL_AC 1 1 The minimum/maximum specifications are guaranteed over the -40C to +85C temperature range (TMIN to TMAX). Guaranteed by characterization. Nominal synchronization depth is 300 mV at 100% of the synchronization depth range. Rev. H | Page 6 of 28 % Hz kHz Lines % % Fields Lines 0.5 0.1 0.3 Degrees % % % Degrees % 1 1 % % 5 CVBS, 0.5 V input CVBS, 0.5 V input Unit 400 Data Sheet ADV7441A ANALOG AND HDMI SPECIFICATIONS AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is -40C to +85C, unless otherwise noted. Table 3. Parameter 1, 2 CLAMP CIRCUITRY External Clamp Capacitor Input Impedance (Except Pin 74) Input Impedance of Pin 74 Common-Mode Level (CML) ADC Full-Scale Level ADC Zero-Scale Level ADC Dynamic Range Clamp Level (When Locked) Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current HDMI SPECIFICATIONS 3 Intrapair (Positive-to-Negative) Differential Input Skew 4, 5 Channel-to-Channel Differential Input Skew5, 6 Test Conditions Min Clamps switched off CVBS input SCART RGB input (R, G, B signals) S-Video input (Y signal) S-Video input (C signal) Component input (Y signal) Component input (Pr signal) Component input (Pb signal) PC RGB input (R, G, B signals) SDP only SDP only SDP only SDP only Typ Max 0.1 10 20 0.88 CML + 0.5 CML - 0.5 1 CML - 0.122 CML - 0.167 CML- 0.122 CML CML - 0.120 CML CML CML - 0.120 8 8 0.25 0.4 F M k V V V V V V V V V V V V mA mA A A 0.4 tbit 0.2 tpixel + 1.78 ns The minimum/maximum specifications are guaranteed over the -40C to +85C temperature range (TMIN to TMAX). Guaranteed by characterization. 3 Guaranteed by design. 4 tbit is 1/10 the pixel period tpixel. 5 The unit of measurement depends on the video applied and the TMDS clock frequency. 6 tpixel is the period of the TMDS clock. 1 2 Rev. H | Page 7 of 28 Unit ADV7441A Data Sheet TIMING CHARACTERISTICS AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is -40C to +85C, unless otherwise noted. Table 4. Parameter 1, 2 SYSTEM CLOCK AND CRYSTAL Crystal Nominal Frequency Crystal Frequency Stability Horizontal Sync Input Frequency LLC Frequency Range I2C PORTS (FAST MODE) 3 xCL Frequency 4 xCL Minimum Pulse Width High4 xCL Minimum Pulse Width Low4 Hold Time (Start Condition) Setup Time (Start Condition) xDA Setup Time4 xCL and xDA Rise Times4 xCL and xDA Fall Times4 Setup Time for Stop Condition I2C PORTS (NORMAL MODE)3 xCL Frequency4 xCL Minimum Pulse Width High4 xCL Minimum Pulse Width Low4 Hold Time (Start Condition) Setup Time (Start Condition) xDA Setup Time4 xCL and xDA Rise Times4 xCL and xDA Fall Times4 Setup Time for Stop Condition RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC Mark-Space Ratio DATA AND CONTROL OUTPUTS Data Output Transition Time SDR (SDP) 5 Data Output Transition Time SDR (CP) 6 I2S PORT (MASTER MODE) SCLK Mark-Space Ratio LRCLK Data Transition Time I2Sx Data Transition Time 7 Symbol Test Conditions Min Typ Max Unit 50 110 170 MHz ppm kHz MHz 28.6363 14.8 12.825 400 t1 t2 t3 t4 t5 t6 t7 t8 0.6 1.3 0.6 0.6 100 t1 t2 t3 t4 t5 t6 t7 t8 4 4.7 4 4.7 250 300 300 0.6 100 4 kHz s s s s ns ns ns s 5 ms 1000 300 t9:t10 45:55 t11 t12 t13 t14 Negative clock edge to start of valid data End of valid data to negative clock edge End of valid data to negative clock edge Negative clock edge to start of valid data t15:t16 t17 t18 t19 t20 End of valid data to negative SCLK edge Negative SCLK edge to start of valid data End of valid data to negative SCLK edge Negative SCLK edge to start of valid data 45:55 MCLKOUT Frequency 4.096 The minimum/maximum specifications are guaranteed over the -40C to +85C temperature range (TMIN to TMAX). Guaranteed by characterization. 3 Refers to all I2C pins (DDC and control port). 4 The prefix x refers to pin names beginning with S, DDCA_S, and DDCB_S. 5 SDP timing figures were obtained using the default drive strength value (0x15) in User Map Register 0xF4. 6 CP timing figures were obtained using the maximum drive strength value (0x3F) in User Map Register 0xF4. 7 The suffix x refers to pin names ending with 0, 1, 2, and 3. 1 2 Rev. H | Page 8 of 28 kHz s s s s ns ns ns s 55:45 % duty cycle 3.4 2.4 2 0.5 ns ns ns ns 55:45 10 10 5 5 24.576 % duty cycle ns ns ns ns MHz Data Sheet ADV7441A Timing Diagrams t5 t3 t3 xDA t6 t1 xCL t7 t4 t8 06914-002 t2 NOTES 1. THE PREFIX x REFERS TO PIN NAMES BEGINNING WITH S, DDCA_S, AND DDCB_S. Figure 2. I2C Timing t9 t10 LLC t11 06914-003 t12 P0 TO P29, VS, HS, DE/FIELD, SFL/SYNC_OUT Figure 3. Pixel Port and Control SDR Output Timing (SDP Core) t9 t10 LLC t13 06914-004 t14 P0 TO P29, VS, HS, DE/FIELD Figure 4. Pixel Port and Control SDR Output Timing (CP Core) t15 SCLK t16 t17 LRCLK t18 I2Sx LEFT-JUSTIFIED MODE t19 MSB MSB - 1 t20 t19 I2Sx MSB MSB - 1 t20 I2Sx RIGHT-JUSTIFIED MODE t19 MSB NOTES 1. THE SUFFIX x REFERS TO PIN NAMES ENDING WITH 0, 1, 2, AND 3. Figure 5. I2S Timing Rev. H | Page 9 of 28 LSB t20 06914-007 I2S MODE ADV7441A Data Sheet ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL PERFORMANCE Table 5. Parameter AVDD to AGND DVDD to DGND PVDD to PGND DVDDIO to DGND CVDD to CGND TVDD to TGND DVDDIO to AVDD DVDDIO to TVDD DVDDIO to DVDD CVDD to DVDD PVDD to DVDD AVDD to CVDD AVDD to PVDD AVDD to DVDD AVDD to TVDD TVDD to DVDD Digital Inputs Voltage to DGND Digital Outputs Voltage to DGND Analog Inputs Voltage to AGND Maximum Junction Temperature (TJ_MAX) Storage Temperature Range Infrared Reflow, Soldering (20 sec) Rating 2.2 V 2.2 V 2.2 V 4V 2.2 V 4V -0.3 V to +3.6 V -3.6 V to +3.6 V -2 V to +2 V -2 V to +0.3 V -2 V to +0.3 V -2 V to +2 V -2 V to +2 V -2 V to +0.3 V -3.6 V to +0.3 V -2 V to +2 V To reduce power consumption during ADV7441A operation, turn off unused ADCs. On a 4-layer PCB that includes a solid ground plane, the value of JA is 25.3C/W. However, due to variations within the PCB metal and, therefore, variations in PCB heat conductivity, the value of JA may differ for various PCBs. The most efficient measurement technique is to use the surface temperature of the package to estimate the die temperature because it is not affected by the variance associated with the value of JA. The maximum junction temperature (TJ_MAX) of 119C must not be exceeded. The following equation calculates the junction temperature using the measured surface temperature of the package and applies only when no heat sink is used on the device under test: DGND - 0.3 V to DVDDIO + 0.3 V AGND - 0.3 V to AVDD + 0.3 V 119C -65C to +150C 260C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Table 6. Package Type 144-Lead LQFP (ST-144) 1 TJ_MAX = TS + (JT x WTOTAL) DGND - 0.3 V to DVDDIO + 0.3 V Junction-to-package surface thermal resistance. JT1 1.62 Unit C/W where: TS is the surface temperature of the package expressed in degrees Celsius. JT is the junction-to-package surface thermal resistance. WTOTAL = {(AVDD x IAVDD) + (DVDD x IDVDD) + (DVDDIO x IDVDDIO) + (PVDD x IPVDD) + (CVDD x ICVDD) + (TVDD x ITVDD)}. The ADV7441A can be operated in ambient temperatures of up to +85C. However, in video modes where highest power is consumed and there is higher than nominal power supply voltages and worst-case video data, operation at these ambient temperatures may cause the junction temperature to exceed its maximum allowed value (119C). One way to avoid this is to restrict the ambient temperature to be below +79C. However, even if the ambient temperature is kept below +79C, the user still needs to observe the thermally efficient PCB design recommendations outlined in this section to ensure that the maximum allowed junction temperature is not exceeded in any video mode. Contact an Analog Devices, Inc., sales representative or a field applications engineer (FAE) for more information on package thermal performance. ESD CAUTION Rev. H | Page 10 of 28 Data Sheet ADV7441A 109 108 PIN 1 2 107 3 106 4 105 5 104 6 103 7 102 8 101 9 100 10 99 11 98 12 97 13 96 14 95 15 94 16 93 17 ADV7441A 92 18 TOP VIEW (Not to Scale) 91 19 90 20 89 21 88 22 87 23 86 24 85 25 84 26 83 27 82 28 81 29 80 30 79 31 78 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 EXT_CLK DGND DVDDIO LLC P22 P23 P24 P25 DGND DVDD P26 P27 P28 P29 VS_IN HS_IN/CS_IN DGND XTAL1 XTAL DVDDIO PVDD PGND ELPF PVDD PGND 43 73 41 74 36 42 75 35 39 76 40 77 34 38 32 33 TEST5 TEST4 DDCA_SDA DDCA_SCL CVDD CGND AUDIO_ELPF PVDD PGND AIN6 AIN12 SOY AIN5 AIN11 AIN4 AIN10 REFP TEST3 REFN TEST2 AVDD AGND CML REFOUT AVDD AGND AGND AIN3 AIN9 AIN2 AIN8 AIN1 AIN7 SOG FB TEST0 06914-005 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 1 37 DDCB_SDA SPDIF I2S0 I2S1 I2S2 I2S3 LRCLK SCLK MCLKOUT EXT_CLAMP SDA SCL ALSB DGND DVDDIO DE/FIELD HS/CS VS/FIELD INT1 SFL/SYNC_OUT/INT2 RESET DGND DVDD P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 DGND DVDDIO P10 143 144 DDCB_SCL DGND DVDD CVDD CGND TVDD RXB_2P RXB_2N TGND RXB_1P RXB_1N TGND RXB_0P RXB_0N TGND RXB_CP RXB_CN TVDD CGND CVDD RTERM TVDD RXA_2P RXA_2N TGND RXA_1P RXA_1N TGND RXA_0P RXA_0N TGND RXA_CP RXA_CN TVDD CGND CVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 6. Pin Configuration Table 7. Pin Function Descriptions Pin No. 14, 22, 34, 49, 56, 64, 143 82, 83, 87 69, 72, 100 103, 110, 126, 140 114, 117, 120, 130, 133, 136 15, 35, 50, 67 23, 57, 142 84, 88 68, 71, 101 104, 109, 125, 141 111, 123, 127, 139 74 73, 91, 108 89 Mnemonic DGND Type 1 G Description Digital Ground. AGND PGND CGND TGND G G G G Analog Ground. PLL Ground. Comparator Ground. Terminator Ground. DVDDIO DVDD AVDD PVDD CVDD TVDD FB TEST0, TEST3, TEST5 TEST2 P P P P P P I I O Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Analog Supply Voltage (1.8 V). Audio and Video PLL Supply Voltage (1.8 V). HDMI Comparator, TMDS PLL, and Equalizer Supply Voltage (1.8 V). Terminator Supply Voltage (3.3 V). Fast Blank. Fast switch overlay between CVBS and RGB analog signals. Test Pins. Do not connect. Test Pin. Do not connect. Rev. H | Page 11 of 28 ADV7441A Data Sheet Pin No. 107 77, 79, 81, 94, 96, 99, 76, 78, 80, 93, 95, 98 24 to 33, 36 to 47, 52 to 55, 58 to 61 19 Mnemonic TEST4 AIN1 to AIN12 Type 1 I/O I Description Test Pin. Do not connect. Analog Video Input Channels. P0 to P29 O Video Pixel Output Port. INT1 O 20 SFL/SYNC_OUT/INT2 O 17 HS/CS O 18 VS/FIELD O 16 DE/FIELD O 11 12 SDA SCL I/O I 13 21 ALSB RESET I I 51 65 LLC XTAL1 O O 66 XTAL I 70 102 85 86 90 92 63 ELPF AUDIO_ELPF REFOUT CML REFN REFP HS_IN/CS_IN O O O O O O I 62 VS_IN I 75 97 112 113 115 116 118 119 121 122 SOG SOY RXA_CN RXA_CP RXA_0N RXA_0P RXA_1N RXA_1P RXA_2N RXA_2P I I I I I I I I I I Interrupt Signal. Can be active low or active high. The set of events that triggers an interrupt is under user control. Subcarrier Frequency Lock (SFL). Contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. Sliced Synchronization Output Signal (SYNC_OUT). Available only in CP mode. Interrupt Signal (INT2). Horizontal Synchronization Output Signal (HS). Output by the SDP and CP. Composite Synchronization (CS). A single signal containing both horizontal and vertical synchronization pulses. Vertical Synchronization Output Signal (VS). Output by the SDP and CP. Field Synchronization Output Signal (FIELD). Field synchronization output signal in all interlaced video modes. Data Enable Signal (DE). Indicates active pixel data. Field Synchronization Output Signal (FIELD). Field synchronization output signal in all interlaced video modes. I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port. I2C Port Serial Clock Input. (Maximum clock rate of 400 kHz.) SCL is the clock line for the control port. This pin sets the second LSB of the slave address for each ADV7441A register map. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7441A circuitry. Line-Locked Output Clock for Pixel Data. Range is 13.5 MHz to 170 MHz. This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7441A. In crystal mode, the crystal must be a fundamental crystal. Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by an external 3.3 V 28.63636 MHz clock oscillator source to clock the ADV7441A. The recommended external loop filter must be connected to this ELPF pin. The recommended external loop filter must be connected to this AUDIO_ELPF pin. Internal Voltage Reference Output. Common-Mode Level for the Internal ADCs. Internal Voltage Reference Output. Internal Voltage Reference Output. HS Input Signal. Used in analog mode for 5-wire timing mode. CS Input Signal. Used in analog mode for 4-wire timing mode. For optimal performance, a 100 series resistor is recommended on the HS_IN/CS_IN pin. VS Input Signal. Used in analog mode for 5-wire timing mode. For optimal performance, a 100 series resistor is recommended on the VS_IN pin. Synchronization-on-Green Input. This pin is used in embedded synchronization mode. Synchronization-on-Luma Input. This pin is used in embedded synchronization mode. Digital Input Clock Complement of Port A in the HDMI Interface. Digital Input Clock True of Port A in the HDMI Interface. Digital Input Channel 0 Complement of Port A in the HDMI Interface. Digital Input Channel 0 True of Port A in the HDMI Interface. Digital Input Channel 1 Complement of Port A in the HDMI Interface. Digital Input Channel 1 True of Port A in the HDMI Interface. Digital Input Channel 2 Complement of Port A in the HDMI Interface. Digital Input Channel 2 True of Port A in the HDMI Interface. Rev. H | Page 12 of 28 Data Sheet ADV7441A Pin No. 128 129 131 132 134 135 137 138 106 1 105 144 2 3 4 5 6 7 8 9 10 Mnemonic RXB_CN RXB_CP RXB_0N RXB_0P RXB_1N RXB_1P RXB_2N RXB_2P DDCA_SDA DDCB_SDA DDCA_SCL DDCB_SCL SPDIF I2S0 I2S1 I2S2 I2S3 LRCLK SCLK MCLKOUT EXT_CLAMP Type 1 I I I I I I I I I/O I/O I I O O O O O O O O I 48 EXT_CLK I 124 RTERM I 1 Description Digital Input Clock Complement of Port B in the HDMI Interface. Digital Input Clock True of Port B in the HDMI Interface. Digital Input Channel 0 Complement of Port B in the HDMI Interface. Digital Input Channel 0 True of Port B in the HDMI Interface. Digital Input Channel 1 Complement of Port B in the HDMI Interface. Digital Input Channel 1 True of Port B in the HDMI Interface. Digital Input Channel 2 Complement of Port B in the HDMI Interface. Digital Input Channel 2 True of Port B in the HDMI Interface. HDCP Slave Serial Data Port A. HDCP Slave Serial Data Port B. HDCP Slave Serial Clock Port A. HDCP Slave Serial Clock Port B. SPDIF Digital Audio Output. I2S Audio for Channel 1 and Channel 2. I2S Audio for Channel 3 and Channel 4. I2S Audio for Channel 5 and Channel 6. I2S Audio for Channel 7 and Channel 8. Data Output Clock for Left and Right Audio Channels. Audio Serial Clock Output. Audio Master Clock Output. External Clamp Signal Input for External Clock and Clamp Mode. This is an optional mode of operation for the ADV7441A. Clock Input for External Clock and Clamp Mode. This is an optional mode of operation for the ADV7441A. Sets internal termination resistance. Connect this pin to TGND using a 500 resistor. G = ground, P = power, I = input, O = output. Rev. H | Page 13 of 28 ADV7441A Data Sheet FUNCTIONAL OVERVIEW The following overview provides a brief description of the functionality of the ADV7441A. More details are available in the Theory of Operation section. ANALOG FRONT END The analog front end of the ADV7441A provides four high quality 10-bit ADCs to enable 10-bit video decoding, a multiplexer with 12 analog input channels to enable multisource connection without the requirement of an external multiplexer, and four current and voltage clamp control loops to ensure that dc offsets are removed from the video signal. SCART functionality and standard definition RGB overlay with CVBS are controlled by the FB input. HDMI RECEIVER The ADV7441A is compatible with the HDMI specification. The ADV7441A supports all HDTV formats up to 1080p and all display resolutions up to UXGA (1600 x 1200 at 60 Hz). The device includes the following features: * * * * Adaptive front-end equalization for HDMI operation with cable lengths up to 30 meters Synchronization conditioning for higher performance in strenuous conditions Audio mute for removing extraneous noise Programmable data island packet interrupt generator STANDARD DEFINITION PROCESSOR PIXEL DATA OUTPUT MODES The ADV7441A features the following SDP output modes: * * * 8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS, VS, and FIELD 16-/20-bit YCrCb 4:2:2 with embedded time codes and/or HS, VS, and FIELD 24-/30-bit YCrCb 4:4:4 with embedded time codes and/or HS, VS, and FIELD COMPOSITE AND S-VIDEO PROCESSING The ADV7441A supports NTSC (M/J/4.43), PAL (B/D/I/G/H/ M/N/Nc/60), and SECAM (B/D/G/K/L) standards for CVBS and S-Video formats. Superadaptive 2D, 5-line comb filters for NTSC and PAL provide superior chrominance and luminance separation for composite video. The composite and S-Video processing functionalities also include fully automatic detection of switching among worldwide standards (PAL/NTSC/SECAM); automatic gain control (AGC) with white peak mode to ensure that the video is processed without compromising the video processing range; Adaptive Digital Line Length Tracking (ADLLTTM); and proprietary architecture for locking to weak, noisy, and unstable sources from VCRs and tuners. The IF filter block compensates for high frequency luma attenuation due to the tuner SAW filter. The ADV7441A also features chroma transient improvement (CTI) and luminance digital noise reduction (DNR), as well as teletext, closed captioning (CC), extended data service (EDS), and wide-screen signaling (WSS). It offers certified Macrovision(R) copy protection detection on composite and S-Video for all worldwide formats (PAL/NTSC/SECAM), and a copy generation management system (CGMS). Other features include 4x oversampling (54 MHz) for CVBS, S-Video, and YUV modes; line-locked clock output (LLC); vertical interval time codes (VITC); support for letterbox detection; a free-run output mode for stable timing when no video input is present; clocking from a single 28.63636 MHz crystal; and subcarrier frequency lock (SFL) output for downstream video encoders. In addition, the device has color controls for hue, brightness, saturation, and contrast and controls for Cr and Cb offsets. The ADV7441A also incorporates a vertical blanking interval data processor and a video programming system (VPS) on the device. The differential gain of the ADV7441A is 0.6% typical, and the differential phase is 0.3 typical. COMPONENT PROCESSOR PIXEL DATA OUTPUT MODES The ADV7441A features single data rate outputs as follows: * * * 8-/10-bit 4:2:2 YCrCb for 525i and 625i 16-/20-bit 4:2:2 YCrCb for all standards 24-/30-bit 4:4:4 YCrCb/RGB for all standards Rev. H | Page 14 of 28 Data Sheet ADV7441A COMPONENT VIDEO PROCESSING RGB GRAPHICS PROCESSING The ADV7441A supports 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other HDTV formats. It provides automatic adjustments for gain (contrast) and offset (brightness), as well as manual adjustment controls. Furthermore, the ADV7441A not only supports analog component YPrPb/RGB video formats with embedded synchronization or with separate HS, VS, and CS, but also supports YCrCb-to-RGB and RGB-to-YCrCb conversions by any-to-any, 3 x 3 color-space conversion matrices. The ADV7441A provides 170 MSPS conversion rate support of RGB input resolutions up to 1600 x 1200 at 60 Hz (UXGA) and automatic or manual clamp and gain controls for graphics models. In addition, the ADV7441A features brightness, saturation, and hue controls. Standard identification (STDI) enables detection of the component format at the system level, and a synchronization source polarity detector (SSPD) determines the source and polarity of the synchronization signals that accompany the input video. The RGB graphics processing functionality features contrast and brightness controls, automatic detection of synchronization source and polarity by the SSPD block, standard identification enabled by the STDI block, and user-defined pixel sampling support for nonstandard video sources. Additional RGB graphics processing features of the ADV7441A include the following: * * * Sampling PLL clock with 500 ps p-p jitter at 170 MSPS. 32-phase DLL support of optimum pixel clock sampling. Color-space conversion of RGB to YCrCb and decimation to a 4:2:2 format for videocentric back-end IC interfacing. Data enable (DE) output signal supplied for direct connection to the HDMI/DVI transmitter IC. Certified Macrovision copy protection detection is available on component formats (525i, 625i, 525p, and 625p). * When no video input is present, free-run output mode provides stable timing. GENERAL FEATURES The ADV7441A supports user-defined pixel sampling for nonstandard video sources and arbitrary pixel sampling for nonstandard video sources. The ADV7441A features HS, VS, and FIELD output signals with programmable position, polarity, and width. It also includes programmable interrupt request output pins, INT1 and INT2. The part offers low power consumption--1.8 V digital core, 1.8 V analog, and 3.3 V digital input/output--and a low power power-down mode. The ADV7441A operates over a temperature range of -40C to +85C and is available in a 144-lead, 20 mm x 20 mm, RoHScompliant LQFP. Rev. H | Page 15 of 28 ADV7441A Data Sheet THEORY OF OPERATION ANALOG FRONT END The ADV7441A analog front end comprises four 10-bit ADCs that digitize the analog video signal before applying it to the SDP or CP. The analog front end uses differential channels connected to each ADC to ensure high performance in mixed-signal applications. The analog front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7441A. Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping in either the CP or SDP. The ADCs are configured to run in 4x oversampling mode when decoding composite and S-Video inputs. For component 525i, 625i, 525p, and 625p sources, 2x oversampling is performed, but 4x oversampling is available for component 525i and 625i. All other video standards are 1x oversampled. Oversampling the video signals reduces the cost and complexity of external antialiasing (AA) filters, with the additional benefit of increasing the signal-to-noise ratio (SNR). The ADV7441A supports simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality. A combination of CVBS and RGB inputs can be mixed and output, as controlled by the I2C registers and the FB pin. HDMI RECEIVER The HDMI receiver on the ADV7441A incorporates active equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI cables, especially those with long lengths and high frequencies. Because the ADV7441A can provide equalization compensation for cable lengths up to 30 meters, it is capable of achieving robust receiver performance at even the highest HDMI data rates. With the inclusion of HDCP, displays can receive encrypted video content. The HDMI interface of the ADV7441A allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP 1.3 protocol. The HDMI receiver also offers advanced audio functionality. The receiver contains an audio mute controller that can detect a variety of selectable conditions that may result in audible extraneous noise in the audio output. Upon detection of these conditions, the audio data can be ramped to prevent audio clicks and pops. STANDARD DEFINITION PROCESSOR The SDP section is capable of decoding a large selection of baseband video signals in composite, S-Video, and YUV formats. The video standards supported by the SDP include PAL (B/D/I/G/H/60/M/N/Nc), NTSC (M/J/4.43), and SECAM (B/D/G/K/L). The ADV7441A automatically detects the video standard and processes it accordingly. The SDP has a five-line, superadaptive, 2D comb filter that provides superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without requiring user intervention. The SDP has an IF filter block that compensates for attenuation in the high frequency luma spectrum due to a tuner SAW filter. The SDP has specific luminance and chrominance parameter control for brightness, contrast, saturation, and hue. The ADV7441A implements the patented ADLLT algorithm to track varying video line lengths from sources such as VCRs. ADLLT enables the ADV7441A to track and decode poor quality video sources, such as VCRs, and noisy sources, such as tuner outputs, VCD players, and camcorders. The SDP also contains a CTI processor. This processor increases the edge rate on chroma transitions, resulting in a sharper video image. The SDP can process a variety of VBI data services, such as teletext, closed captioning (CC), wide-screen signaling (WSS), a video programming system (VPS), vertical interval time codes (VITC), a copy generation management system (CGMS), and an extended data service (XDS). The ADV7441A SDP section has a Macrovision 7.1 detection circuit that allows it to detect Type I, Type II, and Type III protection levels. The decoder is fully robust to all Macrovision signal inputs. Rev. H | Page 16 of 28 Data Sheet ADV7441A COMPONENT PROCESSOR (CP) The component processor section is capable of decoding and digitizing a wide range of component video formats in any color space. Component video standards supported by the CP are 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz, and many other standards. The CP section of the ADV7441A contains an AGC block. This block is followed by a digital clamp circuit that ensures that the video signal is clamped to the correct blanking level. Automatic adjustments within the CP include gain (contrast) and offset (brightness); however, manual adjustment controls are also supported. If no embedded synchronization is present, the video gain can be set manually. A fully programmable, any-to-any, 3 x 3 color-space converter is placed before the CP section. This enables YPrPb-to-RGB and RGB-to-YCrCb conversions. Many other standards of color space can be implemented using the color-space converter. A second fully programmable, any-to-any, 3 x 3 color-space converter is placed in the back end of the CP core. This colorspace converter features advanced color controls, such as contrast, saturation, brightness, and hue controls. The output section of the CP is highly flexible. It can be configured in single data rate (SDR) mode with one data packet per clock cycle. In SDR mode, a 16-/20-bit 4:2:2 or 24-/30-bit 4:4:4 output is possible. In these modes, HS/CS, VS/FIELD, and DE/FIELD (where applicable) timing reference signals are provided. The CP section contains circuitry to enable the detection of Macrovision-encoded YPrPb signals for 525i, 625i, 525p, and 625p. It is designed to be fully robust when decoding these types of signals. VBI DATA PROCESSOR VBI extraction of CGMS data is performed by the VBI data processor (VDP) section of the AD7441A for interlaced, progressive, and high definition scanning rates. The data extracted is read back over the I2C interface. For more detailed product information about the ADV7441A, contact a local Analog Devices sales representative or field applications engineer (FAE). Rev. H | Page 17 of 28 ADV7441A Data Sheet PIXEL OUTPUT FORMATTING Note that unused pins of the pixel output port are driven with a low voltage. Table 8. Standard Definition Pixel Port Modes (P19 to P0) Processor SDP Mode Mode 1 SDP Mode 2 SDP Mode 3 SDP Mode 4 SDP Mode 5 SDP Mode 6 Format Video output 8-bit 4:2:2 Video output 10-bit 4:2:2 Video output 16-bit 4:2:2 Video output 20-bit 4:2:2 Video output 24-bit 4:4:4 Video output 30-bit 4:4:4 19 18 17 16 15 14 YCrCb[7:0] Data Port Pins P[19:0] 13 12 11 10 9 8 7 6 5 4 3 2 1 YCrCb[9:0] Y[7:0] CrCb[7:0] Y[9:0] Cb[9:0] Y[7:0] Cb[7:0] Y[9:0] Cb[9:0] Table 9. Standard Definition Pixel Port Modes (P29 to P20) Processor SDP Mode Mode 1 SDP Mode 2 SDP Mode 3 SDP Mode 4 SDP Mode 5 SDP Mode 6 Format Video output 8-bit 4:2:2 Video output 10-bit 4:2:2 Video output 16-bit 4:2:2 Video output 20-bit 4:2:2 Video output 24-bit 4:4:4 Video output 30-bit 4:4:4 29 28 27 26 Data Port Pins P[29:20] 25 24 23 Cr[7:0] Cr[9:0] Rev. H | Page 18 of 28 22 21 20 0 Data Sheet ADV7441A Table 10. Component Processor Pixel Output Pin Map (P19 to P0) Processor 1 CP Mode Mode 1 CP Mode 2 CP Mode 3 CP Mode 4 CP Mode 5 CP Mode 6 CP Mode 7 CP Mode 8 CP Mode 9 CP Mode 10 CP Mode 11 CP Mode 12 CP Mode 13 CP Mode 14 CP Mode 15 CP Mode 16 CP Mode 17 CP Mode 18 CP Mode 19 Format Video output 8-bit 4:2:2 2 Video output 10-bit 4:2:22 Video output 12-bit 4:2:22 Video output 12-bit 4:2:22 Video output 12-bit 4:2:22 Video output 16-bit 4:2:2 3, 4 Video output 20-bit 4:2:23, 4 Video output 20-bit 4:2:223, 4 Video output 24-bit 4:2:23, 4 Video output 24-bit 4:2:23, 4 Video output 24-bit 4:2:23, 4 Video output 24-bit 4:4:43, 4 Video output 24-bit 4:4:43, 4 Video output 24-bit 4:4:43, 4 Video output 24-bit 4:4:43, 4 Video output 30-bit 4:4:43, 4 Video output 30-bit 4:4:43, 4 Video output 30-bit 4:4:43, 4 Video output 30-bit 4:2:23, 4 19 18 17 16 15 14 YCrCb[7:0] Output of Data Port Pins P[19:0] 13 12 11 10 9 8 7 6 5 4 3 2 1 0 YCrCb[9:0] YCrCb[11:2] YCrCb[11:4] YCrCb[11:4] CHA[7:0] (default data is Y[7:0]) CHA[9:0] (default data is Y[9:0]) CHA[9:2] (default data is Y[9:2]) Y[11:2] YCrCb[3:0] CHB/CHC[7:0] (default data is Cr/Cb[7:0]) CHB/CHC[9:0] (default data is Cr/Cb[9:0]) CHB/CHC[9:2] (default data is Cr/Cb[9:2]) CrCb[11:2] Y[11:4] Y[11:4] CHA[7:0] (default data is G[7:0] or Y[7:0]) CHA[7:0] (default data is G[7:0] or Y[7:0]) CHC[7:0] (default data is B[7:0] or Cb[7:0]) CHC[7:0] (default data is B[7:0] or Cb[7:0]) CHA[9:0] (default data is G[9:0] or Y[9:0]) CHA[9:0] (default data is G[9:0] or Y[9:0]) CrCb[11:4] Y[3:0] CrCb[3:0] CHB[7:0] (default data is R[7:0] or Cr[7:0]) CHC[7:0] (default data is B[7:0] or Cb[7:0]) CHA[7:0] (default data is G[7:0] or Y[7:0]) CHB[7:0] (default data is R[7:0] or Cr[7:0]) CHB[9:0] (default data is R[9:0] or Cr[9:0]) CHC[9:0] (default data is B[9:0] or Cb[9:0]) CHC[9:0] (default data is B[9:0] or Cb[9:0]) CHA[9:0] (default data is G[9:0] or Y[9:0]) CHC[9:0] (default data is B[9:0] or Cb[9:0]) CHB[9:0] (default data is R[9:0] or Cr[9:0]) The CP processor uses the digitizer or HDMI as input. Maximum pixel clock rate of 54 MHz. 3 Maximum pixel clock rate of 170 MHz for analog digitizer. 4 Maximum pixel clock rate of 165 MHz for HDMI. 1 2 Rev. H | Page 19 of 28 ADV7441A Data Sheet Table 11. Component Processor Pixel Output Pin Map (P29 to P20) Processor 1 CP Mode Mode 1 CP Mode 2 CP Mode 3 CP Mode 4 CP Mode 5 CP Mode 6 CP Mode 7 CP Mode 8 CP Mode 9 CP Mode 10 CP Mode 11 CP Mode 12 CP Mode 13 CP Mode 14 CP Mode 15 CP Mode 16 CP Mode 17 CP Mode 18 CP Mode 19 Format Video output 8-bit 4:2:2 2 Video output 10-bit 4:2:22 Video output 12-bit 4:2:22 Video output 12-bit 4:2:22 Video output 12-bit 4:2:22 Video output 16-bit 4:2:2 3, 4 Video output 20-bit 4:2:23, 4 Video output 20-bit 4:2:23, 4 Video output 24-bit 4:2:23, 4 Video output 24-bit 4:2:23, 4 Video output 24-bit 4:2:23, 4 Video output 24-bit 4:4:43, 4 Video output 24-bit 4:4:43, 4 Video output 24-bit 4:4:43, 4 Video output 24-bit 4:4:43, 4 Video output 30-bit 4:4:43, 4 Video output 30-bit 4:4:43, 4 Video output 30-bit 4:4:43, 4 Video output 30-bit 4:2:23, 4 29 28 27 Output of Data Port Pins P[29:20] 26 25 24 23 22 YCrCb[1:0] YCrCb[3:0] Y[1:0] CrCb[1:0] CrCb[1:0] Y[1:0] CrCb[3:0] Y[3:0] CrCb[11:4] CHC[7:0] (for example, B[7:0] or Cb[7:0]) CHB[7:0] (for example, R[7:0] or Cr[7:0]) CHB[7:0] (for example, R[7:0] or Cr[7:0]) CHA[7:0] (for example, G[7:0] or Y[7:0]) CHC[9:0] (for example, B[9:0] or Cb[9:0]) CHB[9:0] (for example, R[9:0] or Cr[9:0]) CHB[9:0] (for example, R[9:0] or Cr[9:0]) CHA[9:0] (for example, G[9:0] or Y[9:0]) The CP processor uses the digitizer or HDMI as input. Maximum pixel clock rate of 54 MHz. Maximum pixel clock rate of 170 MHz for analog digitizer. 4 Maximum pixel clock rate of 165 MHz for HDMI. 1 2 3 Rev. H | Page 20 of 28 21 20 Data Sheet ADV7441A REGISTER MAP ARCHITECTURE The ADV7441A registers are controlled via a 2-wire serial (I2C-compatible) interface. The ADV7441A has eight maps, each with a unique I2C address. The state of the ALSB pin (Pin 13) sets Bit 2 of each register map address in Table 12. Table 12. Register Map Addresses Register Map User Map User Map 1 User Map 2 VDP Map Reserved Map HDMI Map Repeater KSV Map EDID Map Default Address with ALSB = Low 0x40 0x44 0x60 0x48 0x4C 0x68 0x64 0x6C Default Address with ALSB = High 0x42 0x46 0x62 0x4A 0x4E 0x6A 0x66 0x6E Location Where Address Can Be Programmed N/A User Map 2, Register 0xEB User Map, Register 0x0E User Map 2, Register 0xEC User Map 2, Register 0xEA User Map 2, Register 0xEF User Map 2, Register 0xED User Map 2, Register 0xEE Programmable Address Not programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable USER MAP USER MAP 1 USER MAP 2 VDP MAP SA: 0x40 SA: PROGRAMMABLE SA: PROGRAMMABLE SA: PROGRAMMABLE SCL SA: PROGRAMMABLE SA: PROGRAMMABLE SA: PROGRAMMABLE SA: PROGRAMMABLE HDMI MAP EDID MAP REPEATER KSV MAP RESERVED MAP Figure 7. Register Map Access Through the Main I2C Port Rev. H | Page 21 of 28 06914-008 SDA ADV7441A Data Sheet 06914-009 TYPICAL CONNECTION DIAGRAM Figure 8. Typical Connection Diagram Rev. H | Page 22 of 28 Data Sheet ADV7441A RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS Note that the external loop filter components for the ELPF and AUDIO_ELPF pins should be placed as close as possible to the respective pins. The recommended component values are specified in Figure 9 and Figure 10. ELPF 70 AUDIO_ELPF 102 PVDD = 1.8V 1.5k 80nF Figure 9. ELPF Components 8nF PVDD = 1.8V Figure 10. AUDIO_ELPF Components Rev. H | Page 23 of 28 06914-011 82nF 10nF 06914-010 1.69k ADV7441A Data Sheet ADV7441A EVALUATION PLATFORM The back end of the platform can be connected to a specially developed video output board from Analog Devices. This modular board features an Analog Devices encoder and an Analog Devices HDMI transmitter. Analog Devices has developed an advanced TV (ATV) evaluation platform for the ADV7441A decoder. The evaluation platform consists of a motherboard and two daughterboards. The motherboard features a Xilinx FPGA for digital processing and muxing functions. The motherboard also features three AD9742 devices (12-bit DACs) from Analog Devices. This allows the user to drive a VGA monitor with just the motherboard and front-end board. The front end of the platform consists of an ADV7441 evaluation board (EVAL-ADV7441AFEZ_1). This evaluation board contains an ADV7441A decoder (see Table 13 for details). The evaluation board feeds the digital outputs from the ADV7441A decoder to the FPGA on the motherboard. Table 13. Front-End Modular Board Details Front-End Modular Board Model EVAL-ADV7441AFEZ_1 On-Board Decoder ADV7441ABSTZ-170 HDCP License Required Yes AUDIO 96-PIN CONNECTOR ATV MOTHERBOARD VIDEO INPUT BOARD EVAL-ADV7441AFEZ_x VGA OUTPUT Xilinx FPGA AVI 168-PIN CONNECTOR ADV7441A DECODER ANALOG AND DIGITAL VIDEO INPUTS AVO 168-PIN CONNECTOR VIDEO OUTPUT BOARD CVBS ADV7341 HDMI YPrPb Figure 11. Functional Block Diagram of Evaluation Platform Rev. H | Page 24 of 28 Y/C 06914-012 AD9889B Data Sheet ADV7441A OUTLINE DIMENSIONS 0.75 0.60 0.45 22.20 22.00 SQ 21.80 1.60 MAX 109 144 1 108 PIN 1 20.20 20.00 SQ 19.80 TOP VIEW (PINS DOWN) 0.15 0.05 0.20 0.09 7 3.5 0 SEATING PLANE 73 36 0.08 COPLANARITY 72 37 VIEW A VIEW A ROTATED 90 CCW 0.50 BSC LEAD PITCH 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BFB 051706-A 1.45 1.40 1.35 Figure 12. 144-Lead Low Profile Quad Flat Package [LQFP] (ST-144) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADV7441ABSTZ-170 ADV7441ABSTZ-110 ADV7441ABSTZ-5P EVAL-ADV7441AFEZ_1 Notes 2 2 3, 4 2, 5, 6 Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description 144-Lead Low Profile Quad Flat Package [LQFP] 144-Lead Low Profile Quad Flat Package [LQFP] 144-Lead Low Profile Quad Flat Package [LQFP] Front-End Evaluation Board Package Option ST-144 ST-144 ST-144 Z = RoHS Compliant Part. This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC, for licensing requirements) to purchase any components with internal HDCP keys. 3 Speed grade: 5 = 170 MHz. HDCP functionality: P = no HDCP functionality (professional version). 4 Professional version for non-HDCP encrypted applications. Purchaser is not required to be an HDCP adopter. 5 Front-end board for the ATV evaluation platform, fitted with ADV7441ABSTZ-170 decoder. See the ADV7441A Evaluation Platform section for details on the evaluation platform. 6 An ATV motherboard is also required to process the ADV7441A digital outputs and achieve video output. An ATV video output board is optional to evaluate performance through an HDMI Tx and video encoder. 1 2 Rev. H | Page 25 of 28 ADV7441A Data Sheet NOTES Rev. H | Page 26 of 28 Data Sheet ADV7441A NOTES Rev. H | Page 27 of 28 ADV7441A Data Sheet NOTES I2C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors). HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. (c)2007-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06914-0-2/12(H) Rev. H | Page 28 of 28